Lines Matching +full:tegra186 +full:- +full:dc
1 // SPDX-License-Identifier: GPL-2.0-only
18 #include "virt-dma.h"
68 * struct tegra_adma_chip_data - Tegra chip specific data
102 * struct tegra_adma_chan_regs - Tegra ADMA channel registers
115 * struct tegra_adma_desc - Tegra ADMA descriptor to manage transfer requests.
126 * struct tegra_adma_chan - Tegra ADMA channel information
148 * struct tegra_adma - Tegra ADMA controller information
170 writel(val, tdma->base_addr + tdma->cdata->global_reg_offset + reg); in tdma_write()
175 return readl(tdma->base_addr + tdma->cdata->global_reg_offset + reg); in tdma_read()
180 writel(val, tdc->chan_addr + reg); in tdma_ch_write()
185 return readl(tdc->chan_addr + reg); in tdma_ch_read()
188 static inline struct tegra_adma_chan *to_tegra_adma_chan(struct dma_chan *dc) in to_tegra_adma_chan() argument
190 return container_of(dc, struct tegra_adma_chan, vc.chan); in to_tegra_adma_chan()
201 return tdc->tdma->dev; in tdc2dev()
209 static int tegra_adma_slave_config(struct dma_chan *dc, in tegra_adma_slave_config() argument
212 struct tegra_adma_chan *tdc = to_tegra_adma_chan(dc); in tegra_adma_slave_config()
214 memcpy(&tdc->sconfig, sconfig, sizeof(*sconfig)); in tegra_adma_slave_config()
225 tdma_write(tdma, tdma->cdata->ch_base_offset + tdma->cdata->global_int_clear, 0x1); in tegra_adma_init()
232 tdma->base_addr + in tegra_adma_init()
233 tdma->cdata->global_reg_offset + in tegra_adma_init()
248 struct tegra_adma *tdma = tdc->tdma; in tegra_adma_request_alloc()
249 unsigned int sreq_index = tdc->sreq_index; in tegra_adma_request_alloc()
251 if (tdc->sreq_reserved) in tegra_adma_request_alloc()
252 return tdc->sreq_dir == direction ? 0 : -EINVAL; in tegra_adma_request_alloc()
254 if (sreq_index > tdma->cdata->ch_req_max) { in tegra_adma_request_alloc()
255 dev_err(tdma->dev, "invalid DMA request\n"); in tegra_adma_request_alloc()
256 return -EINVAL; in tegra_adma_request_alloc()
261 if (test_and_set_bit(sreq_index, &tdma->tx_requests_reserved)) { in tegra_adma_request_alloc()
262 dev_err(tdma->dev, "DMA request reserved\n"); in tegra_adma_request_alloc()
263 return -EINVAL; in tegra_adma_request_alloc()
268 if (test_and_set_bit(sreq_index, &tdma->rx_requests_reserved)) { in tegra_adma_request_alloc()
269 dev_err(tdma->dev, "DMA request reserved\n"); in tegra_adma_request_alloc()
270 return -EINVAL; in tegra_adma_request_alloc()
275 dev_WARN(tdma->dev, "channel %s has invalid transfer type\n", in tegra_adma_request_alloc()
276 dma_chan_name(&tdc->vc.chan)); in tegra_adma_request_alloc()
277 return -EINVAL; in tegra_adma_request_alloc()
280 tdc->sreq_dir = direction; in tegra_adma_request_alloc()
281 tdc->sreq_reserved = true; in tegra_adma_request_alloc()
288 struct tegra_adma *tdma = tdc->tdma; in tegra_adma_request_free()
290 if (!tdc->sreq_reserved) in tegra_adma_request_free()
293 switch (tdc->sreq_dir) { in tegra_adma_request_free()
295 clear_bit(tdc->sreq_index, &tdma->tx_requests_reserved); in tegra_adma_request_free()
299 clear_bit(tdc->sreq_index, &tdma->rx_requests_reserved); in tegra_adma_request_free()
303 dev_WARN(tdma->dev, "channel %s has invalid transfer type\n", in tegra_adma_request_free()
304 dma_chan_name(&tdc->vc.chan)); in tegra_adma_request_free()
308 tdc->sreq_reserved = false; in tegra_adma_request_free()
338 if (readx_poll_timeout_atomic(readl, tdc->chan_addr + ADMA_CH_STATUS, in tegra_adma_stop()
345 kfree(tdc->desc); in tegra_adma_stop()
346 tdc->desc = NULL; in tegra_adma_stop()
351 struct virt_dma_desc *vd = vchan_next_desc(&tdc->vc); in tegra_adma_start()
358 list_del(&vd->node); in tegra_adma_start()
360 desc = to_tegra_adma_desc(&vd->tx); in tegra_adma_start()
367 ch_regs = &desc->ch_regs; in tegra_adma_start()
369 tdc->tx_buf_pos = 0; in tegra_adma_start()
370 tdc->tx_buf_count = 0; in tegra_adma_start()
371 tdma_ch_write(tdc, ADMA_CH_TC, ch_regs->tc); in tegra_adma_start()
372 tdma_ch_write(tdc, ADMA_CH_CTRL, ch_regs->ctrl); in tegra_adma_start()
373 tdma_ch_write(tdc, ADMA_CH_LOWER_SRC_ADDR, ch_regs->src_addr); in tegra_adma_start()
374 tdma_ch_write(tdc, ADMA_CH_LOWER_TRG_ADDR, ch_regs->trg_addr); in tegra_adma_start()
375 tdma_ch_write(tdc, ADMA_CH_FIFO_CTRL, ch_regs->fifo_ctrl); in tegra_adma_start()
376 tdma_ch_write(tdc, ADMA_CH_CONFIG, ch_regs->config); in tegra_adma_start()
381 tdc->desc = desc; in tegra_adma_start()
386 struct tegra_adma_desc *desc = tdc->desc; in tegra_adma_get_residue()
394 if (pos < tdc->tx_buf_pos) in tegra_adma_get_residue()
395 tdc->tx_buf_count += pos + (max - tdc->tx_buf_pos); in tegra_adma_get_residue()
397 tdc->tx_buf_count += pos - tdc->tx_buf_pos; in tegra_adma_get_residue()
399 periods_remaining = tdc->tx_buf_count % desc->num_periods; in tegra_adma_get_residue()
400 tdc->tx_buf_pos = pos; in tegra_adma_get_residue()
402 return desc->buf_len - (periods_remaining * desc->period_len); in tegra_adma_get_residue()
410 spin_lock(&tdc->vc.lock); in tegra_adma_isr()
413 if (status == 0 || !tdc->desc) { in tegra_adma_isr()
414 spin_unlock(&tdc->vc.lock); in tegra_adma_isr()
418 vchan_cyclic_callback(&tdc->desc->vd); in tegra_adma_isr()
420 spin_unlock(&tdc->vc.lock); in tegra_adma_isr()
425 static void tegra_adma_issue_pending(struct dma_chan *dc) in tegra_adma_issue_pending() argument
427 struct tegra_adma_chan *tdc = to_tegra_adma_chan(dc); in tegra_adma_issue_pending()
430 spin_lock_irqsave(&tdc->vc.lock, flags); in tegra_adma_issue_pending()
432 if (vchan_issue_pending(&tdc->vc)) { in tegra_adma_issue_pending()
433 if (!tdc->desc) in tegra_adma_issue_pending()
437 spin_unlock_irqrestore(&tdc->vc.lock, flags); in tegra_adma_issue_pending()
450 static int tegra_adma_pause(struct dma_chan *dc) in tegra_adma_pause() argument
452 struct tegra_adma_chan *tdc = to_tegra_adma_chan(dc); in tegra_adma_pause()
453 struct tegra_adma_desc *desc = tdc->desc; in tegra_adma_pause()
454 struct tegra_adma_chan_regs *ch_regs = &desc->ch_regs; in tegra_adma_pause()
457 ch_regs->ctrl = tdma_ch_read(tdc, ADMA_CH_CTRL); in tegra_adma_pause()
458 ch_regs->ctrl |= (1 << ADMA_CH_CTRL_XFER_PAUSE_SHIFT); in tegra_adma_pause()
459 tdma_ch_write(tdc, ADMA_CH_CTRL, ch_regs->ctrl); in tegra_adma_pause()
461 while (dcnt-- && !tegra_adma_is_paused(tdc)) in tegra_adma_pause()
466 return -EBUSY; in tegra_adma_pause()
472 static int tegra_adma_resume(struct dma_chan *dc) in tegra_adma_resume() argument
474 struct tegra_adma_chan *tdc = to_tegra_adma_chan(dc); in tegra_adma_resume()
475 struct tegra_adma_desc *desc = tdc->desc; in tegra_adma_resume()
476 struct tegra_adma_chan_regs *ch_regs = &desc->ch_regs; in tegra_adma_resume()
478 ch_regs->ctrl = tdma_ch_read(tdc, ADMA_CH_CTRL); in tegra_adma_resume()
479 ch_regs->ctrl &= ~(1 << ADMA_CH_CTRL_XFER_PAUSE_SHIFT); in tegra_adma_resume()
480 tdma_ch_write(tdc, ADMA_CH_CTRL, ch_regs->ctrl); in tegra_adma_resume()
485 static int tegra_adma_terminate_all(struct dma_chan *dc) in tegra_adma_terminate_all() argument
487 struct tegra_adma_chan *tdc = to_tegra_adma_chan(dc); in tegra_adma_terminate_all()
491 spin_lock_irqsave(&tdc->vc.lock, flags); in tegra_adma_terminate_all()
493 if (tdc->desc) in tegra_adma_terminate_all()
497 vchan_get_all_descriptors(&tdc->vc, &head); in tegra_adma_terminate_all()
498 spin_unlock_irqrestore(&tdc->vc.lock, flags); in tegra_adma_terminate_all()
499 vchan_dma_desc_free_list(&tdc->vc, &head); in tegra_adma_terminate_all()
504 static enum dma_status tegra_adma_tx_status(struct dma_chan *dc, in tegra_adma_tx_status() argument
508 struct tegra_adma_chan *tdc = to_tegra_adma_chan(dc); in tegra_adma_tx_status()
515 ret = dma_cookie_status(dc, cookie, txstate); in tegra_adma_tx_status()
519 spin_lock_irqsave(&tdc->vc.lock, flags); in tegra_adma_tx_status()
521 vd = vchan_find_desc(&tdc->vc, cookie); in tegra_adma_tx_status()
523 desc = to_tegra_adma_desc(&vd->tx); in tegra_adma_tx_status()
524 residual = desc->ch_regs.tc; in tegra_adma_tx_status()
525 } else if (tdc->desc && tdc->desc->vd.tx.cookie == cookie) { in tegra_adma_tx_status()
531 spin_unlock_irqrestore(&tdc->vc.lock, flags); in tegra_adma_tx_status()
551 return (burst_size - 1) << ADMA_CH_CONFIG_BURST_SIZE_SHIFT; in tegra186_adma_get_burst_config()
559 struct tegra_adma_chan_regs *ch_regs = &desc->ch_regs; in tegra_adma_set_xfer_params()
560 const struct tegra_adma_chip_data *cdata = tdc->tdma->cdata; in tegra_adma_set_xfer_params()
563 if (desc->num_periods > ADMA_CH_CONFIG_MAX_BUFS) in tegra_adma_set_xfer_params()
564 return -EINVAL; in tegra_adma_set_xfer_params()
570 burst_size = tdc->sconfig.dst_maxburst; in tegra_adma_set_xfer_params()
571 ch_regs->config = ADMA_CH_CONFIG_SRC_BUF(desc->num_periods - 1); in tegra_adma_set_xfer_params()
572 ch_regs->ctrl = ADMA_CH_REG_FIELD_VAL(tdc->sreq_index, in tegra_adma_set_xfer_params()
573 cdata->ch_req_mask, in tegra_adma_set_xfer_params()
574 cdata->ch_req_tx_shift); in tegra_adma_set_xfer_params()
575 ch_regs->src_addr = buf_addr; in tegra_adma_set_xfer_params()
581 burst_size = tdc->sconfig.src_maxburst; in tegra_adma_set_xfer_params()
582 ch_regs->config = ADMA_CH_CONFIG_TRG_BUF(desc->num_periods - 1); in tegra_adma_set_xfer_params()
583 ch_regs->ctrl = ADMA_CH_REG_FIELD_VAL(tdc->sreq_index, in tegra_adma_set_xfer_params()
584 cdata->ch_req_mask, in tegra_adma_set_xfer_params()
585 cdata->ch_req_rx_shift); in tegra_adma_set_xfer_params()
586 ch_regs->trg_addr = buf_addr; in tegra_adma_set_xfer_params()
591 return -EINVAL; in tegra_adma_set_xfer_params()
594 ch_regs->ctrl |= ADMA_CH_CTRL_DIR(adma_dir) | in tegra_adma_set_xfer_params()
597 ch_regs->config |= cdata->adma_get_burst_config(burst_size); in tegra_adma_set_xfer_params()
598 ch_regs->config |= ADMA_CH_CONFIG_WEIGHT_FOR_WRR(1); in tegra_adma_set_xfer_params()
599 if (cdata->has_outstanding_reqs) in tegra_adma_set_xfer_params()
600 ch_regs->config |= TEGRA186_ADMA_CH_CONFIG_OUTSTANDING_REQS(8); in tegra_adma_set_xfer_params()
613 if (tdc->sreq_index > cdata->sreq_index_offset) in tegra_adma_set_xfer_params()
614 ch_regs->fifo_ctrl = in tegra_adma_set_xfer_params()
615 ADMA_CH_REG_FIELD_VAL(2, cdata->ch_fifo_size_mask, in tegra_adma_set_xfer_params()
618 ch_regs->fifo_ctrl = in tegra_adma_set_xfer_params()
619 ADMA_CH_REG_FIELD_VAL(3, cdata->ch_fifo_size_mask, in tegra_adma_set_xfer_params()
622 ch_regs->tc = desc->period_len & ADMA_CH_TC_COUNT_MASK; in tegra_adma_set_xfer_params()
628 struct dma_chan *dc, dma_addr_t buf_addr, size_t buf_len, in tegra_adma_prep_dma_cyclic() argument
632 struct tegra_adma_chan *tdc = to_tegra_adma_chan(dc); in tegra_adma_prep_dma_cyclic()
654 desc->buf_len = buf_len; in tegra_adma_prep_dma_cyclic()
655 desc->period_len = period_len; in tegra_adma_prep_dma_cyclic()
656 desc->num_periods = buf_len / period_len; in tegra_adma_prep_dma_cyclic()
663 return vchan_tx_prep(&tdc->vc, &desc->vd, flags); in tegra_adma_prep_dma_cyclic()
666 static int tegra_adma_alloc_chan_resources(struct dma_chan *dc) in tegra_adma_alloc_chan_resources() argument
668 struct tegra_adma_chan *tdc = to_tegra_adma_chan(dc); in tegra_adma_alloc_chan_resources()
671 ret = request_irq(tdc->irq, tegra_adma_isr, 0, dma_chan_name(dc), tdc); in tegra_adma_alloc_chan_resources()
674 dma_chan_name(dc)); in tegra_adma_alloc_chan_resources()
680 free_irq(tdc->irq, tdc); in tegra_adma_alloc_chan_resources()
684 dma_cookie_init(&tdc->vc.chan); in tegra_adma_alloc_chan_resources()
689 static void tegra_adma_free_chan_resources(struct dma_chan *dc) in tegra_adma_free_chan_resources() argument
691 struct tegra_adma_chan *tdc = to_tegra_adma_chan(dc); in tegra_adma_free_chan_resources()
693 tegra_adma_terminate_all(dc); in tegra_adma_free_chan_resources()
694 vchan_free_chan_resources(&tdc->vc); in tegra_adma_free_chan_resources()
695 tasklet_kill(&tdc->vc.task); in tegra_adma_free_chan_resources()
696 free_irq(tdc->irq, tdc); in tegra_adma_free_chan_resources()
699 tdc->sreq_index = 0; in tegra_adma_free_chan_resources()
700 tdc->sreq_dir = DMA_TRANS_NONE; in tegra_adma_free_chan_resources()
706 struct tegra_adma *tdma = ofdma->of_dma_data; in tegra_dma_of_xlate()
711 if (dma_spec->args_count != 1) in tegra_dma_of_xlate()
714 sreq_index = dma_spec->args[0]; in tegra_dma_of_xlate()
717 dev_err(tdma->dev, "DMA request must not be 0\n"); in tegra_dma_of_xlate()
721 chan = dma_get_any_slave_channel(&tdma->dma_dev); in tegra_dma_of_xlate()
726 tdc->sreq_index = sreq_index; in tegra_dma_of_xlate()
738 tdma->global_cmd = tdma_read(tdma, ADMA_GLOBAL_CMD); in tegra_adma_runtime_suspend()
739 if (!tdma->global_cmd) in tegra_adma_runtime_suspend()
742 for (i = 0; i < tdma->nr_channels; i++) { in tegra_adma_runtime_suspend()
743 tdc = &tdma->channels[i]; in tegra_adma_runtime_suspend()
744 ch_reg = &tdc->ch_regs; in tegra_adma_runtime_suspend()
745 ch_reg->cmd = tdma_ch_read(tdc, ADMA_CH_CMD); in tegra_adma_runtime_suspend()
747 if (!ch_reg->cmd) in tegra_adma_runtime_suspend()
749 ch_reg->tc = tdma_ch_read(tdc, ADMA_CH_TC); in tegra_adma_runtime_suspend()
750 ch_reg->src_addr = tdma_ch_read(tdc, ADMA_CH_LOWER_SRC_ADDR); in tegra_adma_runtime_suspend()
751 ch_reg->trg_addr = tdma_ch_read(tdc, ADMA_CH_LOWER_TRG_ADDR); in tegra_adma_runtime_suspend()
752 ch_reg->ctrl = tdma_ch_read(tdc, ADMA_CH_CTRL); in tegra_adma_runtime_suspend()
753 ch_reg->fifo_ctrl = tdma_ch_read(tdc, ADMA_CH_FIFO_CTRL); in tegra_adma_runtime_suspend()
754 ch_reg->config = tdma_ch_read(tdc, ADMA_CH_CONFIG); in tegra_adma_runtime_suspend()
758 clk_disable_unprepare(tdma->ahub_clk); in tegra_adma_runtime_suspend()
770 ret = clk_prepare_enable(tdma->ahub_clk); in tegra_adma_runtime_resume()
775 tdma_write(tdma, ADMA_GLOBAL_CMD, tdma->global_cmd); in tegra_adma_runtime_resume()
777 if (!tdma->global_cmd) in tegra_adma_runtime_resume()
780 for (i = 0; i < tdma->nr_channels; i++) { in tegra_adma_runtime_resume()
781 tdc = &tdma->channels[i]; in tegra_adma_runtime_resume()
782 ch_reg = &tdc->ch_regs; in tegra_adma_runtime_resume()
784 if (!ch_reg->cmd) in tegra_adma_runtime_resume()
786 tdma_ch_write(tdc, ADMA_CH_TC, ch_reg->tc); in tegra_adma_runtime_resume()
787 tdma_ch_write(tdc, ADMA_CH_LOWER_SRC_ADDR, ch_reg->src_addr); in tegra_adma_runtime_resume()
788 tdma_ch_write(tdc, ADMA_CH_LOWER_TRG_ADDR, ch_reg->trg_addr); in tegra_adma_runtime_resume()
789 tdma_ch_write(tdc, ADMA_CH_CTRL, ch_reg->ctrl); in tegra_adma_runtime_resume()
790 tdma_ch_write(tdc, ADMA_CH_FIFO_CTRL, ch_reg->fifo_ctrl); in tegra_adma_runtime_resume()
791 tdma_ch_write(tdc, ADMA_CH_CONFIG, ch_reg->config); in tegra_adma_runtime_resume()
792 tdma_ch_write(tdc, ADMA_CH_CMD, ch_reg->cmd); in tegra_adma_runtime_resume()
831 { .compatible = "nvidia,tegra210-adma", .data = &tegra210_chip_data },
832 { .compatible = "nvidia,tegra186-adma", .data = &tegra186_chip_data },
843 cdata = of_device_get_match_data(&pdev->dev); in tegra_adma_probe()
845 dev_err(&pdev->dev, "device match data not found\n"); in tegra_adma_probe()
846 return -ENODEV; in tegra_adma_probe()
849 tdma = devm_kzalloc(&pdev->dev, in tegra_adma_probe()
850 struct_size(tdma, channels, cdata->nr_channels), in tegra_adma_probe()
853 return -ENOMEM; in tegra_adma_probe()
855 tdma->dev = &pdev->dev; in tegra_adma_probe()
856 tdma->cdata = cdata; in tegra_adma_probe()
857 tdma->nr_channels = cdata->nr_channels; in tegra_adma_probe()
860 tdma->base_addr = devm_platform_ioremap_resource(pdev, 0); in tegra_adma_probe()
861 if (IS_ERR(tdma->base_addr)) in tegra_adma_probe()
862 return PTR_ERR(tdma->base_addr); in tegra_adma_probe()
864 tdma->ahub_clk = devm_clk_get(&pdev->dev, "d_audio"); in tegra_adma_probe()
865 if (IS_ERR(tdma->ahub_clk)) { in tegra_adma_probe()
866 dev_err(&pdev->dev, "Error: Missing ahub controller clock\n"); in tegra_adma_probe()
867 return PTR_ERR(tdma->ahub_clk); in tegra_adma_probe()
870 INIT_LIST_HEAD(&tdma->dma_dev.channels); in tegra_adma_probe()
871 for (i = 0; i < tdma->nr_channels; i++) { in tegra_adma_probe()
872 struct tegra_adma_chan *tdc = &tdma->channels[i]; in tegra_adma_probe()
874 tdc->chan_addr = tdma->base_addr + cdata->ch_base_offset in tegra_adma_probe()
875 + (cdata->ch_reg_size * i); in tegra_adma_probe()
877 tdc->irq = of_irq_get(pdev->dev.of_node, i); in tegra_adma_probe()
878 if (tdc->irq <= 0) { in tegra_adma_probe()
879 ret = tdc->irq ?: -ENXIO; in tegra_adma_probe()
883 vchan_init(&tdc->vc, &tdma->dma_dev); in tegra_adma_probe()
884 tdc->vc.desc_free = tegra_adma_desc_free; in tegra_adma_probe()
885 tdc->tdma = tdma; in tegra_adma_probe()
888 pm_runtime_enable(&pdev->dev); in tegra_adma_probe()
890 ret = pm_runtime_resume_and_get(&pdev->dev); in tegra_adma_probe()
898 dma_cap_set(DMA_SLAVE, tdma->dma_dev.cap_mask); in tegra_adma_probe()
899 dma_cap_set(DMA_PRIVATE, tdma->dma_dev.cap_mask); in tegra_adma_probe()
900 dma_cap_set(DMA_CYCLIC, tdma->dma_dev.cap_mask); in tegra_adma_probe()
902 tdma->dma_dev.dev = &pdev->dev; in tegra_adma_probe()
903 tdma->dma_dev.device_alloc_chan_resources = in tegra_adma_probe()
905 tdma->dma_dev.device_free_chan_resources = in tegra_adma_probe()
907 tdma->dma_dev.device_issue_pending = tegra_adma_issue_pending; in tegra_adma_probe()
908 tdma->dma_dev.device_prep_dma_cyclic = tegra_adma_prep_dma_cyclic; in tegra_adma_probe()
909 tdma->dma_dev.device_config = tegra_adma_slave_config; in tegra_adma_probe()
910 tdma->dma_dev.device_tx_status = tegra_adma_tx_status; in tegra_adma_probe()
911 tdma->dma_dev.device_terminate_all = tegra_adma_terminate_all; in tegra_adma_probe()
912 tdma->dma_dev.src_addr_widths = BIT(DMA_SLAVE_BUSWIDTH_4_BYTES); in tegra_adma_probe()
913 tdma->dma_dev.dst_addr_widths = BIT(DMA_SLAVE_BUSWIDTH_4_BYTES); in tegra_adma_probe()
914 tdma->dma_dev.directions = BIT(DMA_DEV_TO_MEM) | BIT(DMA_MEM_TO_DEV); in tegra_adma_probe()
915 tdma->dma_dev.residue_granularity = DMA_RESIDUE_GRANULARITY_SEGMENT; in tegra_adma_probe()
916 tdma->dma_dev.device_pause = tegra_adma_pause; in tegra_adma_probe()
917 tdma->dma_dev.device_resume = tegra_adma_resume; in tegra_adma_probe()
919 ret = dma_async_device_register(&tdma->dma_dev); in tegra_adma_probe()
921 dev_err(&pdev->dev, "ADMA registration failed: %d\n", ret); in tegra_adma_probe()
925 ret = of_dma_controller_register(pdev->dev.of_node, in tegra_adma_probe()
928 dev_err(&pdev->dev, "ADMA OF registration failed %d\n", ret); in tegra_adma_probe()
932 pm_runtime_put(&pdev->dev); in tegra_adma_probe()
934 dev_info(&pdev->dev, "Tegra210 ADMA driver registered %d channels\n", in tegra_adma_probe()
935 tdma->nr_channels); in tegra_adma_probe()
940 dma_async_device_unregister(&tdma->dma_dev); in tegra_adma_probe()
942 pm_runtime_put_sync(&pdev->dev); in tegra_adma_probe()
944 pm_runtime_disable(&pdev->dev); in tegra_adma_probe()
946 while (--i >= 0) in tegra_adma_probe()
947 irq_dispose_mapping(tdma->channels[i].irq); in tegra_adma_probe()
957 of_dma_controller_free(pdev->dev.of_node); in tegra_adma_remove()
958 dma_async_device_unregister(&tdma->dma_dev); in tegra_adma_remove()
960 for (i = 0; i < tdma->nr_channels; ++i) in tegra_adma_remove()
961 irq_dispose_mapping(tdma->channels[i].irq); in tegra_adma_remove()
963 pm_runtime_disable(&pdev->dev); in tegra_adma_remove()
977 .name = "tegra-adma",
987 MODULE_ALIAS("platform:tegra210-adma");