Lines Matching +full:tsens +full:- +full:v1
1 // SPDX-License-Identifier: BSD-3-Clause
6 #include <dt-bindings/interrupt-controller/arm-gic.h>
7 #include <dt-bindings/clock/qcom,gcc-sm8450.h>
8 #include <dt-bindings/clock/qcom,rpmh.h>
9 #include <dt-bindings/clock/qcom,sm8450-camcc.h>
10 #include <dt-bindings/clock/qcom,sm8450-dispcc.h>
11 #include <dt-bindings/clock/qcom,sm8450-videocc.h>
12 #include <dt-bindings/dma/qcom-gpi.h>
13 #include <dt-bindings/gpio/gpio.h>
14 #include <dt-bindings/mailbox/qcom-ipcc.h>
15 #include <dt-bindings/phy/phy-qcom-qmp.h>
16 #include <dt-bindings/power/qcom,rpmhpd.h>
17 #include <dt-bindings/power/qcom-rpmpd.h>
18 #include <dt-bindings/interconnect/qcom,icc.h>
19 #include <dt-bindings/interconnect/qcom,sm8450.h>
20 #include <dt-bindings/soc/qcom,gpr.h>
21 #include <dt-bindings/soc/qcom,rpmh-rsc.h>
22 #include <dt-bindings/sound/qcom,q6dsp-lpass-ports.h>
23 #include <dt-bindings/thermal/thermal.h>
26 interrupt-parent = <&intc>;
28 #address-cells = <2>;
29 #size-cells = <2>;
34 xo_board: xo-board {
35 compatible = "fixed-clock";
36 #clock-cells = <0>;
37 clock-frequency = <76800000>;
40 sleep_clk: sleep-clk {
41 compatible = "fixed-clock";
42 #clock-cells = <0>;
43 clock-frequency = <32000>;
48 #address-cells = <2>;
49 #size-cells = <0>;
55 enable-method = "psci";
56 next-level-cache = <&L2_0>;
57 power-domains = <&CPU_PD0>;
58 power-domain-names = "psci";
59 qcom,freq-domain = <&cpufreq_hw 0>;
60 #cooling-cells = <2>;
62 L2_0: l2-cache {
64 cache-level = <2>;
65 cache-unified;
66 next-level-cache = <&L3_0>;
67 L3_0: l3-cache {
69 cache-level = <3>;
70 cache-unified;
79 enable-method = "psci";
80 next-level-cache = <&L2_100>;
81 power-domains = <&CPU_PD1>;
82 power-domain-names = "psci";
83 qcom,freq-domain = <&cpufreq_hw 0>;
84 #cooling-cells = <2>;
86 L2_100: l2-cache {
88 cache-level = <2>;
89 cache-unified;
90 next-level-cache = <&L3_0>;
98 enable-method = "psci";
99 next-level-cache = <&L2_200>;
100 power-domains = <&CPU_PD2>;
101 power-domain-names = "psci";
102 qcom,freq-domain = <&cpufreq_hw 0>;
103 #cooling-cells = <2>;
105 L2_200: l2-cache {
107 cache-level = <2>;
108 cache-unified;
109 next-level-cache = <&L3_0>;
117 enable-method = "psci";
118 next-level-cache = <&L2_300>;
119 power-domains = <&CPU_PD3>;
120 power-domain-names = "psci";
121 qcom,freq-domain = <&cpufreq_hw 0>;
122 #cooling-cells = <2>;
124 L2_300: l2-cache {
126 cache-level = <2>;
127 cache-unified;
128 next-level-cache = <&L3_0>;
136 enable-method = "psci";
137 next-level-cache = <&L2_400>;
138 power-domains = <&CPU_PD4>;
139 power-domain-names = "psci";
140 qcom,freq-domain = <&cpufreq_hw 1>;
141 #cooling-cells = <2>;
143 L2_400: l2-cache {
145 cache-level = <2>;
146 cache-unified;
147 next-level-cache = <&L3_0>;
155 enable-method = "psci";
156 next-level-cache = <&L2_500>;
157 power-domains = <&CPU_PD5>;
158 power-domain-names = "psci";
159 qcom,freq-domain = <&cpufreq_hw 1>;
160 #cooling-cells = <2>;
162 L2_500: l2-cache {
164 cache-level = <2>;
165 cache-unified;
166 next-level-cache = <&L3_0>;
174 enable-method = "psci";
175 next-level-cache = <&L2_600>;
176 power-domains = <&CPU_PD6>;
177 power-domain-names = "psci";
178 qcom,freq-domain = <&cpufreq_hw 1>;
179 #cooling-cells = <2>;
181 L2_600: l2-cache {
183 cache-level = <2>;
184 cache-unified;
185 next-level-cache = <&L3_0>;
193 enable-method = "psci";
194 next-level-cache = <&L2_700>;
195 power-domains = <&CPU_PD7>;
196 power-domain-names = "psci";
197 qcom,freq-domain = <&cpufreq_hw 2>;
198 #cooling-cells = <2>;
200 L2_700: l2-cache {
202 cache-level = <2>;
203 cache-unified;
204 next-level-cache = <&L3_0>;
208 cpu-map {
244 idle-states {
245 entry-method = "psci";
247 LITTLE_CPU_SLEEP_0: cpu-sleep-0-0 {
248 compatible = "arm,idle-state";
249 idle-state-name = "silver-rail-power-collapse";
250 arm,psci-suspend-param = <0x40000004>;
251 entry-latency-us = <800>;
252 exit-latency-us = <750>;
253 min-residency-us = <4090>;
254 local-timer-stop;
257 BIG_CPU_SLEEP_0: cpu-sleep-1-0 {
258 compatible = "arm,idle-state";
259 idle-state-name = "gold-rail-power-collapse";
260 arm,psci-suspend-param = <0x40000004>;
261 entry-latency-us = <600>;
262 exit-latency-us = <1550>;
263 min-residency-us = <4791>;
264 local-timer-stop;
268 domain-idle-states {
269 CLUSTER_SLEEP_0: cluster-sleep-0 {
270 compatible = "domain-idle-state";
271 arm,psci-suspend-param = <0x41000044>;
272 entry-latency-us = <1050>;
273 exit-latency-us = <2500>;
274 min-residency-us = <5309>;
277 CLUSTER_SLEEP_1: cluster-sleep-1 {
278 compatible = "domain-idle-state";
279 arm,psci-suspend-param = <0x4100c344>;
280 entry-latency-us = <2700>;
281 exit-latency-us = <3500>;
282 min-residency-us = <13959>;
289 compatible = "qcom,scm-sm8450", "qcom,scm";
290 qcom,dload-mode = <&tcsr 0x13000>;
292 #reset-cells = <1>;
296 clk_virt: interconnect-0 {
297 compatible = "qcom,sm8450-clk-virt";
298 #interconnect-cells = <2>;
299 qcom,bcm-voters = <&apps_bcm_voter>;
302 mc_virt: interconnect-1 {
303 compatible = "qcom,sm8450-mc-virt";
304 #interconnect-cells = <2>;
305 qcom,bcm-voters = <&apps_bcm_voter>;
315 compatible = "arm,armv8-pmuv3";
320 compatible = "arm,psci-1.0";
323 CPU_PD0: power-domain-cpu0 {
324 #power-domain-cells = <0>;
325 power-domains = <&CLUSTER_PD>;
326 domain-idle-states = <&LITTLE_CPU_SLEEP_0>;
329 CPU_PD1: power-domain-cpu1 {
330 #power-domain-cells = <0>;
331 power-domains = <&CLUSTER_PD>;
332 domain-idle-states = <&LITTLE_CPU_SLEEP_0>;
335 CPU_PD2: power-domain-cpu2 {
336 #power-domain-cells = <0>;
337 power-domains = <&CLUSTER_PD>;
338 domain-idle-states = <&LITTLE_CPU_SLEEP_0>;
341 CPU_PD3: power-domain-cpu3 {
342 #power-domain-cells = <0>;
343 power-domains = <&CLUSTER_PD>;
344 domain-idle-states = <&LITTLE_CPU_SLEEP_0>;
347 CPU_PD4: power-domain-cpu4 {
348 #power-domain-cells = <0>;
349 power-domains = <&CLUSTER_PD>;
350 domain-idle-states = <&BIG_CPU_SLEEP_0>;
353 CPU_PD5: power-domain-cpu5 {
354 #power-domain-cells = <0>;
355 power-domains = <&CLUSTER_PD>;
356 domain-idle-states = <&BIG_CPU_SLEEP_0>;
359 CPU_PD6: power-domain-cpu6 {
360 #power-domain-cells = <0>;
361 power-domains = <&CLUSTER_PD>;
362 domain-idle-states = <&BIG_CPU_SLEEP_0>;
365 CPU_PD7: power-domain-cpu7 {
366 #power-domain-cells = <0>;
367 power-domains = <&CLUSTER_PD>;
368 domain-idle-states = <&BIG_CPU_SLEEP_0>;
371 CLUSTER_PD: power-domain-cpu-cluster0 {
372 #power-domain-cells = <0>;
373 domain-idle-states = <&CLUSTER_SLEEP_0>, <&CLUSTER_SLEEP_1>;
377 qup_opp_table_100mhz: opp-table-qup {
378 compatible = "operating-points-v2";
380 opp-50000000 {
381 opp-hz = /bits/ 64 <50000000>;
382 required-opps = <&rpmhpd_opp_min_svs>;
385 opp-75000000 {
386 opp-hz = /bits/ 64 <75000000>;
387 required-opps = <&rpmhpd_opp_low_svs>;
390 opp-100000000 {
391 opp-hz = /bits/ 64 <100000000>;
392 required-opps = <&rpmhpd_opp_svs>;
396 reserved_memory: reserved-memory {
397 #address-cells = <2>;
398 #size-cells = <2>;
403 no-map;
408 no-map;
413 no-map;
418 no-map;
423 no-map;
427 compatible = "qcom,cmd-db";
429 no-map;
434 no-map;
439 no-map;
444 no-map;
449 no-map;
457 no-map;
462 no-map;
467 no-map;
472 no-map;
477 no-map;
482 no-map;
487 no-map;
492 no-map;
497 no-map;
502 no-map;
507 no-map;
513 no-map;
519 no-map;
524 no-map;
529 no-map;
534 no-map;
538 compatible = "qcom,rmtfs-mem";
540 no-map;
542 qcom,client-id = <1>;
548 no-map;
553 no-map;
562 no-map;
567 no-map;
572 no-map;
577 no-map;
582 no-map;
587 no-map;
592 no-map;
597 no-map;
602 no-map;
607 no-map;
612 no-map;
617 no-map;
622 no-map;
627 no-map;
631 smp2p-adsp {
634 interrupts-extended = <&ipcc IPCC_CLIENT_LPASS
640 qcom,local-pid = <0>;
641 qcom,remote-pid = <2>;
643 smp2p_adsp_out: master-kernel {
644 qcom,entry-name = "master-kernel";
645 #qcom,smem-state-cells = <1>;
648 smp2p_adsp_in: slave-kernel {
649 qcom,entry-name = "slave-kernel";
650 interrupt-controller;
651 #interrupt-cells = <2>;
655 smp2p-cdsp {
658 interrupts-extended = <&ipcc IPCC_CLIENT_CDSP
664 qcom,local-pid = <0>;
665 qcom,remote-pid = <5>;
667 smp2p_cdsp_out: master-kernel {
668 qcom,entry-name = "master-kernel";
669 #qcom,smem-state-cells = <1>;
672 smp2p_cdsp_in: slave-kernel {
673 qcom,entry-name = "slave-kernel";
674 interrupt-controller;
675 #interrupt-cells = <2>;
679 smp2p-modem {
682 interrupts-extended = <&ipcc IPCC_CLIENT_MPSS
688 qcom,local-pid = <0>;
689 qcom,remote-pid = <1>;
691 smp2p_modem_out: master-kernel {
692 qcom,entry-name = "master-kernel";
693 #qcom,smem-state-cells = <1>;
696 smp2p_modem_in: slave-kernel {
697 qcom,entry-name = "slave-kernel";
698 interrupt-controller;
699 #interrupt-cells = <2>;
702 ipa_smp2p_out: ipa-ap-to-modem {
703 qcom,entry-name = "ipa";
704 #qcom,smem-state-cells = <1>;
707 ipa_smp2p_in: ipa-modem-to-ap {
708 qcom,entry-name = "ipa";
709 interrupt-controller;
710 #interrupt-cells = <2>;
714 smp2p-slpi {
717 interrupts-extended = <&ipcc IPCC_CLIENT_SLPI
723 qcom,local-pid = <0>;
724 qcom,remote-pid = <3>;
726 smp2p_slpi_out: master-kernel {
727 qcom,entry-name = "master-kernel";
728 #qcom,smem-state-cells = <1>;
731 smp2p_slpi_in: slave-kernel {
732 qcom,entry-name = "slave-kernel";
733 interrupt-controller;
734 #interrupt-cells = <2>;
739 #address-cells = <2>;
740 #size-cells = <2>;
742 dma-ranges = <0 0 0 0 0x10 0>;
743 compatible = "simple-bus";
745 gcc: clock-controller@100000 {
746 compatible = "qcom,gcc-sm8450";
748 #clock-cells = <1>;
749 #reset-cells = <1>;
750 #power-domain-cells = <1>;
760 clock-names = "bi_tcxo",
771 gpi_dma2: dma-controller@800000 {
772 compatible = "qcom,sm8450-gpi-dma", "qcom,sm6350-gpi-dma";
773 #dma-cells = <3>;
787 dma-channels = <12>;
788 dma-channel-mask = <0x7e>;
794 compatible = "qcom,geni-se-qup";
796 clock-names = "m-ahb", "s-ahb";
800 #address-cells = <2>;
801 #size-cells = <2>;
806 compatible = "qcom,geni-i2c";
808 clock-names = "se";
810 pinctrl-names = "default";
811 pinctrl-0 = <&qup_i2c15_data_clk>;
813 #address-cells = <1>;
814 #size-cells = <0>;
818 interconnect-names = "qup-core", "qup-config", "qup-memory";
821 dma-names = "tx", "rx";
826 compatible = "qcom,geni-spi";
828 clock-names = "se";
831 pinctrl-names = "default";
832 pinctrl-0 = <&qup_spi15_data_clk>, <&qup_spi15_cs>;
835 interconnect-names = "qup-core", "qup-config";
838 dma-names = "tx", "rx";
839 #address-cells = <1>;
840 #size-cells = <0>;
845 compatible = "qcom,geni-i2c";
847 clock-names = "se";
849 pinctrl-names = "default";
850 pinctrl-0 = <&qup_i2c16_data_clk>;
852 #address-cells = <1>;
853 #size-cells = <0>;
857 interconnect-names = "qup-core", "qup-config", "qup-memory";
860 dma-names = "tx", "rx";
865 compatible = "qcom,geni-spi";
867 clock-names = "se";
870 pinctrl-names = "default";
871 pinctrl-0 = <&qup_spi16_data_clk>, <&qup_spi16_cs>;
874 interconnect-names = "qup-core", "qup-config";
877 dma-names = "tx", "rx";
878 #address-cells = <1>;
879 #size-cells = <0>;
884 compatible = "qcom,geni-i2c";
886 clock-names = "se";
888 pinctrl-names = "default";
889 pinctrl-0 = <&qup_i2c17_data_clk>;
891 #address-cells = <1>;
892 #size-cells = <0>;
896 interconnect-names = "qup-core", "qup-config", "qup-memory";
899 dma-names = "tx", "rx";
904 compatible = "qcom,geni-spi";
906 clock-names = "se";
909 pinctrl-names = "default";
910 pinctrl-0 = <&qup_spi17_data_clk>, <&qup_spi17_cs>;
913 interconnect-names = "qup-core", "qup-config";
916 dma-names = "tx", "rx";
917 #address-cells = <1>;
918 #size-cells = <0>;
923 compatible = "qcom,geni-i2c";
925 clock-names = "se";
927 pinctrl-names = "default";
928 pinctrl-0 = <&qup_i2c18_data_clk>;
930 #address-cells = <1>;
931 #size-cells = <0>;
935 interconnect-names = "qup-core", "qup-config", "qup-memory";
938 dma-names = "tx", "rx";
943 compatible = "qcom,geni-spi";
945 clock-names = "se";
948 pinctrl-names = "default";
949 pinctrl-0 = <&qup_spi18_data_clk>, <&qup_spi18_cs>;
952 interconnect-names = "qup-core", "qup-config";
955 dma-names = "tx", "rx";
956 #address-cells = <1>;
957 #size-cells = <0>;
962 compatible = "qcom,geni-i2c";
964 clock-names = "se";
966 pinctrl-names = "default";
967 pinctrl-0 = <&qup_i2c19_data_clk>;
969 #address-cells = <1>;
970 #size-cells = <0>;
974 interconnect-names = "qup-core", "qup-config", "qup-memory";
977 dma-names = "tx", "rx";
982 compatible = "qcom,geni-spi";
984 clock-names = "se";
987 pinctrl-names = "default";
988 pinctrl-0 = <&qup_spi19_data_clk>, <&qup_spi19_cs>;
991 interconnect-names = "qup-core", "qup-config";
994 dma-names = "tx", "rx";
995 #address-cells = <1>;
996 #size-cells = <0>;
1001 compatible = "qcom,geni-i2c";
1003 clock-names = "se";
1005 pinctrl-names = "default";
1006 pinctrl-0 = <&qup_i2c20_data_clk>;
1008 #address-cells = <1>;
1009 #size-cells = <0>;
1013 interconnect-names = "qup-core", "qup-config", "qup-memory";
1016 dma-names = "tx", "rx";
1021 compatible = "qcom,geni-uart";
1023 clock-names = "se";
1025 pinctrl-names = "default";
1026 pinctrl-0 = <&qup_uart20_default>;
1032 compatible = "qcom,geni-spi";
1034 clock-names = "se";
1037 pinctrl-names = "default";
1038 pinctrl-0 = <&qup_spi20_data_clk>, <&qup_spi20_cs>;
1041 interconnect-names = "qup-core", "qup-config";
1044 dma-names = "tx", "rx";
1045 #address-cells = <1>;
1046 #size-cells = <0>;
1051 compatible = "qcom,geni-i2c";
1053 clock-names = "se";
1055 pinctrl-names = "default";
1056 pinctrl-0 = <&qup_i2c21_data_clk>;
1058 #address-cells = <1>;
1059 #size-cells = <0>;
1063 interconnect-names = "qup-core", "qup-config", "qup-memory";
1066 dma-names = "tx", "rx";
1071 compatible = "qcom,geni-spi";
1073 clock-names = "se";
1076 pinctrl-names = "default";
1077 pinctrl-0 = <&qup_spi21_data_clk>, <&qup_spi21_cs>;
1080 interconnect-names = "qup-core", "qup-config";
1083 dma-names = "tx", "rx";
1084 #address-cells = <1>;
1085 #size-cells = <0>;
1090 gpi_dma0: dma-controller@900000 {
1091 compatible = "qcom,sm8450-gpi-dma", "qcom,sm6350-gpi-dma";
1092 #dma-cells = <3>;
1106 dma-channels = <12>;
1107 dma-channel-mask = <0x7e>;
1113 compatible = "qcom,geni-se-qup";
1115 clock-names = "m-ahb", "s-ahb";
1120 interconnect-names = "qup-core";
1121 #address-cells = <2>;
1122 #size-cells = <2>;
1127 compatible = "qcom,geni-i2c";
1129 clock-names = "se";
1131 pinctrl-names = "default";
1132 pinctrl-0 = <&qup_i2c0_data_clk>;
1134 #address-cells = <1>;
1135 #size-cells = <0>;
1139 interconnect-names = "qup-core", "qup-config", "qup-memory";
1142 dma-names = "tx", "rx";
1147 compatible = "qcom,geni-spi";
1149 clock-names = "se";
1152 pinctrl-names = "default";
1153 pinctrl-0 = <&qup_spi0_data_clk>, <&qup_spi0_cs>;
1154 power-domains = <&rpmhpd RPMHPD_CX>;
1155 operating-points-v2 = <&qup_opp_table_100mhz>;
1159 interconnect-names = "qup-core", "qup-config", "qup-memory";
1162 dma-names = "tx", "rx";
1163 #address-cells = <1>;
1164 #size-cells = <0>;
1169 compatible = "qcom,geni-i2c";
1171 clock-names = "se";
1173 pinctrl-names = "default";
1174 pinctrl-0 = <&qup_i2c1_data_clk>;
1176 #address-cells = <1>;
1177 #size-cells = <0>;
1181 interconnect-names = "qup-core", "qup-config", "qup-memory";
1184 dma-names = "tx", "rx";
1189 compatible = "qcom,geni-spi";
1191 clock-names = "se";
1194 pinctrl-names = "default";
1195 pinctrl-0 = <&qup_spi1_data_clk>, <&qup_spi1_cs>;
1199 interconnect-names = "qup-core", "qup-config", "qup-memory";
1202 dma-names = "tx", "rx";
1203 #address-cells = <1>;
1204 #size-cells = <0>;
1209 compatible = "qcom,geni-i2c";
1211 clock-names = "se";
1213 pinctrl-names = "default";
1214 pinctrl-0 = <&qup_i2c2_data_clk>;
1216 #address-cells = <1>;
1217 #size-cells = <0>;
1221 interconnect-names = "qup-core", "qup-config", "qup-memory";
1224 dma-names = "tx", "rx";
1229 compatible = "qcom,geni-spi";
1231 clock-names = "se";
1234 pinctrl-names = "default";
1235 pinctrl-0 = <&qup_spi2_data_clk>, <&qup_spi2_cs>;
1239 interconnect-names = "qup-core", "qup-config", "qup-memory";
1242 dma-names = "tx", "rx";
1243 #address-cells = <1>;
1244 #size-cells = <0>;
1250 compatible = "qcom,geni-i2c";
1252 clock-names = "se";
1254 pinctrl-names = "default";
1255 pinctrl-0 = <&qup_i2c3_data_clk>;
1257 #address-cells = <1>;
1258 #size-cells = <0>;
1262 interconnect-names = "qup-core", "qup-config", "qup-memory";
1265 dma-names = "tx", "rx";
1270 compatible = "qcom,geni-spi";
1272 clock-names = "se";
1275 pinctrl-names = "default";
1276 pinctrl-0 = <&qup_spi3_data_clk>, <&qup_spi3_cs>;
1280 interconnect-names = "qup-core", "qup-config", "qup-memory";
1283 dma-names = "tx", "rx";
1284 #address-cells = <1>;
1285 #size-cells = <0>;
1290 compatible = "qcom,geni-i2c";
1292 clock-names = "se";
1294 pinctrl-names = "default";
1295 pinctrl-0 = <&qup_i2c4_data_clk>;
1297 #address-cells = <1>;
1298 #size-cells = <0>;
1302 interconnect-names = "qup-core", "qup-config", "qup-memory";
1305 dma-names = "tx", "rx";
1310 compatible = "qcom,geni-spi";
1312 clock-names = "se";
1315 pinctrl-names = "default";
1316 pinctrl-0 = <&qup_spi4_data_clk>, <&qup_spi4_cs>;
1317 power-domains = <&rpmhpd RPMHPD_CX>;
1318 operating-points-v2 = <&qup_opp_table_100mhz>;
1322 interconnect-names = "qup-core", "qup-config", "qup-memory";
1325 dma-names = "tx", "rx";
1326 #address-cells = <1>;
1327 #size-cells = <0>;
1332 compatible = "qcom,geni-i2c";
1334 clock-names = "se";
1336 pinctrl-names = "default";
1337 pinctrl-0 = <&qup_i2c5_data_clk>;
1339 #address-cells = <1>;
1340 #size-cells = <0>;
1344 interconnect-names = "qup-core", "qup-config", "qup-memory";
1347 dma-names = "tx", "rx";
1352 compatible = "qcom,geni-spi";
1354 clock-names = "se";
1357 pinctrl-names = "default";
1358 pinctrl-0 = <&qup_spi5_data_clk>, <&qup_spi5_cs>;
1362 interconnect-names = "qup-core", "qup-config", "qup-memory";
1365 dma-names = "tx", "rx";
1366 #address-cells = <1>;
1367 #size-cells = <0>;
1373 compatible = "qcom,geni-i2c";
1375 clock-names = "se";
1377 pinctrl-names = "default";
1378 pinctrl-0 = <&qup_i2c6_data_clk>;
1380 #address-cells = <1>;
1381 #size-cells = <0>;
1385 interconnect-names = "qup-core", "qup-config", "qup-memory";
1388 dma-names = "tx", "rx";
1393 compatible = "qcom,geni-spi";
1395 clock-names = "se";
1398 pinctrl-names = "default";
1399 pinctrl-0 = <&qup_spi6_data_clk>, <&qup_spi6_cs>;
1403 interconnect-names = "qup-core", "qup-config", "qup-memory";
1406 dma-names = "tx", "rx";
1407 #address-cells = <1>;
1408 #size-cells = <0>;
1413 compatible = "qcom,geni-debug-uart";
1415 clock-names = "se";
1417 pinctrl-names = "default";
1418 pinctrl-0 = <&qup_uart7_tx>, <&qup_uart7_rx>;
1424 gpi_dma1: dma-controller@a00000 {
1425 compatible = "qcom,sm8450-gpi-dma", "qcom,sm6350-gpi-dma";
1426 #dma-cells = <3>;
1440 dma-channels = <12>;
1441 dma-channel-mask = <0x7e>;
1447 compatible = "qcom,geni-se-qup";
1449 clock-names = "m-ahb", "s-ahb";
1454 interconnect-names = "qup-core";
1455 #address-cells = <2>;
1456 #size-cells = <2>;
1461 compatible = "qcom,geni-i2c";
1463 clock-names = "se";
1465 pinctrl-names = "default";
1466 pinctrl-0 = <&qup_i2c8_data_clk>;
1468 #address-cells = <1>;
1469 #size-cells = <0>;
1473 interconnect-names = "qup-core", "qup-config", "qup-memory";
1476 dma-names = "tx", "rx";
1481 compatible = "qcom,geni-spi";
1483 clock-names = "se";
1486 pinctrl-names = "default";
1487 pinctrl-0 = <&qup_spi8_data_clk>, <&qup_spi8_cs>;
1491 interconnect-names = "qup-core", "qup-config", "qup-memory";
1494 dma-names = "tx", "rx";
1495 #address-cells = <1>;
1496 #size-cells = <0>;
1501 compatible = "qcom,geni-i2c";
1503 clock-names = "se";
1505 pinctrl-names = "default";
1506 pinctrl-0 = <&qup_i2c9_data_clk>;
1508 #address-cells = <1>;
1509 #size-cells = <0>;
1513 interconnect-names = "qup-core", "qup-config", "qup-memory";
1516 dma-names = "tx", "rx";
1521 compatible = "qcom,geni-spi";
1523 clock-names = "se";
1526 pinctrl-names = "default";
1527 pinctrl-0 = <&qup_spi9_data_clk>, <&qup_spi9_cs>;
1531 interconnect-names = "qup-core", "qup-config", "qup-memory";
1534 dma-names = "tx", "rx";
1535 #address-cells = <1>;
1536 #size-cells = <0>;
1541 compatible = "qcom,geni-i2c";
1543 clock-names = "se";
1545 pinctrl-names = "default";
1546 pinctrl-0 = <&qup_i2c10_data_clk>;
1548 #address-cells = <1>;
1549 #size-cells = <0>;
1553 interconnect-names = "qup-core", "qup-config", "qup-memory";
1556 dma-names = "tx", "rx";
1561 compatible = "qcom,geni-spi";
1563 clock-names = "se";
1566 pinctrl-names = "default";
1567 pinctrl-0 = <&qup_spi10_data_clk>, <&qup_spi10_cs>;
1571 interconnect-names = "qup-core", "qup-config", "qup-memory";
1574 dma-names = "tx", "rx";
1575 #address-cells = <1>;
1576 #size-cells = <0>;
1581 compatible = "qcom,geni-i2c";
1583 clock-names = "se";
1585 pinctrl-names = "default";
1586 pinctrl-0 = <&qup_i2c11_data_clk>;
1588 #address-cells = <1>;
1589 #size-cells = <0>;
1593 interconnect-names = "qup-core", "qup-config", "qup-memory";
1596 dma-names = "tx", "rx";
1601 compatible = "qcom,geni-spi";
1603 clock-names = "se";
1606 pinctrl-names = "default";
1607 pinctrl-0 = <&qup_spi11_data_clk>, <&qup_spi11_cs>;
1611 interconnect-names = "qup-core", "qup-config", "qup-memory";
1614 dma-names = "tx", "rx";
1615 #address-cells = <1>;
1616 #size-cells = <0>;
1621 compatible = "qcom,geni-i2c";
1623 clock-names = "se";
1625 pinctrl-names = "default";
1626 pinctrl-0 = <&qup_i2c12_data_clk>;
1628 #address-cells = <1>;
1629 #size-cells = <0>;
1633 interconnect-names = "qup-core", "qup-config", "qup-memory";
1636 dma-names = "tx", "rx";
1641 compatible = "qcom,geni-spi";
1643 clock-names = "se";
1646 pinctrl-names = "default";
1647 pinctrl-0 = <&qup_spi12_data_clk>, <&qup_spi12_cs>;
1651 interconnect-names = "qup-core", "qup-config", "qup-memory";
1654 dma-names = "tx", "rx";
1655 #address-cells = <1>;
1656 #size-cells = <0>;
1661 compatible = "qcom,geni-i2c";
1663 clock-names = "se";
1665 pinctrl-names = "default";
1666 pinctrl-0 = <&qup_i2c13_data_clk>;
1671 interconnect-names = "qup-core", "qup-config", "qup-memory";
1674 dma-names = "tx", "rx";
1675 #address-cells = <1>;
1676 #size-cells = <0>;
1681 compatible = "qcom,geni-spi";
1683 clock-names = "se";
1686 pinctrl-names = "default";
1687 pinctrl-0 = <&qup_spi13_data_clk>, <&qup_spi13_cs>;
1691 interconnect-names = "qup-core", "qup-config", "qup-memory";
1694 dma-names = "tx", "rx";
1695 #address-cells = <1>;
1696 #size-cells = <0>;
1701 compatible = "qcom,geni-i2c";
1703 clock-names = "se";
1705 pinctrl-names = "default";
1706 pinctrl-0 = <&qup_i2c14_data_clk>;
1711 interconnect-names = "qup-core", "qup-config", "qup-memory";
1714 dma-names = "tx", "rx";
1715 #address-cells = <1>;
1716 #size-cells = <0>;
1721 compatible = "qcom,geni-spi";
1723 clock-names = "se";
1726 pinctrl-names = "default";
1727 pinctrl-0 = <&qup_spi14_data_clk>, <&qup_spi14_cs>;
1731 interconnect-names = "qup-core", "qup-config", "qup-memory";
1734 dma-names = "tx", "rx";
1735 #address-cells = <1>;
1736 #size-cells = <0>;
1742 compatible = "qcom,sm8450-prng-ee", "qcom,prng-ee";
1747 compatible = "qcom,pcie-sm8450-pcie0";
1753 reg-names = "parf", "dbi", "elbi", "atu", "config";
1755 linux,pci-domain = <0>;
1756 bus-range = <0x00 0xff>;
1757 num-lanes = <1>;
1759 #address-cells = <3>;
1760 #size-cells = <2>;
1769 msi-map = <0x0 &gic_its 0x5981 0x1>,
1771 msi-map-mask = <0xff00>;
1773 interrupt-names = "msi";
1774 #interrupt-cells = <1>;
1775 interrupt-map-mask = <0 0 0 0x7>;
1776 interrupt-map = <0 0 0 1 &intc 0 0 0 149 IRQ_TYPE_LEVEL_HIGH>, /* int_a */
1793 clock-names = "pipe",
1806 iommu-map = <0x0 &apps_smmu 0x1c00 0x1>,
1810 reset-names = "pci";
1812 power-domains = <&gcc PCIE_0_GDSC>;
1815 phy-names = "pciephy";
1817 perst-gpios = <&tlmm 94 GPIO_ACTIVE_LOW>;
1818 wake-gpios = <&tlmm 96 GPIO_ACTIVE_HIGH>;
1820 pinctrl-names = "default";
1821 pinctrl-0 = <&pcie0_default_state>;
1827 compatible = "qcom,sm8450-qmp-gen3x1-pcie-phy";
1829 #address-cells = <2>;
1830 #size-cells = <2>;
1836 clock-names = "aux", "cfg_ahb", "ref", "refgen";
1839 reset-names = "phy";
1841 assigned-clocks = <&gcc GCC_PCIE_0_PHY_RCHNG_CLK>;
1842 assigned-clock-rates = <100000000>;
1852 clock-names = "pipe0";
1854 #clock-cells = <0>;
1855 #phy-cells = <0>;
1856 clock-output-names = "pcie_0_pipe_clk";
1861 compatible = "qcom,pcie-sm8450-pcie1";
1867 reg-names = "parf", "dbi", "elbi", "atu", "config";
1869 linux,pci-domain = <1>;
1870 bus-range = <0x00 0xff>;
1871 num-lanes = <2>;
1873 #address-cells = <3>;
1874 #size-cells = <2>;
1883 msi-map = <0x0 &gic_its 0x5a01 0x1>,
1885 msi-map-mask = <0xff00>;
1887 interrupt-names = "msi";
1888 #interrupt-cells = <1>;
1889 interrupt-map-mask = <0 0 0 0x7>;
1890 interrupt-map = <0 0 0 1 &intc 0 0 0 434 IRQ_TYPE_LEVEL_HIGH>, /* int_a */
1906 clock-names = "pipe",
1918 iommu-map = <0x0 &apps_smmu 0x1c80 0x1>,
1922 reset-names = "pci";
1924 power-domains = <&gcc PCIE_1_GDSC>;
1927 phy-names = "pciephy";
1929 perst-gpios = <&tlmm 97 GPIO_ACTIVE_LOW>;
1930 wake-gpios = <&tlmm 99 GPIO_ACTIVE_HIGH>;
1932 pinctrl-names = "default";
1933 pinctrl-0 = <&pcie1_default_state>;
1939 compatible = "qcom,sm8450-qmp-gen4x2-pcie-phy";
1941 #address-cells = <2>;
1942 #size-cells = <2>;
1948 clock-names = "aux", "cfg_ahb", "ref", "refgen";
1951 reset-names = "phy";
1953 assigned-clocks = <&gcc GCC_PCIE_1_PHY_RCHNG_CLK>;
1954 assigned-clock-rates = <100000000>;
1966 clock-names = "pipe0";
1968 #clock-cells = <0>;
1969 #phy-cells = <0>;
1970 clock-output-names = "pcie_1_pipe_clk";
1975 compatible = "qcom,sm8450-config-noc";
1977 #interconnect-cells = <2>;
1978 qcom,bcm-voters = <&apps_bcm_voter>;
1982 compatible = "qcom,sm8450-system-noc";
1984 #interconnect-cells = <2>;
1985 qcom,bcm-voters = <&apps_bcm_voter>;
1989 compatible = "qcom,sm8450-pcie-anoc";
1991 #interconnect-cells = <2>;
1992 qcom,bcm-voters = <&apps_bcm_voter>;
1996 compatible = "qcom,sm8450-aggre1-noc";
1998 #interconnect-cells = <2>;
2001 qcom,bcm-voters = <&apps_bcm_voter>;
2005 compatible = "qcom,sm8450-aggre2-noc";
2007 #interconnect-cells = <2>;
2008 qcom,bcm-voters = <&apps_bcm_voter>;
2016 compatible = "qcom,sm8450-mmss-noc";
2018 #interconnect-cells = <2>;
2019 qcom,bcm-voters = <&apps_bcm_voter>;
2023 compatible = "qcom,tcsr-mutex";
2025 #hwlock-cells = <1>;
2029 compatible = "qcom,sm8450-tcsr", "syscon";
2034 compatible = "qcom,sm8450-usb-hs-phy",
2035 "qcom,usb-snps-hs-7nm-phy";
2038 #phy-cells = <0>;
2041 clock-names = "ref";
2047 compatible = "qcom,sm8450-qmp-usb3-dp-phy";
2054 clock-names = "aux", "ref", "com_aux", "usb3_pipe";
2058 reset-names = "phy", "common";
2060 #clock-cells = <1>;
2061 #phy-cells = <1>;
2066 #address-cells = <1>;
2067 #size-cells = <0>;
2093 compatible = "qcom,sm8450-slpi-pas";
2096 interrupts-extended = <&pdc 9 IRQ_TYPE_EDGE_RISING>,
2101 interrupt-names = "wdog", "fatal", "ready",
2102 "handover", "stop-ack";
2105 clock-names = "xo";
2107 power-domains = <&rpmhpd RPMHPD_LCX>,
2109 power-domain-names = "lcx", "lmx";
2111 memory-region = <&slpi_mem>;
2115 qcom,smem-states = <&smp2p_slpi_out 0>;
2116 qcom,smem-state-names = "stop";
2120 glink-edge {
2121 interrupts-extended = <&ipcc IPCC_CLIENT_SLPI
2128 qcom,remote-pid = <3>;
2132 qcom,glink-channels = "fastrpcglink-apps-dsp";
2134 #address-cells = <1>;
2135 #size-cells = <0>;
2137 compute-cb@1 {
2138 compatible = "qcom,fastrpc-compute-cb";
2143 compute-cb@2 {
2144 compatible = "qcom,fastrpc-compute-cb";
2149 compute-cb@3 {
2150 compatible = "qcom,fastrpc-compute-cb";
2153 /* note: shared-cb = <4> in downstream */
2160 compatible = "qcom,sm8450-lpass-wsa-macro";
2167 clock-names = "mclk", "npl", "macro", "dcodec", "fsgen";
2168 assigned-clocks = <&q6prmcc LPASS_CLK_ID_WSA2_CORE_TX_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
2170 assigned-clock-rates = <19200000>, <19200000>;
2172 #clock-cells = <0>;
2173 clock-output-names = "wsa2-mclk";
2174 pinctrl-names = "default";
2175 pinctrl-0 = <&wsa2_swr_active>;
2176 #sound-dai-cells = <1>;
2179 swr4: soundwire-controller@31f0000 {
2180 compatible = "qcom,soundwire-v1.7.0";
2184 clock-names = "iface";
2187 qcom,din-ports = <2>;
2188 qcom,dout-ports = <6>;
2190 qcom,ports-sinterval-low = /bits/ 8 <0x07 0x1f 0x3f 0x07 0x1f 0x3f 0x0f 0x0f>;
2191 qcom,ports-offset1 = /bits/ 8 <0x01 0x02 0x0c 0x06 0x12 0x0d 0x07 0x0a>;
2192 qcom,ports-offset2 = /bits/ 8 <0xff 0x00 0x1f 0xff 0x00 0x1f 0x00 0x00>;
2193 qcom,ports-hstart = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff>;
2194 qcom,ports-hstop = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff>;
2195 qcom,ports-word-length = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff>;
2196 qcom,ports-block-pack-mode = /bits/ 8 <0xff 0xff 0x01 0xff 0xff 0x01 0xff 0xff>;
2197 qcom,ports-block-group-count = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff>;
2198 qcom,ports-lane-control = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff>;
2200 #address-cells = <2>;
2201 #size-cells = <0>;
2202 #sound-dai-cells = <1>;
2207 compatible = "qcom,sm8450-lpass-rx-macro";
2214 clock-names = "mclk", "npl", "macro", "dcodec", "fsgen";
2216 assigned-clocks = <&q6prmcc LPASS_CLK_ID_RX_CORE_TX_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
2218 assigned-clock-rates = <19200000>, <19200000>;
2220 #clock-cells = <0>;
2221 clock-output-names = "mclk";
2222 pinctrl-names = "default";
2223 pinctrl-0 = <&rx_swr_active>;
2224 #sound-dai-cells = <1>;
2227 swr1: soundwire-controller@3210000 {
2228 compatible = "qcom,soundwire-v1.7.0";
2232 clock-names = "iface";
2234 qcom,din-ports = <0>;
2235 qcom,dout-ports = <5>;
2237 qcom,ports-sinterval-low = /bits/ 8 <0x03 0x1f 0x1f 0x07 0x00>;
2238 qcom,ports-offset1 = /bits/ 8 <0x00 0x00 0x0b 0x01 0x00>;
2239 qcom,ports-offset2 = /bits/ 8 <0x00 0x00 0x0b 0x00 0x00>;
2240 qcom,ports-hstart = /bits/ 8 <0xff 0x03 0xff 0xff 0xff>;
2241 qcom,ports-hstop = /bits/ 8 <0xff 0x06 0xff 0xff 0xff>;
2242 qcom,ports-word-length = /bits/ 8 <0x01 0x07 0x04 0xff 0xff>;
2243 qcom,ports-block-pack-mode = /bits/ 8 <0xff 0x00 0x01 0xff 0xff>;
2244 qcom,ports-block-group-count = /bits/ 8 <0xff 0xff 0xff 0xff 0x00>;
2245 qcom,ports-lane-control = /bits/ 8 <0x01 0x00 0x00 0x00 0x00>;
2247 #address-cells = <2>;
2248 #size-cells = <0>;
2249 #sound-dai-cells = <1>;
2254 compatible = "qcom,sm8450-lpass-tx-macro";
2261 clock-names = "mclk", "npl", "macro", "dcodec", "fsgen";
2262 assigned-clocks = <&q6prmcc LPASS_CLK_ID_RX_CORE_TX_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
2264 assigned-clock-rates = <19200000>, <19200000>;
2266 #clock-cells = <0>;
2267 clock-output-names = "mclk";
2268 pinctrl-names = "default";
2269 pinctrl-0 = <&tx_swr_active>;
2270 #sound-dai-cells = <1>;
2274 compatible = "qcom,sm8450-lpass-wsa-macro";
2281 clock-names = "mclk", "npl", "macro", "dcodec", "fsgen";
2283 assigned-clocks = <&q6prmcc LPASS_CLK_ID_WSA_CORE_TX_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
2285 assigned-clock-rates = <19200000>, <19200000>;
2287 #clock-cells = <0>;
2288 clock-output-names = "mclk";
2289 pinctrl-names = "default";
2290 pinctrl-0 = <&wsa_swr_active>;
2291 #sound-dai-cells = <1>;
2294 swr0: soundwire-controller@3250000 {
2295 compatible = "qcom,soundwire-v1.7.0";
2299 clock-names = "iface";
2302 qcom,din-ports = <2>;
2303 qcom,dout-ports = <6>;
2305 qcom,ports-sinterval-low = /bits/ 8 <0x07 0x1f 0x3f 0x07 0x1f 0x3f 0x0f 0x0f>;
2306 qcom,ports-offset1 = /bits/ 8 <0x01 0x02 0x0c 0x06 0x12 0x0d 0x07 0x0a>;
2307 qcom,ports-offset2 = /bits/ 8 <0xff 0x00 0x1f 0xff 0x00 0x1f 0x00 0x00>;
2308 qcom,ports-hstart = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff>;
2309 qcom,ports-hstop = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff>;
2310 qcom,ports-word-length = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff>;
2311 qcom,ports-block-pack-mode = /bits/ 8 <0xff 0xff 0x01 0xff 0xff 0x01 0xff 0xff>;
2312 qcom,ports-block-group-count = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff>;
2313 qcom,ports-lane-control = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff>;
2315 #address-cells = <2>;
2316 #size-cells = <0>;
2317 #sound-dai-cells = <1>;
2321 swr2: soundwire-controller@33b0000 {
2322 compatible = "qcom,soundwire-v1.7.0";
2326 interrupt-names = "core", "wakeup";
2329 clock-names = "iface";
2332 qcom,din-ports = <4>;
2333 qcom,dout-ports = <0>;
2334 qcom,ports-sinterval-low = /bits/ 8 <0x01 0x01 0x03 0x03>;
2335 qcom,ports-offset1 = /bits/ 8 <0x00 0x00 0x01 0x01>;
2336 qcom,ports-offset2 = /bits/ 8 <0x00 0x00 0x00 0x00>;
2337 qcom,ports-hstart = /bits/ 8 <0xff 0xff 0xff 0xff>;
2338 qcom,ports-hstop = /bits/ 8 <0xff 0xff 0xff 0xff>;
2339 qcom,ports-word-length = /bits/ 8 <0xff 0xff 0xff 0xff>;
2340 qcom,ports-block-pack-mode = /bits/ 8 <0xff 0xff 0xff 0xff>;
2341 qcom,ports-block-group-count = /bits/ 8 <0xff 0xff 0xff 0xff>;
2342 qcom,ports-lane-control = /bits/ 8 <0x01 0x02 0x00 0x00>;
2344 #address-cells = <2>;
2345 #size-cells = <0>;
2346 #sound-dai-cells = <1>;
2351 compatible = "qcom,sm8450-lpass-va-macro";
2357 clock-names = "mclk", "macro", "dcodec", "npl";
2358 assigned-clocks = <&q6prmcc LPASS_CLK_ID_TX_CORE_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>;
2359 assigned-clock-rates = <19200000>;
2361 #clock-cells = <0>;
2362 clock-output-names = "fsgen";
2363 #sound-dai-cells = <1>;
2368 compatible = "qcom,sm8450-adsp-pas";
2371 interrupts-extended = <&pdc 6 IRQ_TYPE_EDGE_RISING>,
2376 interrupt-names = "wdog", "fatal", "ready",
2377 "handover", "stop-ack";
2380 clock-names = "xo";
2382 power-domains = <&rpmhpd RPMHPD_LCX>,
2384 power-domain-names = "lcx", "lmx";
2386 memory-region = <&adsp_mem>;
2390 qcom,smem-states = <&smp2p_adsp_out 0>;
2391 qcom,smem-state-names = "stop";
2395 remoteproc_adsp_glink: glink-edge {
2396 interrupts-extended = <&ipcc IPCC_CLIENT_LPASS
2403 qcom,remote-pid = <2>;
2407 qcom,glink-channels = "adsp_apps";
2410 #address-cells = <1>;
2411 #size-cells = <0>;
2416 #sound-dai-cells = <0>;
2417 qcom,protection-domain = "avs/audio",
2421 compatible = "qcom,q6apm-dais";
2426 compatible = "qcom,q6apm-lpass-dais";
2427 #sound-dai-cells = <1>;
2434 qcom,protection-domain = "avs/audio",
2437 q6prmcc: clock-controller {
2438 compatible = "qcom,q6prm-lpass-clocks";
2439 #clock-cells = <2>;
2446 qcom,glink-channels = "fastrpcglink-apps-dsp";
2448 #address-cells = <1>;
2449 #size-cells = <0>;
2451 compute-cb@3 {
2452 compatible = "qcom,fastrpc-compute-cb";
2457 compute-cb@4 {
2458 compatible = "qcom,fastrpc-compute-cb";
2463 compute-cb@5 {
2464 compatible = "qcom,fastrpc-compute-cb";
2473 compatible = "qcom,sm8450-cdsp-pas";
2476 interrupts-extended = <&intc GIC_SPI 578 IRQ_TYPE_EDGE_RISING>,
2481 interrupt-names = "wdog", "fatal", "ready",
2482 "handover", "stop-ack";
2485 clock-names = "xo";
2487 power-domains = <&rpmhpd RPMHPD_CX>,
2489 power-domain-names = "cx", "mxc";
2491 memory-region = <&cdsp_mem>;
2495 qcom,smem-states = <&smp2p_cdsp_out 0>;
2496 qcom,smem-state-names = "stop";
2500 glink-edge {
2501 interrupts-extended = <&ipcc IPCC_CLIENT_CDSP
2508 qcom,remote-pid = <5>;
2512 qcom,glink-channels = "fastrpcglink-apps-dsp";
2514 #address-cells = <1>;
2515 #size-cells = <0>;
2517 compute-cb@1 {
2518 compatible = "qcom,fastrpc-compute-cb";
2524 compute-cb@2 {
2525 compatible = "qcom,fastrpc-compute-cb";
2531 compute-cb@3 {
2532 compatible = "qcom,fastrpc-compute-cb";
2538 compute-cb@4 {
2539 compatible = "qcom,fastrpc-compute-cb";
2545 compute-cb@5 {
2546 compatible = "qcom,fastrpc-compute-cb";
2552 compute-cb@6 {
2553 compatible = "qcom,fastrpc-compute-cb";
2559 compute-cb@7 {
2560 compatible = "qcom,fastrpc-compute-cb";
2566 compute-cb@8 {
2567 compatible = "qcom,fastrpc-compute-cb";
2579 compatible = "qcom,sm8450-mpss-pas";
2582 interrupts-extended = <&intc GIC_SPI 264 IRQ_TYPE_EDGE_RISING>,
2588 interrupt-names = "wdog", "fatal", "ready", "handover",
2589 "stop-ack", "shutdown-ack";
2592 clock-names = "xo";
2594 power-domains = <&rpmhpd RPMHPD_CX>,
2596 power-domain-names = "cx", "mss";
2598 memory-region = <&mpss_mem>;
2602 qcom,smem-states = <&smp2p_modem_out 0>;
2603 qcom,smem-state-names = "stop";
2607 glink-edge {
2608 interrupts-extended = <&ipcc IPCC_CLIENT_MPSS
2614 qcom,remote-pid = <1>;
2618 videocc: clock-controller@aaf0000 {
2619 compatible = "qcom,sm8450-videocc";
2623 power-domains = <&rpmhpd RPMHPD_MMCX>;
2624 required-opps = <&rpmhpd_opp_low_svs>;
2625 #clock-cells = <1>;
2626 #reset-cells = <1>;
2627 #power-domain-cells = <1>;
2631 compatible = "qcom,sm8450-cci", "qcom,msm8996-cci";
2634 power-domains = <&camcc TITAN_TOP_GDSC>;
2641 clock-names = "camnoc_axi",
2646 pinctrl-0 = <&cci0_default &cci1_default>;
2647 pinctrl-1 = <&cci0_sleep &cci1_sleep>;
2648 pinctrl-names = "default", "sleep";
2651 #address-cells = <1>;
2652 #size-cells = <0>;
2654 cci0_i2c0: i2c-bus@0 {
2656 clock-frequency = <1000000>;
2657 #address-cells = <1>;
2658 #size-cells = <0>;
2661 cci0_i2c1: i2c-bus@1 {
2663 clock-frequency = <1000000>;
2664 #address-cells = <1>;
2665 #size-cells = <0>;
2670 compatible = "qcom,sm8450-cci", "qcom,msm8996-cci";
2673 power-domains = <&camcc TITAN_TOP_GDSC>;
2680 clock-names = "camnoc_axi",
2685 pinctrl-0 = <&cci2_default &cci3_default>;
2686 pinctrl-1 = <&cci2_sleep &cci3_sleep>;
2687 pinctrl-names = "default", "sleep";
2690 #address-cells = <1>;
2691 #size-cells = <0>;
2693 cci1_i2c0: i2c-bus@0 {
2695 clock-frequency = <1000000>;
2696 #address-cells = <1>;
2697 #size-cells = <0>;
2700 cci1_i2c1: i2c-bus@1 {
2702 clock-frequency = <1000000>;
2703 #address-cells = <1>;
2704 #size-cells = <0>;
2708 camcc: clock-controller@ade0000 {
2709 compatible = "qcom,sm8450-camcc";
2715 power-domains = <&rpmhpd RPMHPD_MMCX>;
2716 required-opps = <&rpmhpd_opp_low_svs>;
2717 #clock-cells = <1>;
2718 #reset-cells = <1>;
2719 #power-domain-cells = <1>;
2723 mdss: display-subsystem@ae00000 {
2724 compatible = "qcom,sm8450-mdss";
2726 reg-names = "mdss";
2733 interconnect-names = "mdp0-mem",
2734 "mdp1-mem",
2735 "cpu-cfg";
2739 power-domains = <&dispcc MDSS_GDSC>;
2747 interrupt-controller;
2748 #interrupt-cells = <1>;
2752 #address-cells = <2>;
2753 #size-cells = <2>;
2758 mdss_mdp: display-controller@ae01000 {
2759 compatible = "qcom,sm8450-dpu";
2762 reg-names = "mdp", "vbif";
2770 clock-names = "bus",
2777 assigned-clocks = <&dispcc DISP_CC_MDSS_VSYNC_CLK>;
2778 assigned-clock-rates = <19200000>;
2780 operating-points-v2 = <&mdp_opp_table>;
2781 power-domains = <&rpmhpd RPMHPD_MMCX>;
2783 interrupt-parent = <&mdss>;
2787 #address-cells = <1>;
2788 #size-cells = <0>;
2793 remote-endpoint = <&mdss_dsi0_in>;
2800 remote-endpoint = <&mdss_dsi1_in>;
2807 remote-endpoint = <&mdss_dp0_in>;
2812 mdp_opp_table: opp-table {
2813 compatible = "operating-points-v2";
2815 opp-172000000 {
2816 opp-hz = /bits/ 64 <172000000>;
2817 required-opps = <&rpmhpd_opp_low_svs_d1>;
2820 opp-200000000 {
2821 opp-hz = /bits/ 64 <200000000>;
2822 required-opps = <&rpmhpd_opp_low_svs>;
2825 opp-325000000 {
2826 opp-hz = /bits/ 64 <325000000>;
2827 required-opps = <&rpmhpd_opp_svs>;
2830 opp-375000000 {
2831 opp-hz = /bits/ 64 <375000000>;
2832 required-opps = <&rpmhpd_opp_svs_l1>;
2835 opp-500000000 {
2836 opp-hz = /bits/ 64 <500000000>;
2837 required-opps = <&rpmhpd_opp_nom>;
2842 mdss_dp0: displayport-controller@ae90000 {
2843 compatible = "qcom,sm8450-dp", "qcom,sm8350-dp";
2849 interrupt-parent = <&mdss>;
2856 clock-names = "core_iface",
2862 assigned-clocks = <&dispcc DISP_CC_MDSS_DPTX0_LINK_CLK_SRC>,
2864 assigned-clock-parents = <&usb_1_qmpphy QMP_USB43DP_DP_LINK_CLK>,
2868 phy-names = "dp";
2870 #sound-dai-cells = <0>;
2872 operating-points-v2 = <&dp_opp_table>;
2873 power-domains = <&rpmhpd RPMHPD_MMCX>;
2878 #address-cells = <1>;
2879 #size-cells = <0>;
2884 remote-endpoint = <&dpu_intf0_out>;
2889 dp_opp_table: opp-table {
2890 compatible = "operating-points-v2";
2892 opp-160000000 {
2893 opp-hz = /bits/ 64 <160000000>;
2894 required-opps = <&rpmhpd_opp_low_svs>;
2897 opp-270000000 {
2898 opp-hz = /bits/ 64 <270000000>;
2899 required-opps = <&rpmhpd_opp_svs>;
2902 opp-540000000 {
2903 opp-hz = /bits/ 64 <540000000>;
2904 required-opps = <&rpmhpd_opp_svs_l1>;
2907 opp-810000000 {
2908 opp-hz = /bits/ 64 <810000000>;
2909 required-opps = <&rpmhpd_opp_nom>;
2915 compatible = "qcom,sm8450-dsi-ctrl", "qcom,mdss-dsi-ctrl";
2917 reg-names = "dsi_ctrl";
2919 interrupt-parent = <&mdss>;
2928 clock-names = "byte",
2935 assigned-clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK_SRC>, <&dispcc DISP_CC_MDSS_PCLK0_CLK_SRC>;
2936 assigned-clock-parents = <&mdss_dsi0_phy 0>, <&mdss_dsi0_phy 1>;
2938 operating-points-v2 = <&mdss_dsi_opp_table>;
2939 power-domains = <&rpmhpd RPMHPD_MMCX>;
2942 phy-names = "dsi";
2944 #address-cells = <1>;
2945 #size-cells = <0>;
2950 #address-cells = <1>;
2951 #size-cells = <0>;
2956 remote-endpoint = <&dpu_intf1_out>;
2967 mdss_dsi_opp_table: opp-table {
2968 compatible = "operating-points-v2";
2970 opp-187500000 {
2971 opp-hz = /bits/ 64 <187500000>;
2972 required-opps = <&rpmhpd_opp_low_svs>;
2975 opp-300000000 {
2976 opp-hz = /bits/ 64 <300000000>;
2977 required-opps = <&rpmhpd_opp_svs>;
2980 opp-358000000 {
2981 opp-hz = /bits/ 64 <358000000>;
2982 required-opps = <&rpmhpd_opp_svs_l1>;
2988 compatible = "qcom,sm8450-dsi-phy-5nm";
2992 reg-names = "dsi_phy",
2996 #clock-cells = <1>;
2997 #phy-cells = <0>;
3001 clock-names = "iface", "ref";
3007 compatible = "qcom,sm8450-dsi-ctrl", "qcom,mdss-dsi-ctrl";
3009 reg-names = "dsi_ctrl";
3011 interrupt-parent = <&mdss>;
3020 clock-names = "byte",
3027 assigned-clocks = <&dispcc DISP_CC_MDSS_BYTE1_CLK_SRC>, <&dispcc DISP_CC_MDSS_PCLK1_CLK_SRC>;
3028 assigned-clock-parents = <&mdss_dsi1_phy 0>, <&mdss_dsi1_phy 1>;
3030 operating-points-v2 = <&mdss_dsi_opp_table>;
3031 power-domains = <&rpmhpd RPMHPD_MMCX>;
3034 phy-names = "dsi";
3036 #address-cells = <1>;
3037 #size-cells = <0>;
3042 #address-cells = <1>;
3043 #size-cells = <0>;
3048 remote-endpoint = <&dpu_intf2_out>;
3061 compatible = "qcom,sm8450-dsi-phy-5nm";
3065 reg-names = "dsi_phy",
3069 #clock-cells = <1>;
3070 #phy-cells = <0>;
3074 clock-names = "iface", "ref";
3080 dispcc: clock-controller@af00000 {
3081 compatible = "qcom,sm8450-dispcc";
3099 power-domains = <&rpmhpd RPMHPD_MMCX>;
3100 required-opps = <&rpmhpd_opp_low_svs>;
3101 #clock-cells = <1>;
3102 #reset-cells = <1>;
3103 #power-domain-cells = <1>;
3107 pdc: interrupt-controller@b220000 {
3108 compatible = "qcom,sm8450-pdc", "qcom,pdc";
3110 qcom,pdc-ranges = <0 480 12>, <14 494 24>, <40 520 54>,
3112 #interrupt-cells = <2>;
3113 interrupt-parent = <&intc>;
3114 interrupt-controller;
3117 tsens0: thermal-sensor@c263000 {
3118 compatible = "qcom,sm8450-tsens", "qcom,tsens-v2";
3124 interrupt-names = "uplow", "critical";
3125 #thermal-sensor-cells = <1>;
3128 tsens1: thermal-sensor@c265000 {
3129 compatible = "qcom,sm8450-tsens", "qcom,tsens-v2";
3135 interrupt-names = "uplow", "critical";
3136 #thermal-sensor-cells = <1>;
3139 aoss_qmp: power-management@c300000 {
3140 compatible = "qcom,sm8450-aoss-qmp", "qcom,aoss-qmp";
3142 interrupts-extended = <&ipcc IPCC_CLIENT_AOP IPCC_MPROC_SIGNAL_GLINK_QMP
3146 #clock-cells = <0>;
3150 compatible = "qcom,rpmh-stats";
3155 compatible = "qcom,spmi-pmic-arb";
3161 reg-names = "core",
3166 interrupt-names = "periph_irq";
3167 interrupts-extended = <&pdc 1 IRQ_TYPE_LEVEL_HIGH>;
3170 interrupt-controller;
3171 #interrupt-cells = <4>;
3172 #address-cells = <2>;
3173 #size-cells = <0>;
3177 compatible = "qcom,sm8450-ipcc", "qcom,ipcc";
3180 interrupt-controller;
3181 #interrupt-cells = <3>;
3182 #mbox-cells = <2>;
3186 compatible = "qcom,sm8450-tlmm";
3189 gpio-controller;
3190 #gpio-cells = <2>;
3191 interrupt-controller;
3192 #interrupt-cells = <2>;
3193 gpio-ranges = <&tlmm 0 0 211>;
3194 wakeup-parent = <&pdc>;
3196 sdc2_default_state: sdc2-default-state {
3197 clk-pins {
3199 drive-strength = <16>;
3200 bias-disable;
3203 cmd-pins {
3205 drive-strength = <16>;
3206 bias-pull-up;
3209 data-pins {
3211 drive-strength = <16>;
3212 bias-pull-up;
3216 sdc2_sleep_state: sdc2-sleep-state {
3217 clk-pins {
3219 drive-strength = <2>;
3220 bias-disable;
3223 cmd-pins {
3225 drive-strength = <2>;
3226 bias-pull-up;
3229 data-pins {
3231 drive-strength = <2>;
3232 bias-pull-up;
3236 cci0_default: cci0-default-state {
3240 drive-strength = <2>;
3241 bias-pull-up;
3244 cci0_sleep: cci0-sleep-state {
3248 drive-strength = <2>;
3249 bias-pull-down;
3252 cci1_default: cci1-default-state {
3256 drive-strength = <2>;
3257 bias-pull-up;
3260 cci1_sleep: cci1-sleep-state {
3264 drive-strength = <2>;
3265 bias-pull-down;
3268 cci2_default: cci2-default-state {
3272 drive-strength = <2>;
3273 bias-pull-up;
3276 cci2_sleep: cci2-sleep-state {
3280 drive-strength = <2>;
3281 bias-pull-down;
3284 cci3_default: cci3-default-state {
3288 drive-strength = <2>;
3289 bias-pull-up;
3292 cci3_sleep: cci3-sleep-state {
3296 drive-strength = <2>;
3297 bias-pull-down;
3300 pcie0_default_state: pcie0-default-state {
3301 perst-pins {
3304 drive-strength = <2>;
3305 bias-pull-down;
3308 clkreq-pins {
3311 drive-strength = <2>;
3312 bias-pull-up;
3315 wake-pins {
3318 drive-strength = <2>;
3319 bias-pull-up;
3323 pcie1_default_state: pcie1-default-state {
3324 perst-pins {
3327 drive-strength = <2>;
3328 bias-pull-down;
3331 clkreq-pins {
3334 drive-strength = <2>;
3335 bias-pull-up;
3338 wake-pins {
3341 drive-strength = <2>;
3342 bias-pull-up;
3346 qup_i2c0_data_clk: qup-i2c0-data-clk-state {
3351 qup_i2c1_data_clk: qup-i2c1-data-clk-state {
3356 qup_i2c2_data_clk: qup-i2c2-data-clk-state {
3361 qup_i2c3_data_clk: qup-i2c3-data-clk-state {
3366 qup_i2c4_data_clk: qup-i2c4-data-clk-state {
3371 qup_i2c5_data_clk: qup-i2c5-data-clk-state {
3376 qup_i2c6_data_clk: qup-i2c6-data-clk-state {
3381 qup_i2c8_data_clk: qup-i2c8-data-clk-state {
3386 qup_i2c9_data_clk: qup-i2c9-data-clk-state {
3391 qup_i2c10_data_clk: qup-i2c10-data-clk-state {
3396 qup_i2c11_data_clk: qup-i2c11-data-clk-state {
3401 qup_i2c12_data_clk: qup-i2c12-data-clk-state {
3406 qup_i2c13_data_clk: qup-i2c13-data-clk-state {
3409 drive-strength = <2>;
3410 bias-pull-up;
3413 qup_i2c14_data_clk: qup-i2c14-data-clk-state {
3416 drive-strength = <2>;
3417 bias-pull-up;
3420 qup_i2c15_data_clk: qup-i2c15-data-clk-state {
3425 qup_i2c16_data_clk: qup-i2c16-data-clk-state {
3430 qup_i2c17_data_clk: qup-i2c17-data-clk-state {
3435 qup_i2c18_data_clk: qup-i2c18-data-clk-state {
3440 qup_i2c19_data_clk: qup-i2c19-data-clk-state {
3445 qup_i2c20_data_clk: qup-i2c20-data-clk-state {
3450 qup_i2c21_data_clk: qup-i2c21-data-clk-state {
3455 qup_spi0_cs: qup-spi0-cs-state {
3460 qup_spi0_data_clk: qup-spi0-data-clk-state {
3465 qup_spi1_cs: qup-spi1-cs-state {
3470 qup_spi1_data_clk: qup-spi1-data-clk-state {
3475 qup_spi2_cs: qup-spi2-cs-state {
3480 qup_spi2_data_clk: qup-spi2-data-clk-state {
3485 qup_spi3_cs: qup-spi3-cs-state {
3490 qup_spi3_data_clk: qup-spi3-data-clk-state {
3495 qup_spi4_cs: qup-spi4-cs-state {
3498 drive-strength = <6>;
3499 bias-disable;
3502 qup_spi4_data_clk: qup-spi4-data-clk-state {
3507 qup_spi5_cs: qup-spi5-cs-state {
3512 qup_spi5_data_clk: qup-spi5-data-clk-state {
3517 qup_spi6_cs: qup-spi6-cs-state {
3522 qup_spi6_data_clk: qup-spi6-data-clk-state {
3527 qup_spi8_cs: qup-spi8-cs-state {
3532 qup_spi8_data_clk: qup-spi8-data-clk-state {
3537 qup_spi9_cs: qup-spi9-cs-state {
3542 qup_spi9_data_clk: qup-spi9-data-clk-state {
3547 qup_spi10_cs: qup-spi10-cs-state {
3552 qup_spi10_data_clk: qup-spi10-data-clk-state {
3557 qup_spi11_cs: qup-spi11-cs-state {
3562 qup_spi11_data_clk: qup-spi11-data-clk-state {
3567 qup_spi12_cs: qup-spi12-cs-state {
3572 qup_spi12_data_clk: qup-spi12-data-clk-state {
3577 qup_spi13_cs: qup-spi13-cs-state {
3582 qup_spi13_data_clk: qup-spi13-data-clk-state {
3587 qup_spi14_cs: qup-spi14-cs-state {
3592 qup_spi14_data_clk: qup-spi14-data-clk-state {
3597 qup_spi15_cs: qup-spi15-cs-state {
3602 qup_spi15_data_clk: qup-spi15-data-clk-state {
3607 qup_spi16_cs: qup-spi16-cs-state {
3612 qup_spi16_data_clk: qup-spi16-data-clk-state {
3617 qup_spi17_cs: qup-spi17-cs-state {
3622 qup_spi17_data_clk: qup-spi17-data-clk-state {
3627 qup_spi18_cs: qup-spi18-cs-state {
3630 drive-strength = <6>;
3631 bias-disable;
3634 qup_spi18_data_clk: qup-spi18-data-clk-state {
3637 drive-strength = <6>;
3638 bias-disable;
3641 qup_spi19_cs: qup-spi19-cs-state {
3644 drive-strength = <6>;
3645 bias-disable;
3648 qup_spi19_data_clk: qup-spi19-data-clk-state {
3651 drive-strength = <6>;
3652 bias-disable;
3655 qup_spi20_cs: qup-spi20-cs-state {
3660 qup_spi20_data_clk: qup-spi20-data-clk-state {
3665 qup_spi21_cs: qup-spi21-cs-state {
3670 qup_spi21_data_clk: qup-spi21-data-clk-state {
3675 qup_uart7_rx: qup-uart7-rx-state {
3678 drive-strength = <2>;
3679 bias-disable;
3682 qup_uart7_tx: qup-uart7-tx-state {
3685 drive-strength = <2>;
3686 bias-disable;
3689 qup_uart20_default: qup-uart20-default-state {
3696 compatible = "qcom,sm8450-lpass-lpi-pinctrl";
3699 gpio-controller;
3700 #gpio-cells = <2>;
3701 gpio-ranges = <&lpass_tlmm 0 0 23>;
3705 clock-names = "core", "audio";
3707 tx_swr_active: tx-swr-active-state {
3708 clk-pins {
3711 drive-strength = <2>;
3712 slew-rate = <1>;
3713 bias-disable;
3716 data-pins {
3719 drive-strength = <2>;
3720 slew-rate = <1>;
3721 bias-bus-hold;
3725 rx_swr_active: rx-swr-active-state {
3726 clk-pins {
3729 drive-strength = <2>;
3730 slew-rate = <1>;
3731 bias-disable;
3734 data-pins {
3737 drive-strength = <2>;
3738 slew-rate = <1>;
3739 bias-bus-hold;
3743 dmic01_default: dmic01-default-state {
3744 clk-pins {
3747 drive-strength = <8>;
3748 output-high;
3751 data-pins {
3754 drive-strength = <8>;
3758 dmic02_default: dmic02-default-state {
3759 clk-pins {
3762 drive-strength = <8>;
3763 output-high;
3766 data-pins {
3769 drive-strength = <8>;
3773 wsa_swr_active: wsa-swr-active-state {
3774 clk-pins {
3777 drive-strength = <2>;
3778 slew-rate = <1>;
3779 bias-disable;
3782 data-pins {
3785 drive-strength = <2>;
3786 slew-rate = <1>;
3787 bias-bus-hold;
3791 wsa2_swr_active: wsa2-swr-active-state {
3792 clk-pins {
3795 drive-strength = <2>;
3796 slew-rate = <1>;
3797 bias-disable;
3800 data-pins {
3803 drive-strength = <2>;
3804 slew-rate = <1>;
3805 bias-bus-hold;
3811 compatible = "qcom,sm8450-imem", "syscon", "simple-mfd";
3815 #address-cells = <1>;
3816 #size-cells = <1>;
3818 pil-reloc@94c {
3819 compatible = "qcom,pil-reloc-info";
3825 compatible = "qcom,sm8450-smmu-500", "arm,mmu-500";
3827 #iommu-cells = <2>;
3828 #global-interrupts = <1>;
3928 intc: interrupt-controller@17100000 {
3929 compatible = "arm,gic-v3";
3930 #interrupt-cells = <3>;
3931 interrupt-controller;
3932 #redistributor-regions = <1>;
3933 redistributor-stride = <0x0 0x40000>;
3937 #address-cells = <2>;
3938 #size-cells = <2>;
3941 gic_its: msi-controller@17140000 {
3942 compatible = "arm,gic-v3-its";
3944 msi-controller;
3945 #msi-cells = <1>;
3950 compatible = "arm,armv7-timer-mem";
3951 #address-cells = <1>;
3952 #size-cells = <1>;
3955 clock-frequency = <19200000>;
3958 frame-number = <0>;
3966 frame-number = <1>;
3973 frame-number = <2>;
3980 frame-number = <3>;
3987 frame-number = <4>;
3994 frame-number = <5>;
4001 frame-number = <6>;
4010 compatible = "qcom,rpmh-rsc";
4015 reg-names = "drv-0", "drv-1", "drv-2", "drv-3";
4019 qcom,tcs-offset = <0xd00>;
4020 qcom,drv-id = <2>;
4021 qcom,tcs-config = <ACTIVE_TCS 3>, <SLEEP_TCS 2>,
4023 power-domains = <&CLUSTER_PD>;
4025 apps_bcm_voter: bcm-voter {
4026 compatible = "qcom,bcm-voter";
4029 rpmhcc: clock-controller {
4030 compatible = "qcom,sm8450-rpmh-clk";
4031 #clock-cells = <1>;
4032 clock-names = "xo";
4036 rpmhpd: power-controller {
4037 compatible = "qcom,sm8450-rpmhpd";
4038 #power-domain-cells = <1>;
4039 operating-points-v2 = <&rpmhpd_opp_table>;
4041 rpmhpd_opp_table: opp-table {
4042 compatible = "operating-points-v2";
4045 opp-level = <RPMH_REGULATOR_LEVEL_RETENTION>;
4049 opp-level = <RPMH_REGULATOR_LEVEL_MIN_SVS>;
4053 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS_D1>;
4057 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>;
4061 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS_L1>;
4065 opp-level = <RPMH_REGULATOR_LEVEL_SVS>;
4069 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L0>;
4073 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>;
4077 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L2>;
4081 opp-level = <RPMH_REGULATOR_LEVEL_NOM>;
4085 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>;
4089 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L2>;
4093 opp-level = <RPMH_REGULATOR_LEVEL_TURBO>;
4097 opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L1>;
4104 compatible = "qcom,sm8450-cpufreq-epss", "qcom,cpufreq-epss";
4108 reg-names = "freq-domain0", "freq-domain1", "freq-domain2";
4110 clock-names = "xo", "alternate";
4114 interrupt-names = "dcvsh-irq-0", "dcvsh-irq-1", "dcvsh-irq-2";
4115 #freq-domain-cells = <1>;
4116 #clock-cells = <1>;
4120 compatible = "qcom,sm8450-gem-noc";
4122 #interconnect-cells = <2>;
4123 qcom,bcm-voters = <&apps_bcm_voter>;
4126 system-cache-controller@19200000 {
4127 compatible = "qcom,sm8450-llcc";
4131 reg-names = "llcc0_base", "llcc1_base", "llcc2_base",
4137 compatible = "qcom,sm8450-ufshc", "qcom,ufshc",
4138 "jedec,ufs-2.0";
4142 phy-names = "ufsphy";
4143 lanes-per-direction = <2>;
4144 #reset-cells = <1>;
4146 reset-names = "rst";
4148 power-domains = <&gcc UFS_PHY_GDSC>;
4151 dma-coherent;
4155 interconnect-names = "ufs-ddr", "cpu-ufs";
4156 clock-names =
4174 freq-table-hz =
4189 compatible = "qcom,sm8450-qmp-ufs-phy";
4191 #address-cells = <2>;
4192 #size-cells = <2>;
4194 clock-names = "ref", "ref_aux", "qref";
4200 reset-names = "ufsphy";
4209 #clock-cells = <1>;
4210 #phy-cells = <0>;
4215 compatible = "qcom,sm8450-inline-crypto-engine",
4216 "qcom,inline-crypto-engine";
4221 cryptobam: dma-controller@1dc4000 {
4222 compatible = "qcom,bam-v1.7.4", "qcom,bam-v1.7.0";
4225 #dma-cells = <1>;
4227 qcom,controlled-remotely;
4236 compatible = "qcom,sm8450-qce", "qcom,sm8150-qce", "qcom,qce";
4239 dma-names = "rx", "tx";
4246 interconnect-names = "memory";
4250 compatible = "qcom,sm8450-sdhci", "qcom,sdhci-msm-v5";
4255 interrupt-names = "hc_irq", "pwr_irq";
4260 clock-names = "iface", "core", "xo";
4264 interconnect-names = "sdhc-ddr","cpu-sdhc";
4266 power-domains = <&rpmhpd RPMHPD_CX>;
4267 operating-points-v2 = <&sdhc2_opp_table>;
4268 bus-width = <4>;
4269 dma-coherent;
4271 /* Forbid SDR104/SDR50 - broken hw! */
4272 sdhci-caps-mask = <0x3 0x0>;
4276 sdhc2_opp_table: opp-table {
4277 compatible = "operating-points-v2";
4279 opp-100000000 {
4280 opp-hz = /bits/ 64 <100000000>;
4281 required-opps = <&rpmhpd_opp_low_svs>;
4284 opp-202000000 {
4285 opp-hz = /bits/ 64 <202000000>;
4286 required-opps = <&rpmhpd_opp_svs_l1>;
4292 compatible = "qcom,sm8450-dwc3", "qcom,dwc3";
4295 #address-cells = <2>;
4296 #size-cells = <2>;
4305 clock-names = "cfg_noc",
4312 assigned-clocks = <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>,
4314 assigned-clock-rates = <19200000>, <200000000>;
4316 interrupts-extended = <&intc GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>,
4320 interrupt-names = "hs_phy_irq",
4325 power-domains = <&gcc USB30_PRIM_GDSC>;
4331 interconnect-names = "usb-ddr", "apps-usb";
4341 phy-names = "usb2-phy", "usb3-phy";
4344 #address-cells = <1>;
4345 #size-cells = <0>;
4365 compatible = "qcom,sm8450-nsp-noc";
4367 #interconnect-cells = <2>;
4368 qcom,bcm-voters = <&apps_bcm_voter>;
4372 compatible = "qcom,sm8450-lpass-ag-noc";
4374 #interconnect-cells = <2>;
4375 qcom,bcm-voters = <&apps_bcm_voter>;
4382 thermal-zones {
4383 aoss0-thermal {
4384 polling-delay-passive = <0>;
4385 polling-delay = <0>;
4386 thermal-sensors = <&tsens0 0>;
4389 thermal-engine-config {
4395 reset-mon-cfg {
4403 cpuss0-thermal {
4404 polling-delay-passive = <0>;
4405 polling-delay = <0>;
4406 thermal-sensors = <&tsens0 1>;
4409 thermal-engine-config {
4415 reset-mon-cfg {
4423 cpuss1-thermal {
4424 polling-delay-passive = <0>;
4425 polling-delay = <0>;
4426 thermal-sensors = <&tsens0 2>;
4429 thermal-engine-config {
4435 reset-mon-cfg {
4443 cpuss3-thermal {
4444 polling-delay-passive = <0>;
4445 polling-delay = <0>;
4446 thermal-sensors = <&tsens0 3>;
4449 thermal-engine-config {
4455 reset-mon-cfg {
4463 cpuss4-thermal {
4464 polling-delay-passive = <0>;
4465 polling-delay = <0>;
4466 thermal-sensors = <&tsens0 4>;
4469 thermal-engine-config {
4475 reset-mon-cfg {
4483 cpu4-top-thermal {
4484 polling-delay-passive = <0>;
4485 polling-delay = <0>;
4486 thermal-sensors = <&tsens0 5>;
4489 cpu4_top_alert0: trip-point0 {
4495 cpu4_top_alert1: trip-point1 {
4501 cpu4_top_crit: cpu-crit {
4509 cpu4-bottom-thermal {
4510 polling-delay-passive = <0>;
4511 polling-delay = <0>;
4512 thermal-sensors = <&tsens0 6>;
4515 cpu4_bottom_alert0: trip-point0 {
4521 cpu4_bottom_alert1: trip-point1 {
4527 cpu4_bottom_crit: cpu-crit {
4535 cpu5-top-thermal {
4536 polling-delay-passive = <0>;
4537 polling-delay = <0>;
4538 thermal-sensors = <&tsens0 7>;
4541 cpu5_top_alert0: trip-point0 {
4547 cpu5_top_alert1: trip-point1 {
4553 cpu5_top_crit: cpu-crit {
4561 cpu5-bottom-thermal {
4562 polling-delay-passive = <0>;
4563 polling-delay = <0>;
4564 thermal-sensors = <&tsens0 8>;
4567 cpu5_bottom_alert0: trip-point0 {
4573 cpu5_bottom_alert1: trip-point1 {
4579 cpu5_bottom_crit: cpu-crit {
4587 cpu6-top-thermal {
4588 polling-delay-passive = <0>;
4589 polling-delay = <0>;
4590 thermal-sensors = <&tsens0 9>;
4593 cpu6_top_alert0: trip-point0 {
4599 cpu6_top_alert1: trip-point1 {
4605 cpu6_top_crit: cpu-crit {
4613 cpu6-bottom-thermal {
4614 polling-delay-passive = <0>;
4615 polling-delay = <0>;
4616 thermal-sensors = <&tsens0 10>;
4619 cpu6_bottom_alert0: trip-point0 {
4625 cpu6_bottom_alert1: trip-point1 {
4631 cpu6_bottom_crit: cpu-crit {
4639 cpu7-top-thermal {
4640 polling-delay-passive = <0>;
4641 polling-delay = <0>;
4642 thermal-sensors = <&tsens0 11>;
4645 cpu7_top_alert0: trip-point0 {
4651 cpu7_top_alert1: trip-point1 {
4657 cpu7_top_crit: cpu-crit {
4665 cpu7-middle-thermal {
4666 polling-delay-passive = <0>;
4667 polling-delay = <0>;
4668 thermal-sensors = <&tsens0 12>;
4671 cpu7_middle_alert0: trip-point0 {
4677 cpu7_middle_alert1: trip-point1 {
4683 cpu7_middle_crit: cpu-crit {
4691 cpu7-bottom-thermal {
4692 polling-delay-passive = <0>;
4693 polling-delay = <0>;
4694 thermal-sensors = <&tsens0 13>;
4697 cpu7_bottom_alert0: trip-point0 {
4703 cpu7_bottom_alert1: trip-point1 {
4709 cpu7_bottom_crit: cpu-crit {
4717 gpu-top-thermal {
4718 polling-delay-passive = <10>;
4719 polling-delay = <0>;
4720 thermal-sensors = <&tsens0 14>;
4723 thermal-engine-config {
4729 thermal-hal-config {
4735 reset-mon-cfg {
4741 gpu0_tj_cfg: tj-cfg {
4749 gpu-bottom-thermal {
4750 polling-delay-passive = <10>;
4751 polling-delay = <0>;
4752 thermal-sensors = <&tsens0 15>;
4755 thermal-engine-config {
4761 thermal-hal-config {
4767 reset-mon-cfg {
4773 gpu1_tj_cfg: tj-cfg {
4781 aoss1-thermal {
4782 polling-delay-passive = <0>;
4783 polling-delay = <0>;
4784 thermal-sensors = <&tsens1 0>;
4787 thermal-engine-config {
4793 reset-mon-cfg {
4801 cpu0-thermal {
4802 polling-delay-passive = <0>;
4803 polling-delay = <0>;
4804 thermal-sensors = <&tsens1 1>;
4807 cpu0_alert0: trip-point0 {
4813 cpu0_alert1: trip-point1 {
4819 cpu0_crit: cpu-crit {
4827 cpu1-thermal {
4828 polling-delay-passive = <0>;
4829 polling-delay = <0>;
4830 thermal-sensors = <&tsens1 2>;
4833 cpu1_alert0: trip-point0 {
4839 cpu1_alert1: trip-point1 {
4845 cpu1_crit: cpu-crit {
4853 cpu2-thermal {
4854 polling-delay-passive = <0>;
4855 polling-delay = <0>;
4856 thermal-sensors = <&tsens1 3>;
4859 cpu2_alert0: trip-point0 {
4865 cpu2_alert1: trip-point1 {
4871 cpu2_crit: cpu-crit {
4879 cpu3-thermal {
4880 polling-delay-passive = <0>;
4881 polling-delay = <0>;
4882 thermal-sensors = <&tsens1 4>;
4885 cpu3_alert0: trip-point0 {
4891 cpu3_alert1: trip-point1 {
4897 cpu3_crit: cpu-crit {
4905 cdsp0-thermal {
4906 polling-delay-passive = <10>;
4907 polling-delay = <0>;
4908 thermal-sensors = <&tsens1 5>;
4911 thermal-engine-config {
4917 thermal-hal-config {
4923 reset-mon-cfg {
4929 cdsp_0_config: junction-config {
4937 cdsp1-thermal {
4938 polling-delay-passive = <10>;
4939 polling-delay = <0>;
4940 thermal-sensors = <&tsens1 6>;
4943 thermal-engine-config {
4949 thermal-hal-config {
4955 reset-mon-cfg {
4961 cdsp_1_config: junction-config {
4969 cdsp2-thermal {
4970 polling-delay-passive = <10>;
4971 polling-delay = <0>;
4972 thermal-sensors = <&tsens1 7>;
4975 thermal-engine-config {
4981 thermal-hal-config {
4987 reset-mon-cfg {
4993 cdsp_2_config: junction-config {
5001 video-thermal {
5002 polling-delay-passive = <0>;
5003 polling-delay = <0>;
5004 thermal-sensors = <&tsens1 8>;
5007 thermal-engine-config {
5013 reset-mon-cfg {
5021 mem-thermal {
5022 polling-delay-passive = <10>;
5023 polling-delay = <0>;
5024 thermal-sensors = <&tsens1 9>;
5027 thermal-engine-config {
5033 ddr_config0: ddr0-config {
5039 reset-mon-cfg {
5047 modem0-thermal {
5048 polling-delay-passive = <0>;
5049 polling-delay = <0>;
5050 thermal-sensors = <&tsens1 10>;
5053 thermal-engine-config {
5059 mdmss0_config0: mdmss0-config0 {
5065 mdmss0_config1: mdmss0-config1 {
5071 reset-mon-cfg {
5079 modem1-thermal {
5080 polling-delay-passive = <0>;
5081 polling-delay = <0>;
5082 thermal-sensors = <&tsens1 11>;
5085 thermal-engine-config {
5091 mdmss1_config0: mdmss1-config0 {
5097 mdmss1_config1: mdmss1-config1 {
5103 reset-mon-cfg {
5111 modem2-thermal {
5112 polling-delay-passive = <0>;
5113 polling-delay = <0>;
5114 thermal-sensors = <&tsens1 12>;
5117 thermal-engine-config {
5123 mdmss2_config0: mdmss2-config0 {
5129 mdmss2_config1: mdmss2-config1 {
5135 reset-mon-cfg {
5143 modem3-thermal {
5144 polling-delay-passive = <0>;
5145 polling-delay = <0>;
5146 thermal-sensors = <&tsens1 13>;
5149 thermal-engine-config {
5155 mdmss3_config0: mdmss3-config0 {
5161 mdmss3_config1: mdmss3-config1 {
5167 reset-mon-cfg {
5175 camera0-thermal {
5176 polling-delay-passive = <0>;
5177 polling-delay = <0>;
5178 thermal-sensors = <&tsens1 14>;
5181 thermal-engine-config {
5187 reset-mon-cfg {
5195 camera1-thermal {
5196 polling-delay-passive = <0>;
5197 polling-delay = <0>;
5198 thermal-sensors = <&tsens1 15>;
5201 thermal-engine-config {
5207 reset-mon-cfg {
5217 compatible = "arm,armv8-timer";
5222 clock-frequency = <19200000>;