Lines Matching +full:0 +full:x0c440000
36 #clock-cells = <0>;
42 #clock-cells = <0>;
49 #size-cells = <0>;
51 CPU0: cpu@0 {
54 reg = <0x0 0x0>;
59 qcom,freq-domain = <&cpufreq_hw 0>;
61 clocks = <&cpufreq_hw 0>;
78 reg = <0x0 0x100>;
83 qcom,freq-domain = <&cpufreq_hw 0>;
85 clocks = <&cpufreq_hw 0>;
97 reg = <0x0 0x200>;
102 qcom,freq-domain = <&cpufreq_hw 0>;
104 clocks = <&cpufreq_hw 0>;
116 reg = <0x0 0x300>;
121 qcom,freq-domain = <&cpufreq_hw 0>;
123 clocks = <&cpufreq_hw 0>;
135 reg = <0x0 0x400>;
154 reg = <0x0 0x500>;
173 reg = <0x0 0x600>;
192 reg = <0x0 0x700>;
247 LITTLE_CPU_SLEEP_0: cpu-sleep-0-0 {
250 arm,psci-suspend-param = <0x40000004>;
257 BIG_CPU_SLEEP_0: cpu-sleep-1-0 {
260 arm,psci-suspend-param = <0x40000004>;
269 CLUSTER_SLEEP_0: cluster-sleep-0 {
271 arm,psci-suspend-param = <0x41000044>;
279 arm,psci-suspend-param = <0x4100c344>;
290 qcom,dload-mode = <&tcsr 0x13000>;
291 interconnects = <&aggre2_noc MASTER_CRYPTO 0 &mc_virt SLAVE_EBI1 0>;
296 clk_virt: interconnect-0 {
311 reg = <0x0 0xa0000000 0x0 0x0>;
324 #power-domain-cells = <0>;
330 #power-domain-cells = <0>;
336 #power-domain-cells = <0>;
342 #power-domain-cells = <0>;
348 #power-domain-cells = <0>;
354 #power-domain-cells = <0>;
360 #power-domain-cells = <0>;
366 #power-domain-cells = <0>;
372 #power-domain-cells = <0>;
402 reg = <0x0 0x80000000 0x0 0x600000>;
407 reg = <0x0 0x80600000 0x0 0x40000>;
412 reg = <0x0 0x80640000 0x0 0x180000>;
417 reg = <0x0 0x807c0000 0x0 0x40000>;
422 reg = <0x0 0x80800000 0x0 0x60000>;
428 reg = <0x0 0x80860000 0x0 0x20000>;
433 reg = <0x0 0x80880000 0x0 0x20000>;
438 reg = <0x0 0x808a0000 0x0 0x40000>;
443 reg = <0x0 0x808e0000 0x0 0x4000>;
448 reg = <0x0 0x808e4000 0x0 0x10000>;
455 reg = <0x0 0x80900000 0x0 0x200000>;
461 reg = <0x0 0x80b00000 0x0 0x100000>;
466 reg = <0x0 0x80c00000 0x0 0x4600000>;
471 reg = <0x0 0x85700000 0x0 0x700000>;
476 reg = <0x0 0x85e00000 0x0 0x2100000>;
481 reg = <0x0 0x88000000 0x0 0x1900000>;
486 reg = <0x0 0x89900000 0x0 0x2000000>;
491 reg = <0x0 0x8b900000 0x0 0x10000>;
496 reg = <0x0 0x8b910000 0x0 0xa000>;
501 reg = <0x0 0x8b91a000 0x0 0x2000>;
506 reg = <0x0 0x8ba00000 0x0 0x180000>;
512 reg = <0x0 0x8bb80000 0x0 0x60000>;
518 reg = <0x0 0x8bbe0000 0x0 0x20000>;
523 reg = <0x0 0x8bc00000 0x0 0x13200000>;
528 reg = <0x0 0x9ee00000 0x0 0x700000>;
533 reg = <0x0 0x9f500000 0x0 0x800000>;
539 reg = <0x0 0x9fd00000 0x0 0x280000>;
547 reg = <0x0 0xa6e00000 0x0 0x40000>;
552 reg = <0x0 0xa6f00000 0x0 0x100000>;
558 /* Linux kernel image is loaded at 0xa0000000 */
561 reg = <0x0 0xbb000000 0x0 0x5000000>;
566 reg = <0x0 0xc0000000 0x0 0x20000000>;
571 reg = <0x0 0xe0000000 0x0 0x600000>;
576 reg = <0x0 0xe0600000 0x0 0x400000>;
581 reg = <0x0 0xe0a00000 0x0 0x100000>;
586 reg = <0x0 0xe0b00000 0x0 0x4af3000>;
591 reg = <0x0 0xe55f3000 0x0 0x9000>;
596 reg = <0x0 0xe55fc000 0x0 0x4000>;
601 reg = <0x0 0xe5600000 0x0 0x100000>;
606 reg = <0x0 0xe8800000 0x0 0x100000>;
611 reg = <0x0 0xe8900000 0x0 0x1200000>;
616 reg = <0x0 0xe9b00000 0x0 0x500000>;
621 reg = <0x0 0xea000000 0x0 0x3900000>;
626 reg = <0x0 0xed900000 0x0 0x3b00000>;
640 qcom,local-pid = <0>;
664 qcom,local-pid = <0>;
688 qcom,local-pid = <0>;
723 qcom,local-pid = <0>;
738 soc: soc@0 {
741 ranges = <0 0 0 0 0x10 0>;
742 dma-ranges = <0 0 0 0 0x10 0>;
747 reg = <0x0 0x00100000 0x0 0x1f4200>;
755 <0>,
756 <&ufs_mem_phy_lanes 0>,
774 reg = <0 0x00800000 0 0x60000>;
788 dma-channel-mask = <0x7e>;
789 iommus = <&apps_smmu 0x496 0x0>;
795 reg = <0x0 0x008c0000 0x0 0x2000>;
799 iommus = <&apps_smmu 0x483 0x0>;
807 reg = <0x0 0x00880000 0x0 0x4000>;
811 pinctrl-0 = <&qup_i2c15_data_clk>;
814 #size-cells = <0>;
815 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>,
816 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>,
817 <&aggre2_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>;
819 dmas = <&gpi_dma2 0 0 QCOM_GPI_I2C>,
820 <&gpi_dma2 1 0 QCOM_GPI_I2C>;
827 reg = <0x0 0x00880000 0x0 0x4000>;
832 pinctrl-0 = <&qup_spi15_data_clk>, <&qup_spi15_cs>;
833 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>,
834 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>;
836 dmas = <&gpi_dma2 0 0 QCOM_GPI_SPI>,
837 <&gpi_dma2 1 0 QCOM_GPI_SPI>;
840 #size-cells = <0>;
846 reg = <0x0 0x00884000 0x0 0x4000>;
850 pinctrl-0 = <&qup_i2c16_data_clk>;
853 #size-cells = <0>;
854 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>,
855 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>,
856 <&aggre2_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>;
858 dmas = <&gpi_dma2 0 1 QCOM_GPI_I2C>,
866 reg = <0x0 0x00884000 0x0 0x4000>;
871 pinctrl-0 = <&qup_spi16_data_clk>, <&qup_spi16_cs>;
872 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>,
873 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>;
875 dmas = <&gpi_dma2 0 1 QCOM_GPI_SPI>,
879 #size-cells = <0>;
885 reg = <0x0 0x00888000 0x0 0x4000>;
889 pinctrl-0 = <&qup_i2c17_data_clk>;
892 #size-cells = <0>;
893 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>,
894 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>,
895 <&aggre2_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>;
897 dmas = <&gpi_dma2 0 2 QCOM_GPI_I2C>,
905 reg = <0x0 0x00888000 0x0 0x4000>;
910 pinctrl-0 = <&qup_spi17_data_clk>, <&qup_spi17_cs>;
911 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>,
912 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>;
914 dmas = <&gpi_dma2 0 2 QCOM_GPI_SPI>,
918 #size-cells = <0>;
924 reg = <0x0 0x0088c000 0x0 0x4000>;
928 pinctrl-0 = <&qup_i2c18_data_clk>;
931 #size-cells = <0>;
932 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>,
933 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>,
934 <&aggre2_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>;
936 dmas = <&gpi_dma2 0 3 QCOM_GPI_I2C>,
944 reg = <0 0x0088c000 0 0x4000>;
949 pinctrl-0 = <&qup_spi18_data_clk>, <&qup_spi18_cs>;
950 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>,
951 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>;
953 dmas = <&gpi_dma2 0 3 QCOM_GPI_I2C>,
957 #size-cells = <0>;
963 reg = <0x0 0x00890000 0x0 0x4000>;
967 pinctrl-0 = <&qup_i2c19_data_clk>;
970 #size-cells = <0>;
971 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>,
972 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>,
973 <&aggre2_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>;
975 dmas = <&gpi_dma2 0 4 QCOM_GPI_I2C>,
983 reg = <0 0x00890000 0 0x4000>;
988 pinctrl-0 = <&qup_spi19_data_clk>, <&qup_spi19_cs>;
989 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>,
990 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>;
992 dmas = <&gpi_dma2 0 4 QCOM_GPI_I2C>,
996 #size-cells = <0>;
1002 reg = <0x0 0x00894000 0x0 0x4000>;
1006 pinctrl-0 = <&qup_i2c20_data_clk>;
1009 #size-cells = <0>;
1010 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>,
1011 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>,
1012 <&aggre2_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>;
1014 dmas = <&gpi_dma2 0 5 QCOM_GPI_I2C>,
1022 reg = <0 0x00894000 0 0x4000>;
1026 pinctrl-0 = <&qup_uart20_default>;
1033 reg = <0 0x00894000 0 0x4000>;
1038 pinctrl-0 = <&qup_spi20_data_clk>, <&qup_spi20_cs>;
1039 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>,
1040 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>;
1042 dmas = <&gpi_dma2 0 5 QCOM_GPI_SPI>,
1046 #size-cells = <0>;
1052 reg = <0x0 0x00898000 0x0 0x4000>;
1056 pinctrl-0 = <&qup_i2c21_data_clk>;
1059 #size-cells = <0>;
1060 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>,
1061 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>,
1062 <&aggre2_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>;
1064 dmas = <&gpi_dma2 0 6 QCOM_GPI_I2C>,
1072 reg = <0 0x00898000 0 0x4000>;
1077 pinctrl-0 = <&qup_spi21_data_clk>, <&qup_spi21_cs>;
1078 interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>,
1079 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>;
1081 dmas = <&gpi_dma2 0 6 QCOM_GPI_SPI>,
1085 #size-cells = <0>;
1093 reg = <0 0x00900000 0 0x60000>;
1107 dma-channel-mask = <0x7e>;
1108 iommus = <&apps_smmu 0x5b6 0x0>;
1114 reg = <0x0 0x009c0000 0x0 0x2000>;
1118 iommus = <&apps_smmu 0x5a3 0x0>;
1119 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>;
1128 reg = <0x0 0x00980000 0x0 0x4000>;
1132 pinctrl-0 = <&qup_i2c0_data_clk>;
1135 #size-cells = <0>;
1136 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>,
1137 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>,
1138 <&aggre2_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>;
1140 dmas = <&gpi_dma0 0 0 QCOM_GPI_I2C>,
1141 <&gpi_dma0 1 0 QCOM_GPI_I2C>;
1148 reg = <0x0 0x00980000 0x0 0x4000>;
1153 pinctrl-0 = <&qup_spi0_data_clk>, <&qup_spi0_cs>;
1156 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>,
1157 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>,
1158 <&aggre2_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>;
1160 dmas = <&gpi_dma0 0 0 QCOM_GPI_SPI>,
1161 <&gpi_dma0 1 0 QCOM_GPI_SPI>;
1164 #size-cells = <0>;
1170 reg = <0x0 0x00984000 0x0 0x4000>;
1174 pinctrl-0 = <&qup_i2c1_data_clk>;
1177 #size-cells = <0>;
1178 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>,
1179 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>,
1180 <&aggre2_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>;
1182 dmas = <&gpi_dma0 0 1 QCOM_GPI_I2C>,
1190 reg = <0x0 0x00984000 0x0 0x4000>;
1195 pinctrl-0 = <&qup_spi1_data_clk>, <&qup_spi1_cs>;
1196 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>,
1197 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>,
1198 <&aggre2_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>;
1200 dmas = <&gpi_dma0 0 1 QCOM_GPI_SPI>,
1204 #size-cells = <0>;
1210 reg = <0x0 0x00988000 0x0 0x4000>;
1214 pinctrl-0 = <&qup_i2c2_data_clk>;
1217 #size-cells = <0>;
1218 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>,
1219 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>,
1220 <&aggre2_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>;
1222 dmas = <&gpi_dma0 0 2 QCOM_GPI_I2C>,
1230 reg = <0x0 0x00988000 0x0 0x4000>;
1235 pinctrl-0 = <&qup_spi2_data_clk>, <&qup_spi2_cs>;
1236 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>,
1237 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>,
1238 <&aggre2_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>;
1240 dmas = <&gpi_dma0 0 2 QCOM_GPI_SPI>,
1244 #size-cells = <0>;
1251 reg = <0x0 0x0098c000 0x0 0x4000>;
1255 pinctrl-0 = <&qup_i2c3_data_clk>;
1258 #size-cells = <0>;
1259 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>,
1260 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>,
1261 <&aggre2_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>;
1263 dmas = <&gpi_dma0 0 3 QCOM_GPI_I2C>,
1271 reg = <0x0 0x0098c000 0x0 0x4000>;
1276 pinctrl-0 = <&qup_spi3_data_clk>, <&qup_spi3_cs>;
1277 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>,
1278 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>,
1279 <&aggre2_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>;
1281 dmas = <&gpi_dma0 0 3 QCOM_GPI_SPI>,
1285 #size-cells = <0>;
1291 reg = <0x0 0x00990000 0x0 0x4000>;
1295 pinctrl-0 = <&qup_i2c4_data_clk>;
1298 #size-cells = <0>;
1299 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>,
1300 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>,
1301 <&aggre2_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>;
1303 dmas = <&gpi_dma0 0 4 QCOM_GPI_I2C>,
1311 reg = <0x0 0x00990000 0x0 0x4000>;
1316 pinctrl-0 = <&qup_spi4_data_clk>, <&qup_spi4_cs>;
1319 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>,
1320 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>,
1321 <&aggre2_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>;
1323 dmas = <&gpi_dma0 0 4 QCOM_GPI_SPI>,
1327 #size-cells = <0>;
1333 reg = <0x0 0x00994000 0x0 0x4000>;
1337 pinctrl-0 = <&qup_i2c5_data_clk>;
1340 #size-cells = <0>;
1341 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>,
1342 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>,
1343 <&aggre2_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>;
1345 dmas = <&gpi_dma0 0 5 QCOM_GPI_I2C>,
1353 reg = <0x0 0x00994000 0x0 0x4000>;
1358 pinctrl-0 = <&qup_spi5_data_clk>, <&qup_spi5_cs>;
1359 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>,
1360 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>,
1361 <&aggre2_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>;
1363 dmas = <&gpi_dma0 0 5 QCOM_GPI_SPI>,
1367 #size-cells = <0>;
1374 reg = <0x0 0x00998000 0x0 0x4000>;
1378 pinctrl-0 = <&qup_i2c6_data_clk>;
1381 #size-cells = <0>;
1382 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>,
1383 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>,
1384 <&aggre2_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>;
1386 dmas = <&gpi_dma0 0 6 QCOM_GPI_I2C>,
1394 reg = <0x0 0x00998000 0x0 0x4000>;
1399 pinctrl-0 = <&qup_spi6_data_clk>, <&qup_spi6_cs>;
1400 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>,
1401 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>,
1402 <&aggre2_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>;
1404 dmas = <&gpi_dma0 0 6 QCOM_GPI_SPI>,
1408 #size-cells = <0>;
1414 reg = <0 0x0099c000 0 0x4000>;
1418 pinctrl-0 = <&qup_uart7_tx>, <&qup_uart7_rx>;
1427 reg = <0 0x00a00000 0 0x60000>;
1441 dma-channel-mask = <0x7e>;
1442 iommus = <&apps_smmu 0x56 0x0>;
1448 reg = <0x0 0x00ac0000 0x0 0x6000>;
1452 iommus = <&apps_smmu 0x43 0x0>;
1453 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>;
1462 reg = <0x0 0x00a80000 0x0 0x4000>;
1466 pinctrl-0 = <&qup_i2c8_data_clk>;
1469 #size-cells = <0>;
1470 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>,
1471 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>,
1472 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>;
1474 dmas = <&gpi_dma1 0 0 QCOM_GPI_I2C>,
1475 <&gpi_dma1 1 0 QCOM_GPI_I2C>;
1482 reg = <0x0 0x00a80000 0x0 0x4000>;
1487 pinctrl-0 = <&qup_spi8_data_clk>, <&qup_spi8_cs>;
1488 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>,
1489 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>,
1490 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>;
1492 dmas = <&gpi_dma1 0 0 QCOM_GPI_SPI>,
1493 <&gpi_dma1 1 0 QCOM_GPI_SPI>;
1496 #size-cells = <0>;
1502 reg = <0x0 0x00a84000 0x0 0x4000>;
1506 pinctrl-0 = <&qup_i2c9_data_clk>;
1509 #size-cells = <0>;
1510 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>,
1511 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>,
1512 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>;
1514 dmas = <&gpi_dma1 0 1 QCOM_GPI_I2C>,
1522 reg = <0x0 0x00a84000 0x0 0x4000>;
1527 pinctrl-0 = <&qup_spi9_data_clk>, <&qup_spi9_cs>;
1528 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>,
1529 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>,
1530 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>;
1532 dmas = <&gpi_dma1 0 1 QCOM_GPI_SPI>,
1536 #size-cells = <0>;
1542 reg = <0x0 0x00a88000 0x0 0x4000>;
1546 pinctrl-0 = <&qup_i2c10_data_clk>;
1549 #size-cells = <0>;
1550 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>,
1551 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>,
1552 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>;
1554 dmas = <&gpi_dma1 0 2 QCOM_GPI_I2C>,
1562 reg = <0x0 0x00a88000 0x0 0x4000>;
1567 pinctrl-0 = <&qup_spi10_data_clk>, <&qup_spi10_cs>;
1568 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>,
1569 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>,
1570 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>;
1572 dmas = <&gpi_dma1 0 2 QCOM_GPI_SPI>,
1576 #size-cells = <0>;
1582 reg = <0x0 0x00a8c000 0x0 0x4000>;
1586 pinctrl-0 = <&qup_i2c11_data_clk>;
1589 #size-cells = <0>;
1590 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>,
1591 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>,
1592 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>;
1594 dmas = <&gpi_dma1 0 3 QCOM_GPI_I2C>,
1602 reg = <0x0 0x00a8c000 0x0 0x4000>;
1607 pinctrl-0 = <&qup_spi11_data_clk>, <&qup_spi11_cs>;
1608 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>,
1609 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>,
1610 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>;
1612 dmas = <&gpi_dma1 0 3 QCOM_GPI_SPI>,
1616 #size-cells = <0>;
1622 reg = <0x0 0x00a90000 0x0 0x4000>;
1626 pinctrl-0 = <&qup_i2c12_data_clk>;
1629 #size-cells = <0>;
1630 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>,
1631 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>,
1632 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>;
1634 dmas = <&gpi_dma1 0 4 QCOM_GPI_I2C>,
1642 reg = <0x0 0x00a90000 0x0 0x4000>;
1647 pinctrl-0 = <&qup_spi12_data_clk>, <&qup_spi12_cs>;
1648 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>,
1649 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>,
1650 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>;
1652 dmas = <&gpi_dma1 0 4 QCOM_GPI_SPI>,
1656 #size-cells = <0>;
1662 reg = <0 0x00a94000 0 0x4000>;
1666 pinctrl-0 = <&qup_i2c13_data_clk>;
1668 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>,
1669 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>,
1670 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>;
1672 dmas = <&gpi_dma1 0 5 QCOM_GPI_I2C>,
1676 #size-cells = <0>;
1682 reg = <0x0 0x00a94000 0x0 0x4000>;
1687 pinctrl-0 = <&qup_spi13_data_clk>, <&qup_spi13_cs>;
1688 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>,
1689 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>,
1690 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>;
1692 dmas = <&gpi_dma1 0 5 QCOM_GPI_SPI>,
1696 #size-cells = <0>;
1702 reg = <0 0x00a98000 0 0x4000>;
1706 pinctrl-0 = <&qup_i2c14_data_clk>;
1708 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>,
1709 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>,
1710 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>;
1712 dmas = <&gpi_dma1 0 6 QCOM_GPI_I2C>,
1716 #size-cells = <0>;
1722 reg = <0x0 0x00a98000 0x0 0x4000>;
1727 pinctrl-0 = <&qup_spi14_data_clk>, <&qup_spi14_cs>;
1728 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>,
1729 <&system_noc MASTER_A2NOC_SNOC 0 &gem_noc SLAVE_LLCC 0>,
1730 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>;
1732 dmas = <&gpi_dma1 0 6 QCOM_GPI_SPI>,
1736 #size-cells = <0>;
1743 reg = <0 0x010c3000 0 0x1000>;
1748 reg = <0 0x01c00000 0 0x3000>,
1749 <0 0x60000000 0 0xf1d>,
1750 <0 0x60000f20 0 0xa8>,
1751 <0 0x60001000 0 0x1000>,
1752 <0 0x60100000 0 0x100000>;
1755 linux,pci-domain = <0>;
1756 bus-range = <0x00 0xff>;
1762 ranges = <0x01000000 0x0 0x00000000 0x0 0x60200000 0x0 0x100000>,
1763 <0x02000000 0x0 0x60300000 0x0 0x60300000 0x0 0x3d00000>;
1766 * MSIs for BDF (1:0.0) only works with Device ID 0x5980.
1769 msi-map = <0x0 &gic_its 0x5981 0x1>,
1770 <0x100 &gic_its 0x5980 0x1>;
1771 msi-map-mask = <0xff00>;
1775 interrupt-map-mask = <0 0 0 0x7>;
1776 interrupt-map = <0 0 0 1 &intc 0 0 0 149 IRQ_TYPE_LEVEL_HIGH>, /* int_a */
1777 <0 0 0 2 &intc 0 0 0 150 IRQ_TYPE_LEVEL_HIGH>, /* int_b */
1778 <0 0 0 3 &intc 0 0 0 151 IRQ_TYPE_LEVEL_HIGH>, /* int_c */
1779 <0 0 0 4 &intc 0 0 0 152 IRQ_TYPE_LEVEL_HIGH>; /* int_d */
1806 iommu-map = <0x0 &apps_smmu 0x1c00 0x1>,
1807 <0x100 &apps_smmu 0x1c01 0x1>;
1821 pinctrl-0 = <&pcie0_default_state>;
1828 reg = <0 0x01c06000 0 0x200>;
1847 reg = <0 0x01c06e00 0 0x200>, /* tx */
1848 <0 0x01c07000 0 0x200>, /* rx */
1849 <0 0x01c06200 0 0x200>, /* pcs */
1850 <0 0x01c06600 0 0x200>; /* pcs_pcie */
1854 #clock-cells = <0>;
1855 #phy-cells = <0>;
1862 reg = <0 0x01c08000 0 0x3000>,
1863 <0 0x40000000 0 0xf1d>,
1864 <0 0x40000f20 0 0xa8>,
1865 <0 0x40001000 0 0x1000>,
1866 <0 0x40100000 0 0x100000>;
1870 bus-range = <0x00 0xff>;
1876 ranges = <0x01000000 0x0 0x00000000 0x0 0x40200000 0x0 0x100000>,
1877 <0x02000000 0x0 0x40300000 0x0 0x40300000 0x0 0x1fd00000>;
1880 * MSIs for BDF (1:0.0) only works with Device ID 0x5a00.
1883 msi-map = <0x0 &gic_its 0x5a01 0x1>,
1884 <0x100 &gic_its 0x5a00 0x1>;
1885 msi-map-mask = <0xff00>;
1889 interrupt-map-mask = <0 0 0 0x7>;
1890 interrupt-map = <0 0 0 1 &intc 0 0 0 434 IRQ_TYPE_LEVEL_HIGH>, /* int_a */
1891 <0 0 0 2 &intc 0 0 0 435 IRQ_TYPE_LEVEL_HIGH>, /* int_b */
1892 <0 0 0 3 &intc 0 0 0 438 IRQ_TYPE_LEVEL_HIGH>, /* int_c */
1893 <0 0 0 4 &intc 0 0 0 439 IRQ_TYPE_LEVEL_HIGH>; /* int_d */
1918 iommu-map = <0x0 &apps_smmu 0x1c80 0x1>,
1919 <0x100 &apps_smmu 0x1c81 0x1>;
1933 pinctrl-0 = <&pcie1_default_state>;
1940 reg = <0 0x01c0f000 0 0x200>;
1959 reg = <0 0x01c0e000 0 0x200>, /* tx */
1960 <0 0x01c0e200 0 0x300>, /* rx */
1961 <0 0x01c0f200 0 0x200>, /* pcs */
1962 <0 0x01c0e800 0 0x200>, /* tx */
1963 <0 0x01c0ea00 0 0x300>, /* rx */
1964 <0 0x01c0f400 0 0xc00>; /* pcs_pcie */
1968 #clock-cells = <0>;
1969 #phy-cells = <0>;
1976 reg = <0 0x01500000 0 0x1c000>;
1983 reg = <0 0x01680000 0 0x1e200>;
1990 reg = <0 0x016c0000 0 0xe280>;
1997 reg = <0 0x016e0000 0 0x1c080>;
2006 reg = <0 0x01700000 0 0x31080>;
2017 reg = <0 0x01740000 0 0x1f080>;
2024 reg = <0x0 0x01f40000 0x0 0x40000>;
2030 reg = <0x0 0x1fc0000 0x0 0x30000>;
2036 reg = <0 0x088e3000 0 0x400>;
2038 #phy-cells = <0>;
2048 reg = <0 0x088e8000 0 0x3000>;
2067 #size-cells = <0>;
2069 port@0 {
2070 reg = <0>;
2094 reg = <0 0x02400000 0 0x4000>;
2097 <&smp2p_slpi_in 0 IRQ_TYPE_EDGE_RISING>,
2115 qcom,smem-states = <&smp2p_slpi_out 0>;
2135 #size-cells = <0>;
2140 iommus = <&apps_smmu 0x0541 0x0>;
2146 iommus = <&apps_smmu 0x0542 0x0>;
2152 iommus = <&apps_smmu 0x0543 0x0>;
2161 reg = <0 0x031e0000 0 0x1000>;
2172 #clock-cells = <0>;
2175 pinctrl-0 = <&wsa2_swr_active>;
2181 reg = <0 0x031f0000 0 0x2000>;
2190 qcom,ports-sinterval-low = /bits/ 8 <0x07 0x1f 0x3f 0x07 0x1f 0x3f 0x0f 0x0f>;
2191 qcom,ports-offset1 = /bits/ 8 <0x01 0x02 0x0c 0x06 0x12 0x0d 0x07 0x0a>;
2192 qcom,ports-offset2 = /bits/ 8 <0xff 0x00 0x1f 0xff 0x00 0x1f 0x00 0x00>;
2193 qcom,ports-hstart = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff>;
2194 qcom,ports-hstop = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff>;
2195 qcom,ports-word-length = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff>;
2196 qcom,ports-block-pack-mode = /bits/ 8 <0xff 0xff 0x01 0xff 0xff 0x01 0xff 0xff>;
2197 qcom,ports-block-group-count = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff>;
2198 qcom,ports-lane-control = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff>;
2201 #size-cells = <0>;
2208 reg = <0 0x03200000 0 0x1000>;
2220 #clock-cells = <0>;
2223 pinctrl-0 = <&rx_swr_active>;
2229 reg = <0 0x03210000 0 0x2000>;
2234 qcom,din-ports = <0>;
2237 qcom,ports-sinterval-low = /bits/ 8 <0x03 0x1f 0x1f 0x07 0x00>;
2238 qcom,ports-offset1 = /bits/ 8 <0x00 0x00 0x0b 0x01 0x00>;
2239 qcom,ports-offset2 = /bits/ 8 <0x00 0x00 0x0b 0x00 0x00>;
2240 qcom,ports-hstart = /bits/ 8 <0xff 0x03 0xff 0xff 0xff>;
2241 qcom,ports-hstop = /bits/ 8 <0xff 0x06 0xff 0xff 0xff>;
2242 qcom,ports-word-length = /bits/ 8 <0x01 0x07 0x04 0xff 0xff>;
2243 qcom,ports-block-pack-mode = /bits/ 8 <0xff 0x00 0x01 0xff 0xff>;
2244 qcom,ports-block-group-count = /bits/ 8 <0xff 0xff 0xff 0xff 0x00>;
2245 qcom,ports-lane-control = /bits/ 8 <0x01 0x00 0x00 0x00 0x00>;
2248 #size-cells = <0>;
2255 reg = <0 0x03220000 0 0x1000>;
2266 #clock-cells = <0>;
2269 pinctrl-0 = <&tx_swr_active>;
2275 reg = <0 0x03240000 0 0x1000>;
2287 #clock-cells = <0>;
2290 pinctrl-0 = <&wsa_swr_active>;
2296 reg = <0 0x03250000 0 0x2000>;
2305 qcom,ports-sinterval-low = /bits/ 8 <0x07 0x1f 0x3f 0x07 0x1f 0x3f 0x0f 0x0f>;
2306 qcom,ports-offset1 = /bits/ 8 <0x01 0x02 0x0c 0x06 0x12 0x0d 0x07 0x0a>;
2307 qcom,ports-offset2 = /bits/ 8 <0xff 0x00 0x1f 0xff 0x00 0x1f 0x00 0x00>;
2308 qcom,ports-hstart = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff>;
2309 qcom,ports-hstop = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff>;
2310 qcom,ports-word-length = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff>;
2311 qcom,ports-block-pack-mode = /bits/ 8 <0xff 0xff 0x01 0xff 0xff 0x01 0xff 0xff>;
2312 qcom,ports-block-group-count = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff>;
2313 qcom,ports-lane-control = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff>;
2316 #size-cells = <0>;
2323 reg = <0 0x033b0000 0 0x2000>;
2333 qcom,dout-ports = <0>;
2334 qcom,ports-sinterval-low = /bits/ 8 <0x01 0x01 0x03 0x03>;
2335 qcom,ports-offset1 = /bits/ 8 <0x00 0x00 0x01 0x01>;
2336 qcom,ports-offset2 = /bits/ 8 <0x00 0x00 0x00 0x00>;
2337 qcom,ports-hstart = /bits/ 8 <0xff 0xff 0xff 0xff>;
2338 qcom,ports-hstop = /bits/ 8 <0xff 0xff 0xff 0xff>;
2339 qcom,ports-word-length = /bits/ 8 <0xff 0xff 0xff 0xff>;
2340 qcom,ports-block-pack-mode = /bits/ 8 <0xff 0xff 0xff 0xff>;
2341 qcom,ports-block-group-count = /bits/ 8 <0xff 0xff 0xff 0xff>;
2342 qcom,ports-lane-control = /bits/ 8 <0x01 0x02 0x00 0x00>;
2345 #size-cells = <0>;
2352 reg = <0 0x033f0000 0 0x1000>;
2361 #clock-cells = <0>;
2369 reg = <0 0x30000000 0 0x100>;
2372 <&smp2p_adsp_in 0 IRQ_TYPE_EDGE_RISING>,
2390 qcom,smem-states = <&smp2p_adsp_out 0>;
2411 #size-cells = <0>;
2416 #sound-dai-cells = <0>;
2422 iommus = <&apps_smmu 0x1801 0x0>;
2449 #size-cells = <0>;
2454 iommus = <&apps_smmu 0x1803 0x0>;
2460 iommus = <&apps_smmu 0x1804 0x0>;
2466 iommus = <&apps_smmu 0x1805 0x0>;
2474 reg = <0 0x32300000 0 0x1400000>;
2477 <&smp2p_cdsp_in 0 IRQ_TYPE_EDGE_RISING>,
2495 qcom,smem-states = <&smp2p_cdsp_out 0>;
2515 #size-cells = <0>;
2520 iommus = <&apps_smmu 0x2161 0x0400>,
2521 <&apps_smmu 0x1021 0x1420>;
2527 iommus = <&apps_smmu 0x2162 0x0400>,
2528 <&apps_smmu 0x1022 0x1420>;
2534 iommus = <&apps_smmu 0x2163 0x0400>,
2535 <&apps_smmu 0x1023 0x1420>;
2541 iommus = <&apps_smmu 0x2164 0x0400>,
2542 <&apps_smmu 0x1024 0x1420>;
2548 iommus = <&apps_smmu 0x2165 0x0400>,
2549 <&apps_smmu 0x1025 0x1420>;
2555 iommus = <&apps_smmu 0x2166 0x0400>,
2556 <&apps_smmu 0x1026 0x1420>;
2562 iommus = <&apps_smmu 0x2167 0x0400>,
2563 <&apps_smmu 0x1027 0x1420>;
2569 iommus = <&apps_smmu 0x2168 0x0400>,
2570 <&apps_smmu 0x1028 0x1420>;
2580 reg = <0x0 0x04080000 0x0 0x4040>;
2583 <&smp2p_modem_in 0 IRQ_TYPE_EDGE_RISING>,
2602 qcom,smem-states = <&smp2p_modem_out 0>;
2620 reg = <0 0x0aaf0000 0 0x10000>;
2632 reg = <0 0x0ac15000 0 0x1000>;
2646 pinctrl-0 = <&cci0_default &cci1_default>;
2652 #size-cells = <0>;
2654 cci0_i2c0: i2c-bus@0 {
2655 reg = <0>;
2658 #size-cells = <0>;
2665 #size-cells = <0>;
2671 reg = <0 0x0ac16000 0 0x1000>;
2685 pinctrl-0 = <&cci2_default &cci3_default>;
2691 #size-cells = <0>;
2693 cci1_i2c0: i2c-bus@0 {
2694 reg = <0>;
2697 #size-cells = <0>;
2704 #size-cells = <0>;
2710 reg = <0 0x0ade0000 0 0x20000>;
2725 reg = <0 0x0ae00000 0 0x1000>;
2729 interconnects = <&mmss_noc MASTER_MDP_DISP 0 &mc_virt SLAVE_EBI1_DISP 0>,
2730 <&mmss_noc MASTER_MDP_DISP 0 &mc_virt SLAVE_EBI1_DISP 0>,
2750 iommus = <&apps_smmu 0x2800 0x402>;
2760 reg = <0 0x0ae01000 0 0x8f000>,
2761 <0 0x0aeb0000 0 0x2008>;
2784 interrupts = <0>;
2788 #size-cells = <0>;
2790 port@0 {
2791 reg = <0>;
2844 reg = <0 0xae90000 0 0x200>,
2845 <0 0xae90200 0 0x200>,
2846 <0 0xae90400 0 0xc00>,
2847 <0 0xae91000 0 0x400>,
2848 <0 0xae91400 0 0x400>;
2870 #sound-dai-cells = <0>;
2879 #size-cells = <0>;
2881 port@0 {
2882 reg = <0>;
2916 reg = <0 0x0ae94000 0 0x400>;
2936 assigned-clock-parents = <&mdss_dsi0_phy 0>, <&mdss_dsi0_phy 1>;
2945 #size-cells = <0>;
2951 #size-cells = <0>;
2953 port@0 {
2954 reg = <0>;
2989 reg = <0 0x0ae94400 0 0x200>,
2990 <0 0x0ae94600 0 0x280>,
2991 <0 0x0ae94900 0 0x260>;
2997 #phy-cells = <0>;
3008 reg = <0 0x0ae96000 0 0x400>;
3028 assigned-clock-parents = <&mdss_dsi1_phy 0>, <&mdss_dsi1_phy 1>;
3037 #size-cells = <0>;
3043 #size-cells = <0>;
3045 port@0 {
3046 reg = <0>;
3062 reg = <0 0x0ae96400 0 0x200>,
3063 <0 0x0ae96600 0 0x280>,
3064 <0 0x0ae96900 0 0x260>;
3070 #phy-cells = <0>;
3082 reg = <0 0x0af00000 0 0x20000>;
3087 <&mdss_dsi0_phy 0>,
3089 <&mdss_dsi1_phy 0>,
3093 <0>, /* dp1 */
3094 <0>,
3095 <0>, /* dp2 */
3096 <0>,
3097 <0>, /* dp3 */
3098 <0>;
3109 reg = <0 0x0b220000 0 0x30000>, <0 0x174000f0 0 0x64>;
3110 qcom,pdc-ranges = <0 480 12>, <14 494 24>, <40 520 54>,
3119 reg = <0 0x0c263000 0 0x1000>, /* TM */
3120 <0 0x0c222000 0 0x1000>; /* SROT */
3130 reg = <0 0x0c265000 0 0x1000>, /* TM */
3131 <0 0x0c223000 0 0x1000>; /* SROT */
3141 reg = <0 0x0c300000 0 0x400>;
3146 #clock-cells = <0>;
3151 reg = <0 0x0c3f0000 0 0x400>;
3156 reg = <0 0x0c400000 0 0x00003000>,
3157 <0 0x0c500000 0 0x00400000>,
3158 <0 0x0c440000 0 0x00080000>,
3159 <0 0x0c4c0000 0 0x00010000>,
3160 <0 0x0c42d000 0 0x00010000>;
3168 qcom,ee = <0>;
3169 qcom,channel = <0>;
3173 #size-cells = <0>;
3178 reg = <0 0x0ed18000 0 0x1000>;
3187 reg = <0 0x0f100000 0 0x300000>;
3193 gpio-ranges = <&tlmm 0 0 211>;
3697 reg = <0 0x03440000 0x0 0x20000>,
3698 <0 0x034d0000 0x0 0x10000>;
3701 gpio-ranges = <&lpass_tlmm 0 0 23>;
3812 reg = <0 0x146aa000 0 0x1000>;
3813 ranges = <0 0 0x146aa000 0x1000>;
3820 reg = <0x94c 0xc8>;
3826 reg = <0 0x15000000 0 0x100000>;
3933 redistributor-stride = <0x0 0x40000>;
3934 reg = <0x0 0x17100000 0x0 0x10000>, /* GICD */
3935 <0x0 0x17180000 0x0 0x200000>; /* GICR * 8 */
3943 reg = <0x0 0x17140000 0x0 0x20000>;
3953 ranges = <0 0 0 0x20000000>;
3954 reg = <0x0 0x17420000 0x0 0x1000>;
3958 frame-number = <0>;
3961 reg = <0x17421000 0x1000>,
3962 <0x17422000 0x1000>;
3968 reg = <0x17423000 0x1000>;
3975 reg = <0x17425000 0x1000>;
3982 reg = <0x17427000 0x1000>;
3989 reg = <0x17429000 0x1000>;
3996 reg = <0x1742b000 0x1000>;
4003 reg = <0x1742d000 0x1000>;
4011 reg = <0x0 0x17a00000 0x0 0x10000>,
4012 <0x0 0x17a10000 0x0 0x10000>,
4013 <0x0 0x17a20000 0x0 0x10000>,
4014 <0x0 0x17a30000 0x0 0x10000>;
4015 reg-names = "drv-0", "drv-1", "drv-2", "drv-3";
4019 qcom,tcs-offset = <0xd00>;
4022 <WAKE_TCS 2>, <CONTROL_TCS 0>;
4105 reg = <0 0x17d91000 0 0x1000>,
4106 <0 0x17d92000 0 0x1000>,
4107 <0 0x17d93000 0 0x1000>;
4114 interrupt-names = "dcvsh-irq-0", "dcvsh-irq-1", "dcvsh-irq-2";
4121 reg = <0 0x19100000 0 0xbb800>;
4128 reg = <0 0x19200000 0 0x80000>, <0 0x19600000 0 0x80000>,
4129 <0 0x19300000 0 0x80000>, <0 0x19700000 0 0x80000>,
4130 <0 0x19a00000 0 0x80000>;
4139 reg = <0 0x01d84000 0 0x3000>;
4150 iommus = <&apps_smmu 0xe0 0x0>;
4153 interconnects = <&aggre1_noc MASTER_UFS_MEM 0 &mc_virt SLAVE_EBI1 0>,
4154 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_UFS_MEM_CFG 0>;
4176 <0 0>,
4177 <0 0>,
4180 <0 0>,
4181 <0 0>,
4182 <0 0>;
4190 reg = <0 0x01d87000 0 0x1c4>;
4199 resets = <&ufs_mem_hc 0>;
4204 reg = <0 0x01d87400 0 0x188>,
4205 <0 0x01d87600 0 0x200>,
4206 <0 0x01d87c00 0 0x200>,
4207 <0 0x01d87800 0 0x188>,
4208 <0 0x01d87a00 0 0x200>;
4210 #phy-cells = <0>;
4217 reg = <0 0x01d88000 0 0x8000>;
4223 reg = <0 0x01dc4000 0 0x28000>;
4226 qcom,ee = <0>;
4228 iommus = <&apps_smmu 0x584 0x11>,
4229 <&apps_smmu 0x588 0x0>,
4230 <&apps_smmu 0x598 0x5>,
4231 <&apps_smmu 0x59a 0x0>,
4232 <&apps_smmu 0x59f 0x0>;
4237 reg = <0 0x01dfa000 0 0x6000>;
4240 iommus = <&apps_smmu 0x584 0x11>,
4241 <&apps_smmu 0x588 0x0>,
4242 <&apps_smmu 0x598 0x5>,
4243 <&apps_smmu 0x59a 0x0>,
4244 <&apps_smmu 0x59f 0x0>;
4245 interconnects = <&aggre2_noc MASTER_CRYPTO 0 &mc_virt SLAVE_EBI1 0>;
4251 reg = <0 0x08804000 0 0x1000>;
4262 interconnects = <&aggre2_noc MASTER_SDCC_2 0 &mc_virt SLAVE_EBI1 0>,
4263 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_SDCC_2 0>;
4265 iommus = <&apps_smmu 0x4a0 0x0>;
4272 sdhci-caps-mask = <0x3 0x0>;
4293 reg = <0 0x0a6f8800 0 0x400>;
4329 interconnects = <&aggre1_noc MASTER_USB3_0 0 &mc_virt SLAVE_EBI1 0>,
4330 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_USB3_0 0>;
4335 reg = <0 0x0a600000 0 0xcd00>;
4337 iommus = <&apps_smmu 0x0 0x0>;
4345 #size-cells = <0>;
4347 port@0 {
4348 reg = <0>;
4366 reg = <0 0x320c0000 0 0x10000>;
4373 reg = <0 0x03c40000 0 0x17200>;
4384 polling-delay-passive = <0>;
4385 polling-delay = <0>;
4386 thermal-sensors = <&tsens0 0>;
4404 polling-delay-passive = <0>;
4405 polling-delay = <0>;
4424 polling-delay-passive = <0>;
4425 polling-delay = <0>;
4444 polling-delay-passive = <0>;
4445 polling-delay = <0>;
4464 polling-delay-passive = <0>;
4465 polling-delay = <0>;
4484 polling-delay-passive = <0>;
4485 polling-delay = <0>;
4510 polling-delay-passive = <0>;
4511 polling-delay = <0>;
4536 polling-delay-passive = <0>;
4537 polling-delay = <0>;
4562 polling-delay-passive = <0>;
4563 polling-delay = <0>;
4588 polling-delay-passive = <0>;
4589 polling-delay = <0>;
4614 polling-delay-passive = <0>;
4615 polling-delay = <0>;
4640 polling-delay-passive = <0>;
4641 polling-delay = <0>;
4666 polling-delay-passive = <0>;
4667 polling-delay = <0>;
4692 polling-delay-passive = <0>;
4693 polling-delay = <0>;
4719 polling-delay = <0>;
4751 polling-delay = <0>;
4782 polling-delay-passive = <0>;
4783 polling-delay = <0>;
4784 thermal-sensors = <&tsens1 0>;
4802 polling-delay-passive = <0>;
4803 polling-delay = <0>;
4828 polling-delay-passive = <0>;
4829 polling-delay = <0>;
4854 polling-delay-passive = <0>;
4855 polling-delay = <0>;
4880 polling-delay-passive = <0>;
4881 polling-delay = <0>;
4907 polling-delay = <0>;
4939 polling-delay = <0>;
4971 polling-delay = <0>;
5002 polling-delay-passive = <0>;
5003 polling-delay = <0>;
5023 polling-delay = <0>;
5048 polling-delay-passive = <0>;
5049 polling-delay = <0>;
5080 polling-delay-passive = <0>;
5081 polling-delay = <0>;
5112 polling-delay-passive = <0>;
5113 polling-delay = <0>;
5144 polling-delay-passive = <0>;
5145 polling-delay = <0>;
5176 polling-delay-passive = <0>;
5177 polling-delay = <0>;
5196 polling-delay-passive = <0>;
5197 polling-delay = <0>;