3 // mt8186-afe-clk.c  --  Mediatek 8186 afe clock ctrl
12 #include "mt8186-afe-common.h"
13 #include "mt8186-afe-clk.h"
75 int mt8186_set_audio_int_bus_parent(struct mtk_base_afe *afe,  in mt8186_set_audio_int_bus_parent()  argument
78 	struct mt8186_afe_private *afe_priv = afe->platform_priv;  in mt8186_set_audio_int_bus_parent()
84 		dev_err(afe->dev, "%s clk_set_parent %s-%s fail %d\n",  in mt8186_set_audio_int_bus_parent()
93 static int apll1_mux_setting(struct mtk_base_afe *afe, bool enable)  in apll1_mux_setting()  argument
95 	struct mt8186_afe_private *afe_priv = afe->platform_priv;  in apll1_mux_setting()
101 			dev_err(afe->dev, "%s clk_prepare_enable %s fail %d\n",  in apll1_mux_setting()
108 			dev_err(afe->dev, "%s clk_set_parent %s-%s fail %d\n",  in apll1_mux_setting()
117 			dev_err(afe->dev, "%s clk_prepare_enable %s fail %d\n",  in apll1_mux_setting()
124 			dev_err(afe->dev, "%s clk_set_parent %s-%s fail %d\n",  in apll1_mux_setting()
133 			dev_err(afe->dev, "%s clk_set_parent %s-%s fail %d\n",  in apll1_mux_setting()
143 			dev_err(afe->dev, "%s clk_set_parent %s-%s fail %d\n",  in apll1_mux_setting()
154 static int apll2_mux_setting(struct mtk_base_afe *afe, bool enable)  in apll2_mux_setting()  argument
156 	struct mt8186_afe_private *afe_priv = afe->platform_priv;  in apll2_mux_setting()
162 			dev_err(afe->dev, "%s clk_prepare_enable %s fail %d\n",  in apll2_mux_setting()
169 			dev_err(afe->dev, "%s clk_set_parent %s-%s fail %d\n",  in apll2_mux_setting()
178 			dev_err(afe->dev, "%s clk_prepare_enable %s fail %d\n",  in apll2_mux_setting()
185 			dev_err(afe->dev, "%s clk_set_parent %s-%s fail %d\n",  in apll2_mux_setting()
194 			dev_err(afe->dev, "%s clk_set_parent %s-%s fail %d\n",  in apll2_mux_setting()
204 			dev_err(afe->dev, "%s clk_set_parent %s-%s fail %d\n",  in apll2_mux_setting()
215 int mt8186_afe_enable_cgs(struct mtk_base_afe *afe)  in mt8186_afe_enable_cgs()  argument
217 	struct mt8186_afe_private *afe_priv = afe->platform_priv;  in mt8186_afe_enable_cgs()
224 			dev_err(afe->dev, "%s clk_prepare_enable %s fail %d\n",  in mt8186_afe_enable_cgs()
233 void mt8186_afe_disable_cgs(struct mtk_base_afe *afe)  in mt8186_afe_disable_cgs()  argument
235 	struct mt8186_afe_private *afe_priv = afe->platform_priv;  in mt8186_afe_disable_cgs()
242 int mt8186_afe_enable_clock(struct mtk_base_afe *afe)  in mt8186_afe_enable_clock()  argument
244 	struct mt8186_afe_private *afe_priv = afe->platform_priv;  in mt8186_afe_enable_clock()
249 		dev_err(afe->dev, "%s clk_prepare_enable %s fail %d\n",  in mt8186_afe_enable_clock()
256 		dev_err(afe->dev, "%s clk_prepare_enable %s fail %d\n",  in mt8186_afe_enable_clock()
263 		dev_err(afe->dev, "%s clk_prepare_enable %s fail %d\n",  in mt8186_afe_enable_clock()
270 		dev_err(afe->dev, "%s clk_set_parent %s-%s fail %d\n",  in mt8186_afe_enable_clock()
278 		dev_err(afe->dev, "%s clk_prepare_enable %s fail %d\n",  in mt8186_afe_enable_clock()
282 	ret = mt8186_set_audio_int_bus_parent(afe,  in mt8186_afe_enable_clock()
290 		dev_err(afe->dev, "%s clk_set_parent %s-%s fail %d\n",  in mt8186_afe_enable_clock()
298 		dev_err(afe->dev, "%s clk_prepare_enable %s fail %d\n",  in mt8186_afe_enable_clock()
309 	mt8186_set_audio_int_bus_parent(afe, CLK_CLK26M);  in mt8186_afe_enable_clock()
322 void mt8186_afe_disable_clock(struct mtk_base_afe *afe)  in mt8186_afe_disable_clock()  argument
324 	struct mt8186_afe_private *afe_priv = afe->platform_priv;  in mt8186_afe_disable_clock()
327 	mt8186_set_audio_int_bus_parent(afe, CLK_CLK26M);  in mt8186_afe_disable_clock()
334 int mt8186_afe_suspend_clock(struct mtk_base_afe *afe)  in mt8186_afe_suspend_clock()  argument
336 	struct mt8186_afe_private *afe_priv = afe->platform_priv;  in mt8186_afe_suspend_clock()
342 		dev_info(afe->dev, "%s clk_prepare_enable %s fail %d\n",  in mt8186_afe_suspend_clock()
346 	ret = mt8186_set_audio_int_bus_parent(afe, CLK_CLK26M);  in mt8186_afe_suspend_clock()
355 	mt8186_set_audio_int_bus_parent(afe, CLK_TOP_MAINPLL_D2_D4);  in mt8186_afe_suspend_clock()
361 int mt8186_afe_resume_clock(struct mtk_base_afe *afe)  in mt8186_afe_resume_clock()  argument
363 	struct mt8186_afe_private *afe_priv = afe->platform_priv;  in mt8186_afe_resume_clock()
369 		dev_info(afe->dev, "%s clk_prepare_enable %s fail %d\n",  in mt8186_afe_resume_clock()
373 	ret = mt8186_set_audio_int_bus_parent(afe,  in mt8186_afe_resume_clock()
383 	mt8186_set_audio_int_bus_parent(afe, CLK_CLK26M);  in mt8186_afe_resume_clock()
389 int mt8186_apll1_enable(struct mtk_base_afe *afe)  in mt8186_apll1_enable()  argument
391 	struct mt8186_afe_private *afe_priv = afe->platform_priv;  in mt8186_apll1_enable()
395 	apll1_mux_setting(afe, true);  in mt8186_apll1_enable()
399 		dev_err(afe->dev, "%s clk_prepare_enable %s fail %d\n",  in mt8186_apll1_enable()
406 		dev_err(afe->dev, "%s clk_prepare_enable %s fail %d\n",  in mt8186_apll1_enable()
411 	regmap_update_bits(afe->regmap, AFE_APLL1_TUNER_CFG, 0xfff7, 0x832);  in mt8186_apll1_enable()
412 	regmap_update_bits(afe->regmap, AFE_APLL1_TUNER_CFG, 0x1, 0x1);  in mt8186_apll1_enable()
414 	regmap_update_bits(afe->regmap, AFE_HD_ENGEN_ENABLE,  in mt8186_apll1_enable()
427 void mt8186_apll1_disable(struct mtk_base_afe *afe)  in mt8186_apll1_disable()  argument
429 	struct mt8186_afe_private *afe_priv = afe->platform_priv;  in mt8186_apll1_disable()
431 	regmap_update_bits(afe->regmap, AFE_HD_ENGEN_ENABLE,  in mt8186_apll1_disable()
434 	regmap_update_bits(afe->regmap, AFE_APLL1_TUNER_CFG, 0x1, 0);  in mt8186_apll1_disable()
439 	apll1_mux_setting(afe, false);  in mt8186_apll1_disable()
442 int mt8186_apll2_enable(struct mtk_base_afe *afe)  in mt8186_apll2_enable()  argument
444 	struct mt8186_afe_private *afe_priv = afe->platform_priv;  in mt8186_apll2_enable()
448 	apll2_mux_setting(afe, true);  in mt8186_apll2_enable()
452 		dev_err(afe->dev, "%s clk_prepare_enable %s fail %d\n",  in mt8186_apll2_enable()
459 		dev_err(afe->dev, "%s clk_prepare_enable %s fail %d\n",  in mt8186_apll2_enable()
464 	regmap_update_bits(afe->regmap, AFE_APLL2_TUNER_CFG, 0xfff7, 0x634);  in mt8186_apll2_enable()
465 	regmap_update_bits(afe->regmap, AFE_APLL2_TUNER_CFG, 0x1, 0x1);  in mt8186_apll2_enable()
467 	regmap_update_bits(afe->regmap, AFE_HD_ENGEN_ENABLE,  in mt8186_apll2_enable()
480 void mt8186_apll2_disable(struct mtk_base_afe *afe)  in mt8186_apll2_disable()  argument
482 	struct mt8186_afe_private *afe_priv = afe->platform_priv;  in mt8186_apll2_disable()
484 	regmap_update_bits(afe->regmap, AFE_HD_ENGEN_ENABLE,  in mt8186_apll2_disable()
487 	regmap_update_bits(afe->regmap, AFE_APLL2_TUNER_CFG, 0x1, 0);  in mt8186_apll2_disable()
492 	apll2_mux_setting(afe, false);  in mt8186_apll2_disable()
495 int mt8186_get_apll_rate(struct mtk_base_afe *afe, int apll)  in mt8186_get_apll_rate()  argument
500 int mt8186_get_apll_by_rate(struct mtk_base_afe *afe, int rate)  in mt8186_get_apll_by_rate()  argument
505 int mt8186_get_apll_by_name(struct mtk_base_afe *afe, const char *name)  in mt8186_get_apll_by_name()  argument
542 int mt8186_mck_enable(struct mtk_base_afe *afe, int mck_id, int rate)  in mt8186_mck_enable()  argument
544 	struct mt8186_afe_private *afe_priv = afe->platform_priv;  in mt8186_mck_enable()
545 	int apll = mt8186_get_apll_by_rate(afe, rate);  in mt8186_mck_enable()
556 			dev_err(afe->dev, "%s(), clk_prepare_enable %s fail %d\n",  in mt8186_mck_enable()
563 			dev_err(afe->dev, "%s(), clk_set_parent %s-%s fail %d\n",  in mt8186_mck_enable()
573 		dev_err(afe->dev, "%s(), clk_prepare_enable %s fail %d\n",  in mt8186_mck_enable()
579 		dev_err(afe->dev, "%s(), clk_set_rate %s, rate %d, fail %d\n",  in mt8186_mck_enable()
587 void mt8186_mck_disable(struct mtk_base_afe *afe, int mck_id)  in mt8186_mck_disable()  argument
589 	struct mt8186_afe_private *afe_priv = afe->platform_priv;  in mt8186_mck_disable()
598 int mt8186_init_clock(struct mtk_base_afe *afe)  in mt8186_init_clock()  argument
600 	struct mt8186_afe_private *afe_priv = afe->platform_priv;  in mt8186_init_clock()
601 	struct device_node *of_node = afe->dev->of_node;  in mt8186_init_clock()
604 	mt8186_audsys_clk_register(afe);  in mt8186_init_clock()
606 	afe_priv->clk = devm_kcalloc(afe->dev, CLK_NUM, sizeof(*afe_priv->clk),  in mt8186_init_clock()
612 		afe_priv->clk[i] = devm_clk_get(afe->dev, aud_clks[i]);  in mt8186_init_clock()
614 			dev_err(afe->dev, "%s devm_clk_get %s fail, ret %ld\n",  in mt8186_init_clock()
624 		dev_err(afe->dev, "%s() Cannot find apmixedsys controller: %ld\n",  in mt8186_init_clock()
632 		dev_err(afe->dev, "%s() Cannot find topckgen controller: %ld\n",  in mt8186_init_clock()
640 		dev_err(afe->dev, "%s() Cannot find infracfg: %ld\n",  in mt8186_init_clock()
650 	struct mtk_base_afe *afe = priv;  in mt8186_deinit_clock()  local
651 	mt8186_audsys_clk_unregister(afe);  in mt8186_deinit_clock()