Lines Matching +full:serial +full:- +full:clk +full:- +full:low
1 // SPDX-License-Identifier: GPL-2.0
9 * Inspired by st-asc.c from STMicroelectronics (c)
12 #include <linux/clk.h>
15 #include <linux/dma-direction.h>
17 #include <linux/dma-mapping.h>
29 #include <linux/serial.h>
36 #include "stm32-usart.h"
120 val = readl_relaxed(port->membase + reg); in stm32_usart_set_bits()
122 writel_relaxed(val, port->membase + reg); in stm32_usart_set_bits()
129 val = readl_relaxed(port->membase + reg); in stm32_usart_clr_bits()
131 writel_relaxed(val, port->membase + reg); in stm32_usart_clr_bits()
137 const struct stm32_usart_offsets *ofs = &stm32_port->info->ofs; in stm32_usart_tx_empty()
139 if (readl_relaxed(port->membase + ofs->isr) & USART_SR_TC) in stm32_usart_tx_empty()
148 struct serial_rs485 *rs485conf = &port->rs485; in stm32_usart_rs485_rts_enable()
150 if (stm32_port->hw_flow_control || in stm32_usart_rs485_rts_enable()
151 !(rs485conf->flags & SER_RS485_ENABLED)) in stm32_usart_rs485_rts_enable()
154 if (rs485conf->flags & SER_RS485_RTS_ON_SEND) { in stm32_usart_rs485_rts_enable()
155 mctrl_gpio_set(stm32_port->gpios, in stm32_usart_rs485_rts_enable()
156 stm32_port->port.mctrl | TIOCM_RTS); in stm32_usart_rs485_rts_enable()
158 mctrl_gpio_set(stm32_port->gpios, in stm32_usart_rs485_rts_enable()
159 stm32_port->port.mctrl & ~TIOCM_RTS); in stm32_usart_rs485_rts_enable()
166 struct serial_rs485 *rs485conf = &port->rs485; in stm32_usart_rs485_rts_disable()
168 if (stm32_port->hw_flow_control || in stm32_usart_rs485_rts_disable()
169 !(rs485conf->flags & SER_RS485_ENABLED)) in stm32_usart_rs485_rts_disable()
172 if (rs485conf->flags & SER_RS485_RTS_ON_SEND) { in stm32_usart_rs485_rts_disable()
173 mctrl_gpio_set(stm32_port->gpios, in stm32_usart_rs485_rts_disable()
174 stm32_port->port.mctrl & ~TIOCM_RTS); in stm32_usart_rs485_rts_disable()
176 mctrl_gpio_set(stm32_port->gpios, in stm32_usart_rs485_rts_disable()
177 stm32_port->port.mctrl | TIOCM_RTS); in stm32_usart_rs485_rts_disable()
222 const struct stm32_usart_offsets *ofs = &stm32_port->info->ofs; in stm32_usart_config_rs485()
223 const struct stm32_usart_config *cfg = &stm32_port->info->cfg; in stm32_usart_config_rs485()
227 stm32_usart_clr_bits(port, ofs->cr1, BIT(cfg->uart_enable_bit)); in stm32_usart_config_rs485()
229 rs485conf->flags |= SER_RS485_RX_DURING_TX; in stm32_usart_config_rs485()
231 if (rs485conf->flags & SER_RS485_ENABLED) { in stm32_usart_config_rs485()
232 cr1 = readl_relaxed(port->membase + ofs->cr1); in stm32_usart_config_rs485()
233 cr3 = readl_relaxed(port->membase + ofs->cr3); in stm32_usart_config_rs485()
234 usartdiv = readl_relaxed(port->membase + ofs->brr); in stm32_usart_config_rs485()
242 baud = DIV_ROUND_CLOSEST(port->uartclk, usartdiv); in stm32_usart_config_rs485()
244 rs485conf->delay_rts_before_send, in stm32_usart_config_rs485()
245 rs485conf->delay_rts_after_send, in stm32_usart_config_rs485()
248 if (rs485conf->flags & SER_RS485_RTS_ON_SEND) in stm32_usart_config_rs485()
253 writel_relaxed(cr3, port->membase + ofs->cr3); in stm32_usart_config_rs485()
254 writel_relaxed(cr1, port->membase + ofs->cr1); in stm32_usart_config_rs485()
256 stm32_usart_clr_bits(port, ofs->cr3, in stm32_usart_config_rs485()
258 stm32_usart_clr_bits(port, ofs->cr1, in stm32_usart_config_rs485()
262 stm32_usart_set_bits(port, ofs->cr1, BIT(cfg->uart_enable_bit)); in stm32_usart_config_rs485()
276 struct serial_rs485 *rs485conf = &port->rs485; in stm32_usart_init_rs485()
278 rs485conf->flags = 0; in stm32_usart_init_rs485()
279 rs485conf->delay_rts_before_send = 0; in stm32_usart_init_rs485()
280 rs485conf->delay_rts_after_send = 0; in stm32_usart_init_rs485()
282 if (!pdev->dev.of_node) in stm32_usart_init_rs485()
283 return -ENODEV; in stm32_usart_init_rs485()
291 const struct stm32_usart_offsets *ofs = &stm32_port->info->ofs; in stm32_usart_rx_dma_enabled()
293 if (!stm32_port->rx_ch) in stm32_usart_rx_dma_enabled()
296 return !!(readl_relaxed(port->membase + ofs->cr3) & USART_CR3_DMAR); in stm32_usart_rx_dma_enabled()
303 const struct stm32_usart_offsets *ofs = &stm32_port->info->ofs; in stm32_usart_pending_rx_pio()
305 *sr = readl_relaxed(port->membase + ofs->isr); in stm32_usart_pending_rx_pio()
323 const struct stm32_usart_offsets *ofs = &stm32_port->info->ofs; in stm32_usart_get_char_pio()
326 c = readl_relaxed(port->membase + ofs->rdr); in stm32_usart_get_char_pio()
328 c &= stm32_port->rdr_mask; in stm32_usart_get_char_pio()
336 const struct stm32_usart_offsets *ofs = &stm32_port->info->ofs; in stm32_usart_receive_chars_pio()
355 * cleared by the sequence [read SR - read DR]. in stm32_usart_receive_chars_pio()
357 if ((sr & USART_SR_ERR_MASK) && ofs->icr != UNDEF_REG) in stm32_usart_receive_chars_pio()
359 port->membase + ofs->icr); in stm32_usart_receive_chars_pio()
362 port->icount.rx++; in stm32_usart_receive_chars_pio()
366 port->icount.overrun++; in stm32_usart_receive_chars_pio()
368 port->icount.parity++; in stm32_usart_receive_chars_pio()
372 port->icount.brk++; in stm32_usart_receive_chars_pio()
376 port->icount.frame++; in stm32_usart_receive_chars_pio()
380 sr &= port->read_status_mask; in stm32_usart_receive_chars_pio()
403 struct tty_port *ttyport = &stm32_port->port.state->port; in stm32_usart_push_buffer_dma()
407 dma_start = stm32_port->rx_buf + (RX_BUF_L - stm32_port->last_res); in stm32_usart_push_buffer_dma()
414 if (!(stm32_port->rdr_mask == (BIT(8) - 1))) in stm32_usart_push_buffer_dma()
416 *(dma_start + i) &= stm32_port->rdr_mask; in stm32_usart_push_buffer_dma()
419 port->icount.rx += dma_count; in stm32_usart_push_buffer_dma()
421 port->icount.buf_overrun++; in stm32_usart_push_buffer_dma()
422 stm32_port->last_res -= dma_count; in stm32_usart_push_buffer_dma()
423 if (stm32_port->last_res == 0) in stm32_usart_push_buffer_dma()
424 stm32_port->last_res = RX_BUF_L; in stm32_usart_push_buffer_dma()
433 if (stm32_port->rx_dma_state.residue > stm32_port->last_res) { in stm32_usart_receive_chars_dma()
435 dma_size = stm32_port->last_res; in stm32_usart_receive_chars_dma()
440 dma_size = stm32_port->last_res - stm32_port->rx_dma_state.residue; in stm32_usart_receive_chars_dma()
450 const struct stm32_usart_offsets *ofs = &stm32_port->info->ofs; in stm32_usart_receive_chars()
456 rx_dma_status = dmaengine_tx_status(stm32_port->rx_ch, in stm32_usart_receive_chars()
457 stm32_port->rx_ch->cookie, in stm32_usart_receive_chars()
458 &stm32_port->rx_dma_state); in stm32_usart_receive_chars()
462 sr = readl_relaxed(port->membase + ofs->isr); in stm32_usart_receive_chars()
465 stm32_usart_clr_bits(port, ofs->cr3, USART_CR3_DMAR); in stm32_usart_receive_chars()
471 stm32_usart_set_bits(port, ofs->cr3, USART_CR3_DMAR); in stm32_usart_receive_chars()
475 dmaengine_terminate_async(stm32_port->rx_ch); in stm32_usart_receive_chars()
476 stm32_usart_clr_bits(port, ofs->cr3, USART_CR3_DMAR); in stm32_usart_receive_chars()
478 dev_dbg(port->dev, "DMA error, fallback to irq mode\n"); in stm32_usart_receive_chars()
490 dmaengine_terminate_async(stm32_port->tx_ch); in stm32_usart_tx_dma_terminate()
491 stm32_port->tx_dma_busy = false; in stm32_usart_tx_dma_terminate()
503 return stm32_port->tx_dma_busy; in stm32_usart_tx_dma_started()
508 const struct stm32_usart_offsets *ofs = &stm32_port->info->ofs; in stm32_usart_tx_dma_enabled()
510 return !!(readl_relaxed(stm32_port->port.membase + ofs->cr3) & USART_CR3_DMAT); in stm32_usart_tx_dma_enabled()
517 const struct stm32_usart_offsets *ofs = &stm32port->info->ofs; in stm32_usart_tx_dma_complete()
520 stm32_usart_clr_bits(port, ofs->cr3, USART_CR3_DMAT); in stm32_usart_tx_dma_complete()
524 spin_lock_irqsave(&port->lock, flags); in stm32_usart_tx_dma_complete()
526 spin_unlock_irqrestore(&port->lock, flags); in stm32_usart_tx_dma_complete()
532 const struct stm32_usart_offsets *ofs = &stm32_port->info->ofs; in stm32_usart_tx_interrupt_enable()
538 if (stm32_port->fifoen && stm32_port->txftcfg >= 0) in stm32_usart_tx_interrupt_enable()
539 stm32_usart_set_bits(port, ofs->cr3, USART_CR3_TXFTIE); in stm32_usart_tx_interrupt_enable()
541 stm32_usart_set_bits(port, ofs->cr1, USART_CR1_TXEIE); in stm32_usart_tx_interrupt_enable()
547 const struct stm32_usart_offsets *ofs = &stm32_port->info->ofs; in stm32_usart_tc_interrupt_enable()
549 stm32_usart_set_bits(port, ofs->cr1, USART_CR1_TCIE); in stm32_usart_tc_interrupt_enable()
555 struct tty_port *tport = &port->state->port; in stm32_usart_rx_dma_complete()
559 spin_lock_irqsave(&port->lock, flags); in stm32_usart_rx_dma_complete()
569 const struct stm32_usart_offsets *ofs = &stm32_port->info->ofs; in stm32_usart_tx_interrupt_disable()
571 if (stm32_port->fifoen && stm32_port->txftcfg >= 0) in stm32_usart_tx_interrupt_disable()
572 stm32_usart_clr_bits(port, ofs->cr3, USART_CR3_TXFTIE); in stm32_usart_tx_interrupt_disable()
574 stm32_usart_clr_bits(port, ofs->cr1, USART_CR1_TXEIE); in stm32_usart_tx_interrupt_disable()
580 const struct stm32_usart_offsets *ofs = &stm32_port->info->ofs; in stm32_usart_tc_interrupt_disable()
582 stm32_usart_clr_bits(port, ofs->cr1, USART_CR1_TCIE); in stm32_usart_tc_interrupt_disable()
588 const struct stm32_usart_offsets *ofs = &stm32_port->info->ofs; in stm32_usart_transmit_chars_pio()
589 struct circ_buf *xmit = &port->state->xmit; in stm32_usart_transmit_chars_pio()
592 stm32_usart_clr_bits(port, ofs->cr3, USART_CR3_DMAT); in stm32_usart_transmit_chars_pio()
596 if (!(readl_relaxed(port->membase + ofs->isr) & USART_SR_TXE)) in stm32_usart_transmit_chars_pio()
598 writel_relaxed(xmit->buf[xmit->tail], port->membase + ofs->tdr); in stm32_usart_transmit_chars_pio()
599 xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1); in stm32_usart_transmit_chars_pio()
600 port->icount.tx++; in stm32_usart_transmit_chars_pio()
613 const struct stm32_usart_offsets *ofs = &stm32port->info->ofs; in stm32_usart_transmit_chars_dma()
614 struct circ_buf *xmit = &port->state->xmit; in stm32_usart_transmit_chars_dma()
620 stm32_usart_set_bits(port, ofs->cr3, USART_CR3_DMAT); in stm32_usart_transmit_chars_dma()
629 if (xmit->tail < xmit->head) { in stm32_usart_transmit_chars_dma()
630 memcpy(&stm32port->tx_buf[0], &xmit->buf[xmit->tail], count); in stm32_usart_transmit_chars_dma()
632 size_t one = UART_XMIT_SIZE - xmit->tail; in stm32_usart_transmit_chars_dma()
637 two = count - one; in stm32_usart_transmit_chars_dma()
639 memcpy(&stm32port->tx_buf[0], &xmit->buf[xmit->tail], one); in stm32_usart_transmit_chars_dma()
641 memcpy(&stm32port->tx_buf[one], &xmit->buf[0], two); in stm32_usart_transmit_chars_dma()
644 desc = dmaengine_prep_slave_single(stm32port->tx_ch, in stm32_usart_transmit_chars_dma()
645 stm32port->tx_dma_buf, in stm32_usart_transmit_chars_dma()
659 stm32port->tx_dma_busy = true; in stm32_usart_transmit_chars_dma()
661 desc->callback = stm32_usart_tx_dma_complete; in stm32_usart_transmit_chars_dma()
662 desc->callback_param = port; in stm32_usart_transmit_chars_dma()
672 dma_async_issue_pending(stm32port->tx_ch); in stm32_usart_transmit_chars_dma()
674 stm32_usart_set_bits(port, ofs->cr3, USART_CR3_DMAT); in stm32_usart_transmit_chars_dma()
676 xmit->tail = (xmit->tail + count) & (UART_XMIT_SIZE - 1); in stm32_usart_transmit_chars_dma()
677 port->icount.tx += count; in stm32_usart_transmit_chars_dma()
687 const struct stm32_usart_offsets *ofs = &stm32_port->info->ofs; in stm32_usart_transmit_chars()
688 struct circ_buf *xmit = &port->state->xmit; in stm32_usart_transmit_chars()
692 if (!stm32_port->hw_flow_control && in stm32_usart_transmit_chars()
693 port->rs485.flags & SER_RS485_ENABLED) { in stm32_usart_transmit_chars()
694 stm32_port->txdone = false; in stm32_usart_transmit_chars()
699 if (port->x_char) { in stm32_usart_transmit_chars()
702 stm32_usart_clr_bits(port, ofs->cr3, USART_CR3_DMAT); in stm32_usart_transmit_chars()
706 readl_relaxed_poll_timeout_atomic(port->membase + ofs->isr, in stm32_usart_transmit_chars()
711 dev_warn(port->dev, "1 character may be erased\n"); in stm32_usart_transmit_chars()
713 writel_relaxed(port->x_char, port->membase + ofs->tdr); in stm32_usart_transmit_chars()
714 port->x_char = 0; in stm32_usart_transmit_chars()
715 port->icount.tx++; in stm32_usart_transmit_chars()
717 stm32_usart_set_bits(port, ofs->cr3, USART_CR3_DMAT); in stm32_usart_transmit_chars()
726 if (ofs->icr == UNDEF_REG) in stm32_usart_transmit_chars()
727 stm32_usart_clr_bits(port, ofs->isr, USART_SR_TC); in stm32_usart_transmit_chars()
729 writel_relaxed(USART_ICR_TCCF, port->membase + ofs->icr); in stm32_usart_transmit_chars()
731 if (stm32_port->tx_ch) in stm32_usart_transmit_chars()
741 if (!stm32_port->hw_flow_control && in stm32_usart_transmit_chars()
742 port->rs485.flags & SER_RS485_ENABLED) { in stm32_usart_transmit_chars()
743 stm32_port->txdone = true; in stm32_usart_transmit_chars()
752 struct tty_port *tport = &port->state->port; in stm32_usart_interrupt()
754 const struct stm32_usart_offsets *ofs = &stm32_port->info->ofs; in stm32_usart_interrupt()
758 sr = readl_relaxed(port->membase + ofs->isr); in stm32_usart_interrupt()
760 if (!stm32_port->hw_flow_control && in stm32_usart_interrupt()
761 port->rs485.flags & SER_RS485_ENABLED && in stm32_usart_interrupt()
767 if ((sr & USART_SR_RTOF) && ofs->icr != UNDEF_REG) in stm32_usart_interrupt()
769 port->membase + ofs->icr); in stm32_usart_interrupt()
771 if ((sr & USART_SR_WUF) && ofs->icr != UNDEF_REG) { in stm32_usart_interrupt()
774 port->membase + ofs->icr); in stm32_usart_interrupt()
775 stm32_usart_clr_bits(port, ofs->cr3, USART_CR3_WUFIE); in stm32_usart_interrupt()
776 if (irqd_is_wakeup_set(irq_get_irq_data(port->irq))) in stm32_usart_interrupt()
777 pm_wakeup_event(tport->tty->dev, 0); in stm32_usart_interrupt()
784 if (!stm32_port->throttled) { in stm32_usart_interrupt()
787 spin_lock(&port->lock); in stm32_usart_interrupt()
795 if ((sr & USART_SR_TXE) && !(stm32_port->tx_ch)) { in stm32_usart_interrupt()
796 spin_lock(&port->lock); in stm32_usart_interrupt()
798 spin_unlock(&port->lock); in stm32_usart_interrupt()
810 struct tty_port *tport = &port->state->port; in stm32_usart_threaded_interrupt()
816 if (!stm32_port->throttled) { in stm32_usart_threaded_interrupt()
817 spin_lock_irqsave(&port->lock, flags); in stm32_usart_threaded_interrupt()
830 const struct stm32_usart_offsets *ofs = &stm32_port->info->ofs; in stm32_usart_set_mctrl()
832 if ((mctrl & TIOCM_RTS) && (port->status & UPSTAT_AUTORTS)) in stm32_usart_set_mctrl()
833 stm32_usart_set_bits(port, ofs->cr3, USART_CR3_RTSE); in stm32_usart_set_mctrl()
835 stm32_usart_clr_bits(port, ofs->cr3, USART_CR3_RTSE); in stm32_usart_set_mctrl()
837 mctrl_gpio_set(stm32_port->gpios, mctrl); in stm32_usart_set_mctrl()
848 return mctrl_gpio_get(stm32_port->gpios, &ret); in stm32_usart_get_mctrl()
853 mctrl_gpio_enable_ms(to_stm32_port(port)->gpios); in stm32_usart_enable_ms()
858 mctrl_gpio_disable_ms(to_stm32_port(port)->gpios); in stm32_usart_disable_ms()
865 const struct stm32_usart_offsets *ofs = &stm32_port->info->ofs; in stm32_usart_stop_tx()
869 stm32_usart_clr_bits(port, ofs->cr3, USART_CR3_DMAT); in stm32_usart_stop_tx()
877 struct circ_buf *xmit = &port->state->xmit; in stm32_usart_start_tx()
879 if (uart_circ_empty(xmit) && !port->x_char) { in stm32_usart_start_tx()
893 const struct stm32_usart_offsets *ofs = &stm32_port->info->ofs; in stm32_usart_flush_buffer()
895 if (stm32_port->tx_ch) { in stm32_usart_flush_buffer()
897 stm32_usart_clr_bits(port, ofs->cr3, USART_CR3_DMAT); in stm32_usart_flush_buffer()
905 const struct stm32_usart_offsets *ofs = &stm32_port->info->ofs; in stm32_usart_throttle()
908 spin_lock_irqsave(&port->lock, flags); in stm32_usart_throttle()
915 stm32_usart_clr_bits(port, ofs->cr3, USART_CR3_DMAR); in stm32_usart_throttle()
917 stm32_usart_clr_bits(port, ofs->cr1, stm32_port->cr1_irq); in stm32_usart_throttle()
918 if (stm32_port->cr3_irq) in stm32_usart_throttle()
919 stm32_usart_clr_bits(port, ofs->cr3, stm32_port->cr3_irq); in stm32_usart_throttle()
921 stm32_port->throttled = true; in stm32_usart_throttle()
922 spin_unlock_irqrestore(&port->lock, flags); in stm32_usart_throttle()
929 const struct stm32_usart_offsets *ofs = &stm32_port->info->ofs; in stm32_usart_unthrottle()
932 spin_lock_irqsave(&port->lock, flags); in stm32_usart_unthrottle()
933 stm32_usart_set_bits(port, ofs->cr1, stm32_port->cr1_irq); in stm32_usart_unthrottle()
934 if (stm32_port->cr3_irq) in stm32_usart_unthrottle()
935 stm32_usart_set_bits(port, ofs->cr3, stm32_port->cr3_irq); in stm32_usart_unthrottle()
938 * Switch back to DMA mode (re-enable DMA request line). in stm32_usart_unthrottle()
941 if (stm32_port->rx_ch) in stm32_usart_unthrottle()
942 stm32_usart_set_bits(port, ofs->cr3, USART_CR3_DMAR); in stm32_usart_unthrottle()
944 stm32_port->throttled = false; in stm32_usart_unthrottle()
945 spin_unlock_irqrestore(&port->lock, flags); in stm32_usart_unthrottle()
952 const struct stm32_usart_offsets *ofs = &stm32_port->info->ofs; in stm32_usart_stop_rx()
955 if (stm32_port->rx_ch) in stm32_usart_stop_rx()
956 stm32_usart_clr_bits(port, ofs->cr3, USART_CR3_DMAR); in stm32_usart_stop_rx()
958 stm32_usart_clr_bits(port, ofs->cr1, stm32_port->cr1_irq); in stm32_usart_stop_rx()
959 if (stm32_port->cr3_irq) in stm32_usart_stop_rx()
960 stm32_usart_clr_bits(port, ofs->cr3, stm32_port->cr3_irq); in stm32_usart_stop_rx()
963 /* Handle breaks - ignored by us */
971 const struct stm32_usart_offsets *ofs = &stm32_port->info->ofs; in stm32_usart_start_rx_dma_cyclic()
975 stm32_port->last_res = RX_BUF_L; in stm32_usart_start_rx_dma_cyclic()
977 desc = dmaengine_prep_dma_cyclic(stm32_port->rx_ch, in stm32_usart_start_rx_dma_cyclic()
978 stm32_port->rx_dma_buf, in stm32_usart_start_rx_dma_cyclic()
983 dev_err(port->dev, "rx dma prep cyclic failed\n"); in stm32_usart_start_rx_dma_cyclic()
984 return -ENODEV; in stm32_usart_start_rx_dma_cyclic()
987 desc->callback = stm32_usart_rx_dma_complete; in stm32_usart_start_rx_dma_cyclic()
988 desc->callback_param = port; in stm32_usart_start_rx_dma_cyclic()
993 dmaengine_terminate_sync(stm32_port->rx_ch); in stm32_usart_start_rx_dma_cyclic()
998 dma_async_issue_pending(stm32_port->rx_ch); in stm32_usart_start_rx_dma_cyclic()
1001 * DMA request line not re-enabled at resume when port is throttled. in stm32_usart_start_rx_dma_cyclic()
1002 * It will be re-enabled by unthrottle ops. in stm32_usart_start_rx_dma_cyclic()
1004 if (!stm32_port->throttled) in stm32_usart_start_rx_dma_cyclic()
1005 stm32_usart_set_bits(port, ofs->cr3, USART_CR3_DMAR); in stm32_usart_start_rx_dma_cyclic()
1013 const struct stm32_usart_offsets *ofs = &stm32_port->info->ofs; in stm32_usart_startup()
1014 const struct stm32_usart_config *cfg = &stm32_port->info->cfg; in stm32_usart_startup()
1015 const char *name = to_platform_device(port->dev)->name; in stm32_usart_startup()
1019 ret = request_threaded_irq(port->irq, stm32_usart_interrupt, in stm32_usart_startup()
1026 if (stm32_port->swap) { in stm32_usart_startup()
1027 val = readl_relaxed(port->membase + ofs->cr2); in stm32_usart_startup()
1029 writel_relaxed(val, port->membase + ofs->cr2); in stm32_usart_startup()
1033 if (ofs->rqr != UNDEF_REG) in stm32_usart_startup()
1034 writel_relaxed(USART_RQR_RXFRQ, port->membase + ofs->rqr); in stm32_usart_startup()
1036 if (stm32_port->rx_ch) { in stm32_usart_startup()
1039 free_irq(port->irq, port); in stm32_usart_startup()
1045 val = stm32_port->cr1_irq | USART_CR1_RE | BIT(cfg->uart_enable_bit); in stm32_usart_startup()
1046 stm32_usart_set_bits(port, ofs->cr1, val); in stm32_usart_startup()
1054 const struct stm32_usart_offsets *ofs = &stm32_port->info->ofs; in stm32_usart_shutdown()
1055 const struct stm32_usart_config *cfg = &stm32_port->info->cfg; in stm32_usart_shutdown()
1060 stm32_usart_clr_bits(port, ofs->cr3, USART_CR3_DMAT); in stm32_usart_shutdown()
1069 val |= stm32_port->cr1_irq | USART_CR1_RE; in stm32_usart_shutdown()
1070 val |= BIT(cfg->uart_enable_bit); in stm32_usart_shutdown()
1071 if (stm32_port->fifoen) in stm32_usart_shutdown()
1074 ret = readl_relaxed_poll_timeout(port->membase + ofs->isr, in stm32_usart_shutdown()
1080 dev_err(port->dev, "Transmission is not complete\n"); in stm32_usart_shutdown()
1083 if (stm32_port->rx_ch) in stm32_usart_shutdown()
1084 dmaengine_terminate_async(stm32_port->rx_ch); in stm32_usart_shutdown()
1087 if (ofs->rqr != UNDEF_REG) in stm32_usart_shutdown()
1089 port->membase + ofs->rqr); in stm32_usart_shutdown()
1091 stm32_usart_clr_bits(port, ofs->cr1, val); in stm32_usart_shutdown()
1093 free_irq(port->irq, port); in stm32_usart_shutdown()
1101 const struct stm32_usart_offsets *ofs = &stm32_port->info->ofs; in stm32_usart_set_termios()
1102 const struct stm32_usart_config *cfg = &stm32_port->info->cfg; in stm32_usart_set_termios()
1103 struct serial_rs485 *rs485conf = &port->rs485; in stm32_usart_set_termios()
1106 tcflag_t cflag = termios->c_cflag; in stm32_usart_set_termios()
1111 if (!stm32_port->hw_flow_control) in stm32_usart_set_termios()
1114 baud = uart_get_baud_rate(port, termios, old, 0, port->uartclk / 8); in stm32_usart_set_termios()
1116 spin_lock_irqsave(&port->lock, flags); in stm32_usart_set_termios()
1118 ret = readl_relaxed_poll_timeout_atomic(port->membase + ofs->isr, in stm32_usart_set_termios()
1125 dev_err(port->dev, "Transmission is not complete\n"); in stm32_usart_set_termios()
1127 /* Stop serial port and reset value */ in stm32_usart_set_termios()
1128 writel_relaxed(0, port->membase + ofs->cr1); in stm32_usart_set_termios()
1131 if (ofs->rqr != UNDEF_REG) in stm32_usart_set_termios()
1133 port->membase + ofs->rqr); in stm32_usart_set_termios()
1136 if (stm32_port->fifoen) in stm32_usart_set_termios()
1138 cr2 = stm32_port->swap ? USART_CR2_SWAP : 0; in stm32_usart_set_termios()
1141 cr3 = readl_relaxed(port->membase + ofs->cr3); in stm32_usart_set_termios()
1143 if (stm32_port->fifoen) { in stm32_usart_set_termios()
1144 if (stm32_port->txftcfg >= 0) in stm32_usart_set_termios()
1145 cr3 |= stm32_port->txftcfg << USART_CR3_TXFTCFG_SHIFT; in stm32_usart_set_termios()
1146 if (stm32_port->rxftcfg >= 0) in stm32_usart_set_termios()
1147 cr3 |= stm32_port->rxftcfg << USART_CR3_RXFTCFG_SHIFT; in stm32_usart_set_termios()
1154 stm32_port->rdr_mask = (BIT(bits) - 1); in stm32_usart_set_termios()
1170 } else if ((bits == 7) && cfg->has_7bits_data) { in stm32_usart_set_termios()
1173 dev_dbg(port->dev, "Unsupported data bits config: %u bits\n" in stm32_usart_set_termios()
1177 termios->c_cflag = cflag; in stm32_usart_set_termios()
1185 if (ofs->rtor != UNDEF_REG && (stm32_port->rx_ch || in stm32_usart_set_termios()
1186 (stm32_port->fifoen && in stm32_usart_set_termios()
1187 stm32_port->rxftcfg >= 0))) { in stm32_usart_set_termios()
1194 stm32_port->cr1_irq = USART_CR1_RTOIE; in stm32_usart_set_termios()
1195 writel_relaxed(bits, port->membase + ofs->rtor); in stm32_usart_set_termios()
1199 * wake up over usart, from low power until the DMA gets re-enabled by resume. in stm32_usart_set_termios()
1201 stm32_port->cr3_irq = USART_CR3_RXFTIE; in stm32_usart_set_termios()
1204 cr1 |= stm32_port->cr1_irq; in stm32_usart_set_termios()
1205 cr3 |= stm32_port->cr3_irq; in stm32_usart_set_termios()
1210 port->status &= ~(UPSTAT_AUTOCTS | UPSTAT_AUTORTS); in stm32_usart_set_termios()
1212 port->status |= UPSTAT_AUTOCTS | UPSTAT_AUTORTS; in stm32_usart_set_termios()
1216 usartdiv = DIV_ROUND_CLOSEST(port->uartclk, baud); in stm32_usart_set_termios()
1227 stm32_usart_set_bits(port, ofs->cr1, USART_CR1_OVER8); in stm32_usart_set_termios()
1231 stm32_usart_clr_bits(port, ofs->cr1, USART_CR1_OVER8); in stm32_usart_set_termios()
1236 writel_relaxed(mantissa | fraction, port->membase + ofs->brr); in stm32_usart_set_termios()
1240 port->read_status_mask = USART_SR_ORE; in stm32_usart_set_termios()
1241 if (termios->c_iflag & INPCK) in stm32_usart_set_termios()
1242 port->read_status_mask |= USART_SR_PE | USART_SR_FE; in stm32_usart_set_termios()
1243 if (termios->c_iflag & (IGNBRK | BRKINT | PARMRK)) in stm32_usart_set_termios()
1244 port->read_status_mask |= USART_SR_FE; in stm32_usart_set_termios()
1247 port->ignore_status_mask = 0; in stm32_usart_set_termios()
1248 if (termios->c_iflag & IGNPAR) in stm32_usart_set_termios()
1249 port->ignore_status_mask = USART_SR_PE | USART_SR_FE; in stm32_usart_set_termios()
1250 if (termios->c_iflag & IGNBRK) { in stm32_usart_set_termios()
1251 port->ignore_status_mask |= USART_SR_FE; in stm32_usart_set_termios()
1256 if (termios->c_iflag & IGNPAR) in stm32_usart_set_termios()
1257 port->ignore_status_mask |= USART_SR_ORE; in stm32_usart_set_termios()
1261 if ((termios->c_cflag & CREAD) == 0) in stm32_usart_set_termios()
1262 port->ignore_status_mask |= USART_SR_DUMMY_RX; in stm32_usart_set_termios()
1264 if (stm32_port->rx_ch) { in stm32_usart_set_termios()
1275 if (rs485conf->flags & SER_RS485_ENABLED) { in stm32_usart_set_termios()
1277 rs485conf->delay_rts_before_send, in stm32_usart_set_termios()
1278 rs485conf->delay_rts_after_send, in stm32_usart_set_termios()
1280 if (rs485conf->flags & SER_RS485_RTS_ON_SEND) { in stm32_usart_set_termios()
1282 rs485conf->flags &= ~SER_RS485_RTS_AFTER_SEND; in stm32_usart_set_termios()
1285 rs485conf->flags |= SER_RS485_RTS_AFTER_SEND; in stm32_usart_set_termios()
1293 /* Configure wake up from low power on start bit detection */ in stm32_usart_set_termios()
1294 if (stm32_port->wakeup_src) { in stm32_usart_set_termios()
1299 writel_relaxed(cr3, port->membase + ofs->cr3); in stm32_usart_set_termios()
1300 writel_relaxed(cr2, port->membase + ofs->cr2); in stm32_usart_set_termios()
1301 writel_relaxed(cr1, port->membase + ofs->cr1); in stm32_usart_set_termios()
1303 stm32_usart_set_bits(port, ofs->cr1, BIT(cfg->uart_enable_bit)); in stm32_usart_set_termios()
1304 spin_unlock_irqrestore(&port->lock, flags); in stm32_usart_set_termios()
1307 if (UART_ENABLE_MS(port, termios->c_cflag)) in stm32_usart_set_termios()
1315 return (port->type == PORT_STM32) ? DRIVER_NAME : NULL; in stm32_usart_type()
1330 port->type = PORT_STM32; in stm32_usart_config_port()
1337 return -EINVAL; in stm32_usart_verify_port()
1345 const struct stm32_usart_offsets *ofs = &stm32port->info->ofs; in stm32_usart_pm()
1346 const struct stm32_usart_config *cfg = &stm32port->info->cfg; in stm32_usart_pm()
1351 pm_runtime_get_sync(port->dev); in stm32_usart_pm()
1354 spin_lock_irqsave(&port->lock, flags); in stm32_usart_pm()
1355 stm32_usart_clr_bits(port, ofs->cr1, BIT(cfg->uart_enable_bit)); in stm32_usart_pm()
1356 spin_unlock_irqrestore(&port->lock, flags); in stm32_usart_pm()
1357 pm_runtime_put_sync(port->dev); in stm32_usart_pm()
1369 return clk_prepare_enable(stm32_port->clk); in stm32_usart_poll_init()
1375 const struct stm32_usart_offsets *ofs = &stm32_port->info->ofs; in stm32_usart_poll_get_char()
1377 if (!(readl_relaxed(port->membase + ofs->isr) & USART_SR_RXNE)) in stm32_usart_poll_get_char()
1380 return readl_relaxed(port->membase + ofs->rdr) & stm32_port->rdr_mask; in stm32_usart_poll_get_char()
1431 if (of_property_read_u32(pdev->dev.of_node, p, &bytes)) in stm32_usart_get_ftcfg()
1438 i = ARRAY_SIZE(stm32h7_usart_fifo_thresh_cfg) - 1; in stm32_usart_get_ftcfg()
1440 dev_dbg(&pdev->dev, "%s set to %d bytes\n", p, in stm32_usart_get_ftcfg()
1445 *ftcfg = i - 1; in stm32_usart_get_ftcfg()
1447 *ftcfg = -EINVAL; in stm32_usart_get_ftcfg()
1452 clk_disable_unprepare(stm32port->clk); in stm32_usart_deinit_port()
1465 struct uart_port *port = &stm32port->port; in stm32_usart_init_port()
1473 port->iotype = UPIO_MEM; in stm32_usart_init_port()
1474 port->flags = UPF_BOOT_AUTOCONF; in stm32_usart_init_port()
1475 port->ops = &stm32_uart_ops; in stm32_usart_init_port()
1476 port->dev = &pdev->dev; in stm32_usart_init_port()
1477 port->fifosize = stm32port->info->cfg.fifosize; in stm32_usart_init_port()
1478 port->has_sysrq = IS_ENABLED(CONFIG_SERIAL_STM32_CONSOLE); in stm32_usart_init_port()
1479 port->irq = irq; in stm32_usart_init_port()
1480 port->rs485_config = stm32_usart_config_rs485; in stm32_usart_init_port()
1481 port->rs485_supported = stm32_rs485_supported; in stm32_usart_init_port()
1487 stm32port->wakeup_src = stm32port->info->cfg.has_wakeup && in stm32_usart_init_port()
1488 of_property_read_bool(pdev->dev.of_node, "wakeup-source"); in stm32_usart_init_port()
1490 stm32port->swap = stm32port->info->cfg.has_swap && in stm32_usart_init_port()
1491 of_property_read_bool(pdev->dev.of_node, "rx-tx-swap"); in stm32_usart_init_port()
1493 stm32port->fifoen = stm32port->info->cfg.has_fifo; in stm32_usart_init_port()
1494 if (stm32port->fifoen) { in stm32_usart_init_port()
1495 stm32_usart_get_ftcfg(pdev, "rx-threshold", in stm32_usart_init_port()
1496 &stm32port->rxftcfg); in stm32_usart_init_port()
1497 stm32_usart_get_ftcfg(pdev, "tx-threshold", in stm32_usart_init_port()
1498 &stm32port->txftcfg); in stm32_usart_init_port()
1501 port->membase = devm_platform_get_and_ioremap_resource(pdev, 0, &res); in stm32_usart_init_port()
1502 if (IS_ERR(port->membase)) in stm32_usart_init_port()
1503 return PTR_ERR(port->membase); in stm32_usart_init_port()
1504 port->mapbase = res->start; in stm32_usart_init_port()
1506 spin_lock_init(&port->lock); in stm32_usart_init_port()
1508 stm32port->clk = devm_clk_get(&pdev->dev, NULL); in stm32_usart_init_port()
1509 if (IS_ERR(stm32port->clk)) in stm32_usart_init_port()
1510 return PTR_ERR(stm32port->clk); in stm32_usart_init_port()
1512 /* Ensure that clk rate is correct by enabling the clk */ in stm32_usart_init_port()
1513 ret = clk_prepare_enable(stm32port->clk); in stm32_usart_init_port()
1517 stm32port->port.uartclk = clk_get_rate(stm32port->clk); in stm32_usart_init_port()
1518 if (!stm32port->port.uartclk) { in stm32_usart_init_port()
1519 ret = -EINVAL; in stm32_usart_init_port()
1523 stm32port->gpios = mctrl_gpio_init(&stm32port->port, 0); in stm32_usart_init_port()
1524 if (IS_ERR(stm32port->gpios)) { in stm32_usart_init_port()
1525 ret = PTR_ERR(stm32port->gpios); in stm32_usart_init_port()
1530 * Both CTS/RTS gpios and "st,hw-flow-ctrl" (deprecated) or "uart-has-rtscts" in stm32_usart_init_port()
1533 if (stm32port->hw_flow_control) { in stm32_usart_init_port()
1534 if (mctrl_gpio_to_gpiod(stm32port->gpios, UART_GPIO_CTS) || in stm32_usart_init_port()
1535 mctrl_gpio_to_gpiod(stm32port->gpios, UART_GPIO_RTS)) { in stm32_usart_init_port()
1536 dev_err(&pdev->dev, "Conflicting RTS/CTS config\n"); in stm32_usart_init_port()
1537 ret = -EINVAL; in stm32_usart_init_port()
1545 clk_disable_unprepare(stm32port->clk); in stm32_usart_init_port()
1552 struct device_node *np = pdev->dev.of_node; in stm32_usart_of_get_port()
1558 id = of_alias_get_id(np, "serial"); in stm32_usart_of_get_port()
1560 dev_err(&pdev->dev, "failed to get alias id, errno %d\n", id); in stm32_usart_of_get_port()
1568 of_property_read_bool (np, "st,hw-flow-ctrl") /*deprecated*/ || in stm32_usart_of_get_port()
1569 of_property_read_bool (np, "uart-has-rtscts"); in stm32_usart_of_get_port()
1579 { .compatible = "st,stm32-uart", .data = &stm32f4_info},
1580 { .compatible = "st,stm32f7-uart", .data = &stm32f7_info},
1581 { .compatible = "st,stm32h7-uart", .data = &stm32h7_info},
1591 if (stm32port->rx_buf) in stm32_usart_of_dma_rx_remove()
1592 dma_free_coherent(&pdev->dev, RX_BUF_L, stm32port->rx_buf, in stm32_usart_of_dma_rx_remove()
1593 stm32port->rx_dma_buf); in stm32_usart_of_dma_rx_remove()
1599 const struct stm32_usart_offsets *ofs = &stm32port->info->ofs; in stm32_usart_of_dma_rx_probe()
1600 struct uart_port *port = &stm32port->port; in stm32_usart_of_dma_rx_probe()
1601 struct device *dev = &pdev->dev; in stm32_usart_of_dma_rx_probe()
1610 return -ENODEV; in stm32_usart_of_dma_rx_probe()
1612 stm32port->rx_buf = dma_alloc_coherent(dev, RX_BUF_L, in stm32_usart_of_dma_rx_probe()
1613 &stm32port->rx_dma_buf, in stm32_usart_of_dma_rx_probe()
1615 if (!stm32port->rx_buf) in stm32_usart_of_dma_rx_probe()
1616 return -ENOMEM; in stm32_usart_of_dma_rx_probe()
1620 config.src_addr = port->mapbase + ofs->rdr; in stm32_usart_of_dma_rx_probe()
1623 ret = dmaengine_slave_config(stm32port->rx_ch, &config); in stm32_usart_of_dma_rx_probe()
1636 if (stm32port->tx_buf) in stm32_usart_of_dma_tx_remove()
1637 dma_free_coherent(&pdev->dev, TX_BUF_L, stm32port->tx_buf, in stm32_usart_of_dma_tx_remove()
1638 stm32port->tx_dma_buf); in stm32_usart_of_dma_tx_remove()
1644 const struct stm32_usart_offsets *ofs = &stm32port->info->ofs; in stm32_usart_of_dma_tx_probe()
1645 struct uart_port *port = &stm32port->port; in stm32_usart_of_dma_tx_probe()
1646 struct device *dev = &pdev->dev; in stm32_usart_of_dma_tx_probe()
1650 stm32port->tx_buf = dma_alloc_coherent(dev, TX_BUF_L, in stm32_usart_of_dma_tx_probe()
1651 &stm32port->tx_dma_buf, in stm32_usart_of_dma_tx_probe()
1653 if (!stm32port->tx_buf) in stm32_usart_of_dma_tx_probe()
1654 return -ENOMEM; in stm32_usart_of_dma_tx_probe()
1658 config.dst_addr = port->mapbase + ofs->tdr; in stm32_usart_of_dma_tx_probe()
1661 ret = dmaengine_slave_config(stm32port->tx_ch, &config); in stm32_usart_of_dma_tx_probe()
1678 return -ENODEV; in stm32_usart_serial_probe()
1680 stm32port->info = of_device_get_match_data(&pdev->dev); in stm32_usart_serial_probe()
1681 if (!stm32port->info) in stm32_usart_serial_probe()
1682 return -EINVAL; in stm32_usart_serial_probe()
1688 if (stm32port->wakeup_src) { in stm32_usart_serial_probe()
1689 device_set_wakeup_capable(&pdev->dev, true); in stm32_usart_serial_probe()
1690 ret = dev_pm_set_wake_irq(&pdev->dev, stm32port->port.irq); in stm32_usart_serial_probe()
1695 stm32port->rx_ch = dma_request_chan(&pdev->dev, "rx"); in stm32_usart_serial_probe()
1696 if (PTR_ERR(stm32port->rx_ch) == -EPROBE_DEFER) { in stm32_usart_serial_probe()
1697 ret = -EPROBE_DEFER; in stm32_usart_serial_probe()
1700 /* Fall back in interrupt mode for any non-deferral error */ in stm32_usart_serial_probe()
1701 if (IS_ERR(stm32port->rx_ch)) in stm32_usart_serial_probe()
1702 stm32port->rx_ch = NULL; in stm32_usart_serial_probe()
1704 stm32port->tx_ch = dma_request_chan(&pdev->dev, "tx"); in stm32_usart_serial_probe()
1705 if (PTR_ERR(stm32port->tx_ch) == -EPROBE_DEFER) { in stm32_usart_serial_probe()
1706 ret = -EPROBE_DEFER; in stm32_usart_serial_probe()
1709 /* Fall back in interrupt mode for any non-deferral error */ in stm32_usart_serial_probe()
1710 if (IS_ERR(stm32port->tx_ch)) in stm32_usart_serial_probe()
1711 stm32port->tx_ch = NULL; in stm32_usart_serial_probe()
1713 if (stm32port->rx_ch && stm32_usart_of_dma_rx_probe(stm32port, pdev)) { in stm32_usart_serial_probe()
1715 dma_release_channel(stm32port->rx_ch); in stm32_usart_serial_probe()
1716 stm32port->rx_ch = NULL; in stm32_usart_serial_probe()
1719 if (stm32port->tx_ch && stm32_usart_of_dma_tx_probe(stm32port, pdev)) { in stm32_usart_serial_probe()
1721 dma_release_channel(stm32port->tx_ch); in stm32_usart_serial_probe()
1722 stm32port->tx_ch = NULL; in stm32_usart_serial_probe()
1725 if (!stm32port->rx_ch) in stm32_usart_serial_probe()
1726 dev_info(&pdev->dev, "interrupt mode for rx (no dma)\n"); in stm32_usart_serial_probe()
1727 if (!stm32port->tx_ch) in stm32_usart_serial_probe()
1728 dev_info(&pdev->dev, "interrupt mode for tx (no dma)\n"); in stm32_usart_serial_probe()
1730 platform_set_drvdata(pdev, &stm32port->port); in stm32_usart_serial_probe()
1732 pm_runtime_get_noresume(&pdev->dev); in stm32_usart_serial_probe()
1733 pm_runtime_set_active(&pdev->dev); in stm32_usart_serial_probe()
1734 pm_runtime_enable(&pdev->dev); in stm32_usart_serial_probe()
1736 ret = uart_add_one_port(&stm32_usart_driver, &stm32port->port); in stm32_usart_serial_probe()
1740 pm_runtime_put_sync(&pdev->dev); in stm32_usart_serial_probe()
1745 pm_runtime_disable(&pdev->dev); in stm32_usart_serial_probe()
1746 pm_runtime_set_suspended(&pdev->dev); in stm32_usart_serial_probe()
1747 pm_runtime_put_noidle(&pdev->dev); in stm32_usart_serial_probe()
1749 if (stm32port->tx_ch) { in stm32_usart_serial_probe()
1751 dma_release_channel(stm32port->tx_ch); in stm32_usart_serial_probe()
1754 if (stm32port->rx_ch) in stm32_usart_serial_probe()
1758 if (stm32port->rx_ch) in stm32_usart_serial_probe()
1759 dma_release_channel(stm32port->rx_ch); in stm32_usart_serial_probe()
1762 if (stm32port->wakeup_src) in stm32_usart_serial_probe()
1763 dev_pm_clear_wake_irq(&pdev->dev); in stm32_usart_serial_probe()
1766 if (stm32port->wakeup_src) in stm32_usart_serial_probe()
1767 device_set_wakeup_capable(&pdev->dev, false); in stm32_usart_serial_probe()
1778 const struct stm32_usart_offsets *ofs = &stm32_port->info->ofs; in stm32_usart_serial_remove()
1782 pm_runtime_get_sync(&pdev->dev); in stm32_usart_serial_remove()
1787 pm_runtime_disable(&pdev->dev); in stm32_usart_serial_remove()
1788 pm_runtime_set_suspended(&pdev->dev); in stm32_usart_serial_remove()
1789 pm_runtime_put_noidle(&pdev->dev); in stm32_usart_serial_remove()
1791 stm32_usart_clr_bits(port, ofs->cr1, USART_CR1_PEIE); in stm32_usart_serial_remove()
1792 cr3 = readl_relaxed(port->membase + ofs->cr3); in stm32_usart_serial_remove()
1796 writel_relaxed(cr3, port->membase + ofs->cr3); in stm32_usart_serial_remove()
1798 if (stm32_port->tx_ch) { in stm32_usart_serial_remove()
1800 dma_release_channel(stm32_port->tx_ch); in stm32_usart_serial_remove()
1803 if (stm32_port->rx_ch) { in stm32_usart_serial_remove()
1805 dma_release_channel(stm32_port->rx_ch); in stm32_usart_serial_remove()
1808 stm32_usart_clr_bits(port, ofs->cr3, USART_CR3_DMAT); in stm32_usart_serial_remove()
1810 if (stm32_port->wakeup_src) { in stm32_usart_serial_remove()
1811 dev_pm_clear_wake_irq(&pdev->dev); in stm32_usart_serial_remove()
1812 device_init_wakeup(&pdev->dev, false); in stm32_usart_serial_remove()
1823 const struct stm32_usart_offsets *ofs = &stm32_port->info->ofs; in stm32_usart_console_putchar()
1827 ret = readl_relaxed_poll_timeout_atomic(port->membase + ofs->isr, isr, in stm32_usart_console_putchar()
1831 dev_err(port->dev, "Error while sending data in UART TX : %d\n", ret); in stm32_usart_console_putchar()
1834 writel_relaxed(ch, port->membase + ofs->tdr); in stm32_usart_console_putchar()
1841 struct uart_port *port = &stm32_ports[co->index].port; in stm32_usart_console_write()
1843 const struct stm32_usart_offsets *ofs = &stm32_port->info->ofs; in stm32_usart_console_write()
1844 const struct stm32_usart_config *cfg = &stm32_port->info->cfg; in stm32_usart_console_write()
1850 locked = spin_trylock_irqsave(&port->lock, flags); in stm32_usart_console_write()
1852 spin_lock_irqsave(&port->lock, flags); in stm32_usart_console_write()
1855 old_cr1 = readl_relaxed(port->membase + ofs->cr1); in stm32_usart_console_write()
1857 new_cr1 |= USART_CR1_TE | BIT(cfg->uart_enable_bit); in stm32_usart_console_write()
1858 writel_relaxed(new_cr1, port->membase + ofs->cr1); in stm32_usart_console_write()
1863 writel_relaxed(old_cr1, port->membase + ofs->cr1); in stm32_usart_console_write()
1866 spin_unlock_irqrestore(&port->lock, flags); in stm32_usart_console_write()
1877 if (co->index >= STM32_MAX_PORTS) in stm32_usart_console_setup()
1878 return -ENODEV; in stm32_usart_console_setup()
1880 stm32port = &stm32_ports[co->index]; in stm32_usart_console_setup()
1888 if (stm32port->port.mapbase == 0 || !stm32port->port.membase) in stm32_usart_console_setup()
1889 return -ENXIO; in stm32_usart_console_setup()
1894 return uart_set_options(&stm32port->port, co, baud, parity, bits, flow); in stm32_usart_console_setup()
1903 .index = -1,
1916 struct stm32_usart_info *info = port->private_data; in early_stm32_usart_console_putchar()
1918 while (!(readl_relaxed(port->membase + info->ofs.isr) & USART_SR_TXE)) in early_stm32_usart_console_putchar()
1921 writel_relaxed(ch, port->membase + info->ofs.tdr); in early_stm32_usart_console_putchar()
1926 struct earlycon_device *device = console->data; in early_stm32_serial_write()
1927 struct uart_port *port = &device->port; in early_stm32_serial_write()
1934 if (!(device->port.membase || device->port.iobase)) in early_stm32_h7_serial_setup()
1935 return -ENODEV; in early_stm32_h7_serial_setup()
1936 device->port.private_data = &stm32h7_info; in early_stm32_h7_serial_setup()
1937 device->con->write = early_stm32_serial_write; in early_stm32_h7_serial_setup()
1943 if (!(device->port.membase || device->port.iobase)) in early_stm32_f7_serial_setup()
1944 return -ENODEV; in early_stm32_f7_serial_setup()
1945 device->port.private_data = &stm32f7_info; in early_stm32_f7_serial_setup()
1946 device->con->write = early_stm32_serial_write; in early_stm32_f7_serial_setup()
1952 if (!(device->port.membase || device->port.iobase)) in early_stm32_f4_serial_setup()
1953 return -ENODEV; in early_stm32_f4_serial_setup()
1954 device->port.private_data = &stm32f4_info; in early_stm32_f4_serial_setup()
1955 device->con->write = early_stm32_serial_write; in early_stm32_f4_serial_setup()
1959 OF_EARLYCON_DECLARE(stm32, "st,stm32h7-uart", early_stm32_h7_serial_setup);
1960 OF_EARLYCON_DECLARE(stm32, "st,stm32f7-uart", early_stm32_f7_serial_setup);
1961 OF_EARLYCON_DECLARE(stm32, "st,stm32-uart", early_stm32_f4_serial_setup);
1977 const struct stm32_usart_offsets *ofs = &stm32_port->info->ofs; in stm32_usart_serial_en_wakeup()
1978 struct tty_port *tport = &port->state->port; in stm32_usart_serial_en_wakeup()
1983 if (!stm32_port->wakeup_src || !tty_port_initialized(tport)) in stm32_usart_serial_en_wakeup()
1987 * Enable low-power wake-up and wake-up irq if argument is set to in stm32_usart_serial_en_wakeup()
1988 * "enable", disable low-power wake-up and wake-up irq otherwise in stm32_usart_serial_en_wakeup()
1991 stm32_usart_set_bits(port, ofs->cr1, USART_CR1_UESM); in stm32_usart_serial_en_wakeup()
1992 stm32_usart_set_bits(port, ofs->cr3, USART_CR3_WUFIE); in stm32_usart_serial_en_wakeup()
1993 mctrl_gpio_enable_irq_wake(stm32_port->gpios); in stm32_usart_serial_en_wakeup()
1997 * entering low-power mode and re-enabled when exiting from in stm32_usart_serial_en_wakeup()
1998 * low-power mode. in stm32_usart_serial_en_wakeup()
2000 if (stm32_port->rx_ch) { in stm32_usart_serial_en_wakeup()
2001 spin_lock_irqsave(&port->lock, flags); in stm32_usart_serial_en_wakeup()
2003 stm32_usart_clr_bits(port, ofs->cr3, USART_CR3_DMAR); in stm32_usart_serial_en_wakeup()
2006 dmaengine_terminate_async(stm32_port->rx_ch); in stm32_usart_serial_en_wakeup()
2015 if (stm32_port->rx_ch) { in stm32_usart_serial_en_wakeup()
2020 mctrl_gpio_disable_irq_wake(stm32_port->gpios); in stm32_usart_serial_en_wakeup()
2021 stm32_usart_clr_bits(port, ofs->cr1, USART_CR1_UESM); in stm32_usart_serial_en_wakeup()
2022 stm32_usart_clr_bits(port, ofs->cr3, USART_CR3_WUFIE); in stm32_usart_serial_en_wakeup()
2079 clk_disable_unprepare(stm32port->clk); in stm32_usart_runtime_suspend()
2090 return clk_prepare_enable(stm32port->clk); in stm32_usart_runtime_resume()
2138 MODULE_DESCRIPTION("STMicroelectronics STM32 serial port driver");