197 #define REG_GET_MASK(r, m)	(((r) & (m)) >> (ffs(m) - 1))  macro
430 	val = REG_GET_MASK(val, zone->sg->sensor_temp_mask);  in tegra_thermctl_get_temp()
1272 		state = REG_GET_MASK(r, SENSOR_CONFIG1_TEMP_ENABLE);  in regs_show()
1282 		state = REG_GET_MASK(r, SENSOR_CONFIG1_TIDDQ_EN_MASK);  in regs_show()
1284 		state = REG_GET_MASK(r, SENSOR_CONFIG1_TEN_COUNT_MASK);  in regs_show()
1286 		state = REG_GET_MASK(r, SENSOR_CONFIG1_TSAMPLE_MASK);  in regs_show()
1290 		state = REG_GET_MASK(r, SENSOR_STATUS1_TEMP_VALID_MASK);  in regs_show()
1292 		state = REG_GET_MASK(r, SENSOR_STATUS1_TEMP_MASK);  in regs_show()
1296 		state = REG_GET_MASK(r, SENSOR_STATUS0_VALID_MASK);  in regs_show()
1298 		state = REG_GET_MASK(r, SENSOR_STATUS0_CAPTURE_MASK);  in regs_show()
1302 		state = REG_GET_MASK(r, SENSOR_CONFIG0_STOP);  in regs_show()
1304 		state = REG_GET_MASK(r, SENSOR_CONFIG0_TALL_MASK);  in regs_show()
1306 		state = REG_GET_MASK(r, SENSOR_CONFIG0_TCALC_OVER);  in regs_show()
1308 		state = REG_GET_MASK(r, SENSOR_CONFIG0_OVER);  in regs_show()
1310 		state = REG_GET_MASK(r, SENSOR_CONFIG0_CPTR_OVER);  in regs_show()
1314 		state = REG_GET_MASK(r, SENSOR_CONFIG2_THERMA_MASK);  in regs_show()
1316 		state = REG_GET_MASK(r, SENSOR_CONFIG2_THERMB_MASK);  in regs_show()
1330 	state = REG_GET_MASK(r, SENSOR_TEMP1_CPU_TEMP_MASK);  in regs_show()
1332 	state = REG_GET_MASK(r, SENSOR_TEMP1_GPU_TEMP_MASK);  in regs_show()
1335 	state = REG_GET_MASK(r, SENSOR_TEMP2_PLLX_TEMP_MASK);  in regs_show()
1337 	state = REG_GET_MASK(r, SENSOR_TEMP2_MEM_TEMP_MASK);  in regs_show()
1350 			state = REG_GET_MASK(r, mask);  in regs_show()
1356 			state = REG_GET_MASK(r, mask);  in regs_show()
1362 			state = REG_GET_MASK(r, mask);  in regs_show()
1366 			state = REG_GET_MASK(r, mask);  in regs_show()
1378 			state = REG_GET_MASK(r, mask);  in regs_show()
1390 			state = REG_GET_MASK(r, mask);  in regs_show()
1416 	state = REG_GET_MASK(r, ttgs[0]->thermtrip_any_en_mask);  in regs_show()
1419 		state = REG_GET_MASK(r, ttgs[i]->thermtrip_enable_mask);  in regs_show()
1421 		state = REG_GET_MASK(r, ttgs[i]->thermtrip_threshold_mask);  in regs_show()
1432 	state = REG_GET_MASK(r, THROT_STATUS_BREACH_MASK);  in regs_show()
1434 	state = REG_GET_MASK(r, THROT_STATUS_STATE_MASK);  in regs_show()
1436 	state = REG_GET_MASK(r, THROT_STATUS_ENABLED_MASK);  in regs_show()
1441 		state = REG_GET_MASK(r, XPU_PSKIP_STATUS_ENABLED_MASK);  in regs_show()
1444 		state = REG_GET_MASK(r, XPU_PSKIP_STATUS_M_MASK);  in regs_show()
1446 		state = REG_GET_MASK(r, XPU_PSKIP_STATUS_N_MASK);  in regs_show()
1448 		state = REG_GET_MASK(r, XPU_PSKIP_STATUS_ENABLED_MASK);  in regs_show()
1519 	if (REG_GET_MASK(r, THROT_STATUS_STATE_MASK))  in throt_get_cdev_cur_state()
1931 	r = REG_GET_MASK(r, THROT_PRIORITY_LOCK_PRIORITY_MASK);  in soctherm_throttle_program()