Lines Matching +full:lo +full:- +full:en
1 // SPDX-License-Identifier: GPL-2.0
3 * Copyright (c) 2014 - 2018, NVIDIA CORPORATION. All rights reserved.
34 #include <dt-bindings/thermal/tegra124-soctherm.h>
197 #define REG_GET_MASK(r, m) (((r) & (m)) >> (ffs(m) - 1))
200 (((v) & (m >> (ffs(m) - 1))) << (ffs(m) - 1)))
203 #define THROT_DEPTH_DIVIDEND(depth) ((256 * (100 - (depth)) / 100) - 1)
205 /* gk20a nv_therm interface N:3 Mapping. Levels defined in tegra124-soctherm.h
212 #define THROT_LEVEL_TO_DEPTH(level) ((0x1 << (level)) - 1)
229 (ALARM_OFFSET * (throt - THROTTLE_OC1)))
232 (ALARM_OFFSET * (throt - THROTTLE_OC1)))
235 (ALARM_OFFSET * (throt - THROTTLE_OC1)))
238 (ALARM_OFFSET * (throt - THROTTLE_OC1)))
241 (ALARM_OFFSET * (throt - THROTTLE_OC1)))
244 (4 * (throt - THROTTLE_OC1)))
260 static const int min_low_temp = -127000;
361 * ccroc_writel() - writes a value to a CCROC register
370 writel(value, (ts->ccroc_regs + reg)); in ccroc_writel()
374 * ccroc_readl() - reads specified register from CCROC IP block
382 return readl(ts->ccroc_regs + reg); in ccroc_readl()
387 const struct tegra_tsensor *sensor = &tegra->soc->tsensors[i]; in enable_tsensor()
388 void __iomem *base = tegra->regs + sensor->base; in enable_tsensor()
391 val = sensor->config->tall << SENSOR_CONFIG0_TALL_SHIFT; in enable_tsensor()
394 val = (sensor->config->tsample - 1) << SENSOR_CONFIG1_TSAMPLE_SHIFT; in enable_tsensor()
395 val |= sensor->config->tiddq_en << SENSOR_CONFIG1_TIDDQ_EN_SHIFT; in enable_tsensor()
396 val |= sensor->config->ten_count << SENSOR_CONFIG1_TEN_COUNT_SHIFT; in enable_tsensor()
400 writel(tegra->calib[i], base + SENSOR_CONFIG2); in enable_tsensor()
419 t *= -1; in translate_temp()
426 struct tegra_thermctl_zone *zone = tz->devdata; in tegra_thermctl_get_temp()
429 val = readl(zone->reg); in tegra_thermctl_get_temp()
430 val = REG_GET_MASK(val, zone->sg->sensor_temp_mask); in tegra_thermctl_get_temp()
437 * enforce_temp_range() - check and enforce temperature range [min, max]
459 * thermtrip_program() - Configures the hardware to shut down the
472 * Return: 0 upon success, or %-EINVAL upon failure.
482 if (!sg || !sg->thermtrip_threshold_mask) in thermtrip_program()
483 return -EINVAL; in thermtrip_program()
485 temp = enforce_temp_range(dev, trip_temp) / ts->soc->thresh_grain; in thermtrip_program()
487 r = readl(ts->regs + THERMCTL_THERMTRIP_CTL); in thermtrip_program()
488 r = REG_SET_MASK(r, sg->thermtrip_threshold_mask, temp); in thermtrip_program()
489 r = REG_SET_MASK(r, sg->thermtrip_enable_mask, 1); in thermtrip_program()
490 r = REG_SET_MASK(r, sg->thermtrip_any_en_mask, 0); in thermtrip_program()
491 writel(r, ts->regs + THERMCTL_THERMTRIP_CTL); in thermtrip_program()
497 * throttrip_program() - Configures the hardware to throttle the
511 * Return: 0 upon success, or %-EINVAL upon failure.
523 if (!sg || !stc || !stc->init) in throttrip_program()
524 return -EINVAL; in throttrip_program()
526 temp = enforce_temp_range(dev, trip_temp) / ts->soc->thresh_grain; in throttrip_program()
529 throt = stc->id; in throttrip_program()
530 reg_off = THERMCTL_LVL_REG(sg->thermctl_lvl0_offset, throt + 1); in throttrip_program()
540 "invalid throt id %d - assuming HEAVY", in throttrip_program()
544 r = readl(ts->regs + reg_off); in throttrip_program()
545 r = REG_SET_MASK(r, sg->thermctl_lvl0_up_thresh_mask, temp); in throttrip_program()
546 r = REG_SET_MASK(r, sg->thermctl_lvl0_dn_thresh_mask, temp); in throttrip_program()
550 writel(r, ts->regs + reg_off); in throttrip_program()
560 for (i = 0; ts->throt_cfgs[i].name; i++) in find_throttle_cfg_by_name()
561 if (!strcmp(ts->throt_cfgs[i].name, name)) in find_throttle_cfg_by_name()
562 return &ts->throt_cfgs[i]; in find_throttle_cfg_by_name()
570 struct tsensor_group_thermtrips *tt = ts->soc->thermtrips; in tsensor_group_thermtrip_get()
576 for (i = 0; i < ts->soc->num_ttgs; i++) { in tsensor_group_thermtrip_get()
587 struct tegra_thermctl_zone *zone = tz->devdata; in tegra_thermctl_set_trip_temp()
588 struct tegra_soctherm *ts = zone->ts; in tegra_thermctl_set_trip_temp()
589 const struct tegra_tsensor_group *sg = zone->sg; in tegra_thermctl_set_trip_temp()
590 struct device *dev = zone->dev; in tegra_thermctl_set_trip_temp()
595 return -EINVAL; in tegra_thermctl_set_trip_temp()
597 ret = tz->ops->get_trip_type(tz, trip, &type); in tegra_thermctl_set_trip_temp()
607 if (min_low_temp == tsensor_group_thermtrip_get(ts, sg->id)) in tegra_thermctl_set_trip_temp()
619 if (!ts->throt_cfgs[i].init) in tegra_thermctl_set_trip_temp()
622 cdev = ts->throt_cfgs[i].cdev; in tegra_thermctl_set_trip_temp()
624 stc = find_throttle_cfg_by_name(ts, cdev->type); in tegra_thermctl_set_trip_temp()
640 mutex_lock(&zn->ts->thermctl_lock); in thermal_irq_enable()
641 r = readl(zn->ts->regs + THERMCTL_INTR_ENABLE); in thermal_irq_enable()
642 r = REG_SET_MASK(r, zn->sg->thermctl_isr_mask, TH_INTR_UP_DN_EN); in thermal_irq_enable()
643 writel(r, zn->ts->regs + THERMCTL_INTR_ENABLE); in thermal_irq_enable()
644 mutex_unlock(&zn->ts->thermctl_lock); in thermal_irq_enable()
652 mutex_lock(&zn->ts->thermctl_lock); in thermal_irq_disable()
653 r = readl(zn->ts->regs + THERMCTL_INTR_DISABLE); in thermal_irq_disable()
654 r = REG_SET_MASK(r, zn->sg->thermctl_isr_mask, 0); in thermal_irq_disable()
655 writel(r, zn->ts->regs + THERMCTL_INTR_DISABLE); in thermal_irq_disable()
656 mutex_unlock(&zn->ts->thermctl_lock); in thermal_irq_disable()
659 static int tegra_thermctl_set_trips(struct thermal_zone_device *tz, int lo, int hi) in tegra_thermctl_set_trips() argument
661 struct tegra_thermctl_zone *zone = tz->devdata; in tegra_thermctl_set_trips()
666 r = readl(zone->ts->regs + zone->sg->thermctl_lvl0_offset); in tegra_thermctl_set_trips()
668 writel(r, zone->ts->regs + zone->sg->thermctl_lvl0_offset); in tegra_thermctl_set_trips()
670 lo = enforce_temp_range(zone->dev, lo) / zone->ts->soc->thresh_grain; in tegra_thermctl_set_trips()
671 hi = enforce_temp_range(zone->dev, hi) / zone->ts->soc->thresh_grain; in tegra_thermctl_set_trips()
672 dev_dbg(zone->dev, "%s hi:%d, lo:%d\n", __func__, hi, lo); in tegra_thermctl_set_trips()
674 r = REG_SET_MASK(r, zone->sg->thermctl_lvl0_up_thresh_mask, hi); in tegra_thermctl_set_trips()
675 r = REG_SET_MASK(r, zone->sg->thermctl_lvl0_dn_thresh_mask, lo); in tegra_thermctl_set_trips()
677 writel(r, zone->ts->regs + zone->sg->thermctl_lvl0_offset); in tegra_thermctl_set_trips()
697 return -EINVAL; in get_hot_temp()
700 ret = tz->ops->get_trip_type(tz, i, &type); in get_hot_temp()
702 return -EINVAL; in get_hot_temp()
704 ret = tz->ops->get_trip_temp(tz, i, temp); in get_hot_temp()
712 return -EINVAL; in get_hot_temp()
716 * tegra_soctherm_set_hwtrips() - set HW trip point from DT data
748 temperature = tsensor_group_thermtrip_get(ts, sg->id); in tegra_soctherm_set_hwtrips()
750 if (tz->ops->get_crit_temp(tz, &temperature)) in tegra_soctherm_set_hwtrips()
755 dev_err(dev, "thermtrip: %s: error during enable\n", sg->name); in tegra_soctherm_set_hwtrips()
760 sg->name, temperature); in tegra_soctherm_set_hwtrips()
765 sg->name); in tegra_soctherm_set_hwtrips()
772 if (!ts->throt_cfgs[i].init) in tegra_soctherm_set_hwtrips()
775 cdev = ts->throt_cfgs[i].cdev; in tegra_soctherm_set_hwtrips()
777 stc = find_throttle_cfg_by_name(ts, cdev->type); in tegra_soctherm_set_hwtrips()
784 sg->name); in tegra_soctherm_set_hwtrips()
790 sg->name, temperature); in tegra_soctherm_set_hwtrips()
796 sg->name); in tegra_soctherm_set_hwtrips()
812 * cause a new interrupt but this is taken care of by the re-reading of in soctherm_thermal_isr()
815 r = readl(ts->regs + THERMCTL_INTR_STATUS); in soctherm_thermal_isr()
816 writel(r, ts->regs + THERMCTL_INTR_DISABLE); in soctherm_thermal_isr()
822 * soctherm_thermal_isr_thread() - Handles a thermal interrupt request
833 * Disabled interrupts are re-enabled.
844 st = readl(ts->regs + THERMCTL_INTR_STATUS); in soctherm_thermal_isr_thread()
861 writel(ex, ts->regs + THERMCTL_INTR_STATUS); in soctherm_thermal_isr_thread()
865 tz = ts->thermctl_tzs[TEGRA124_SOCTHERM_SENSOR_CPU]; in soctherm_thermal_isr_thread()
871 tz = ts->thermctl_tzs[TEGRA124_SOCTHERM_SENSOR_GPU]; in soctherm_thermal_isr_thread()
877 tz = ts->thermctl_tzs[TEGRA124_SOCTHERM_SENSOR_PLLX]; in soctherm_thermal_isr_thread()
883 tz = ts->thermctl_tzs[TEGRA124_SOCTHERM_SENSOR_MEM]; in soctherm_thermal_isr_thread()
896 writel(st, ts->regs + THERMCTL_INTR_STATUS); in soctherm_thermal_isr_thread()
903 * soctherm_oc_intr_enable() - Enables the soctherm over-current interrupt
906 * @enable: Flag indicating enable the soctherm over-current
909 * Enables a specific over-current pins @alarm to raise an interrupt if the flag
921 r = readl(ts->regs + OC_INTR_ENABLE); in soctherm_oc_intr_enable()
939 writel(r, ts->regs + OC_INTR_ENABLE); in soctherm_oc_intr_enable()
943 * soctherm_handle_alarm() - Handles soctherm alarms
946 * "Handles" over-current alarms (OC1, OC2, OC3, and OC4) by printing
949 * Return: -EINVAL for @alarm = THROTTLE_OC3, otherwise 0 (success).
953 int rv = -EINVAL; in soctherm_handle_alarm()
988 * soctherm_edp_isr_thread() - log an over-current interrupt request
992 * Over-current events are handled in hardware. This function is called to log
994 * over-current interrupt registers for registers are set but
1005 st = readl(ts->regs + OC_INTR_STATUS); in soctherm_edp_isr_thread()
1016 writel(st, ts->regs + OC_INTR_STATUS); in soctherm_edp_isr_thread()
1050 writel(st, ts->regs + OC_INTR_STATUS); in soctherm_edp_isr_thread()
1057 * soctherm_edp_isr() - Disables any active interrupts
1064 * handle asserted interrupts and subsequently unmask/re-enable them.
1079 r = readl(ts->regs + OC_INTR_STATUS); in soctherm_edp_isr()
1080 writel(r, ts->regs + OC_INTR_DISABLE); in soctherm_edp_isr()
1086 * soctherm_oc_irq_lock() - locks the over-current interrupt request
1090 * a particular over-current interrupt request.
1096 mutex_lock(&d->irq_lock); in soctherm_oc_irq_lock()
1100 * soctherm_oc_irq_sync_unlock() - Unlocks the OC interrupt request
1104 * with a particular over-current interrupt request.
1110 mutex_unlock(&d->irq_lock); in soctherm_oc_irq_sync_unlock()
1114 * soctherm_oc_irq_enable() - Enables the SOC_THERM over-current interrupt queue
1118 * to respond to over-current interrupts.
1125 d->irq_enable |= BIT(data->hwirq); in soctherm_oc_irq_enable()
1129 * soctherm_oc_irq_disable() - Disables overcurrent interrupt requests
1141 d->irq_enable &= ~BIT(data->hwirq); in soctherm_oc_irq_disable()
1150 * soctherm_oc_irq_map() - SOC_THERM interrupt request domain mapper
1169 struct soctherm_oc_irq_chip_data *data = h->host_data; in soctherm_oc_irq_map()
1172 irq_set_chip(virq, &data->irq_chip); in soctherm_oc_irq_map()
1178 * soctherm_irq_domain_xlate_twocell() - xlate for soctherm interrupts
1198 return -EINVAL; in soctherm_irq_domain_xlate_twocell()
1204 *out_hwirq = intspec[0] - 1; in soctherm_irq_domain_xlate_twocell()
1215 * soctherm_oc_int_init() - Initial enabling of the over
1223 * -ENOMEM (out of memory), or irq_base if the function failed to
1251 return -ENOMEM; in soctherm_oc_int_init()
1261 struct platform_device *pdev = s->private; in regs_show()
1263 const struct tegra_tsensor *tsensors = ts->soc->tsensors; in regs_show()
1264 const struct tegra_tsensor_group **ttgs = ts->soc->ttgs; in regs_show()
1268 seq_puts(s, "-----TSENSE (convert HW)-----\n"); in regs_show()
1270 for (i = 0; i < ts->soc->num_tsensors; i++) { in regs_show()
1271 r = readl(ts->regs + tsensors[i].base + SENSOR_CONFIG1); in regs_show()
1275 seq_printf(s, "En(%d) ", state); in regs_show()
1289 r = readl(ts->regs + tsensors[i].base + SENSOR_STATUS1); in regs_show()
1295 r = readl(ts->regs + tsensors[i].base + SENSOR_STATUS0); in regs_show()
1301 r = readl(ts->regs + tsensors[i].base + SENSOR_CONFIG0); in regs_show()
1313 r = readl(ts->regs + tsensors[i].base + SENSOR_CONFIG2); in regs_show()
1320 r = readl(ts->regs + SENSOR_PDIV); in regs_show()
1323 r = readl(ts->regs + SENSOR_HOTSPOT_OFF); in regs_show()
1327 seq_puts(s, "-----SOC_THERM-----\n"); in regs_show()
1329 r = readl(ts->regs + SENSOR_TEMP1); in regs_show()
1334 r = readl(ts->regs + SENSOR_TEMP2); in regs_show()
1340 for (i = 0; i < ts->soc->num_ttgs; i++) { in regs_show()
1341 seq_printf(s, "%s:\n", ttgs[i]->name); in regs_show()
1345 u16 off = ttgs[i]->thermctl_lvl0_offset; in regs_show()
1347 r = readl(ts->regs + THERMCTL_LVL_REG(off, level)); in regs_show()
1349 mask = ttgs[i]->thermctl_lvl0_up_thresh_mask; in regs_show()
1351 v = sign_extend32(state, ts->soc->bptt - 1); in regs_show()
1352 v *= ts->soc->thresh_grain; in regs_show()
1355 mask = ttgs[i]->thermctl_lvl0_dn_thresh_mask; in regs_show()
1357 v = sign_extend32(state, ts->soc->bptt - 1); in regs_show()
1358 v *= ts->soc->thresh_grain; in regs_show()
1363 seq_printf(s, "En(%d) ", state); in regs_show()
1392 state == 0 ? "LO" : in regs_show()
1398 r = readl(ts->regs + THERMCTL_STATS_CTL); in regs_show()
1400 r & STATS_CTL_EN_UP ? "En" : "--", in regs_show()
1401 r & STATS_CTL_EN_DN ? "En" : "--"); in regs_show()
1407 r = readl(ts->regs + THERMCTL_LVL_REG(off, level)); in regs_show()
1411 r = readl(ts->regs + THERMCTL_LVL_REG(off, level)); in regs_show()
1415 r = readl(ts->regs + THERMCTL_THERMTRIP_CTL); in regs_show()
1416 state = REG_GET_MASK(r, ttgs[0]->thermtrip_any_en_mask); in regs_show()
1417 seq_printf(s, "Thermtrip Any En(%d)\n", state); in regs_show()
1418 for (i = 0; i < ts->soc->num_ttgs; i++) { in regs_show()
1419 state = REG_GET_MASK(r, ttgs[i]->thermtrip_enable_mask); in regs_show()
1420 seq_printf(s, " %s En(%d) ", ttgs[i]->name, state); in regs_show()
1421 state = REG_GET_MASK(r, ttgs[i]->thermtrip_threshold_mask); in regs_show()
1422 state *= ts->soc->thresh_grain; in regs_show()
1426 r = readl(ts->regs + THROT_GLOBAL_CFG); in regs_show()
1430 seq_puts(s, "---------------------------------------------------\n"); in regs_show()
1431 r = readl(ts->regs + THROT_STATUS); in regs_show()
1439 r = readl(ts->regs + CPU_PSKIP_STATUS); in regs_show()
1440 if (ts->soc->use_ccroc) { in regs_show()
1464 tegra->debugfs_dir = root; in soctherm_debug_init()
1477 if (!tegra->clock_soctherm || !tegra->clock_tsensor) in soctherm_clk_enable()
1478 return -EINVAL; in soctherm_clk_enable()
1480 reset_control_assert(tegra->reset); in soctherm_clk_enable()
1483 err = clk_prepare_enable(tegra->clock_soctherm); in soctherm_clk_enable()
1485 reset_control_deassert(tegra->reset); in soctherm_clk_enable()
1489 err = clk_prepare_enable(tegra->clock_tsensor); in soctherm_clk_enable()
1491 clk_disable_unprepare(tegra->clock_soctherm); in soctherm_clk_enable()
1492 reset_control_deassert(tegra->reset); in soctherm_clk_enable()
1496 clk_disable_unprepare(tegra->clock_tsensor); in soctherm_clk_enable()
1497 clk_disable_unprepare(tegra->clock_soctherm); in soctherm_clk_enable()
1500 reset_control_deassert(tegra->reset); in soctherm_clk_enable()
1515 struct tegra_soctherm *ts = cdev->devdata; in throt_get_cdev_cur_state()
1518 r = readl(ts->regs + THROT_STATUS); in throt_get_cdev_cur_state()
1541 struct device *dev = &pdev->dev; in soctherm_thermtrips_parse()
1543 struct tsensor_group_thermtrips *tt = ts->soc->thermtrips; in soctherm_thermtrips_parse()
1544 const int max_num_prop = ts->soc->num_ttgs * 2; in soctherm_thermtrips_parse()
1549 return -ENOMEM; in soctherm_thermtrips_parse()
1551 n = of_property_count_u32_elems(dev->of_node, "nvidia,thermtrips"); in soctherm_thermtrips_parse()
1560 tlb = devm_kcalloc(&pdev->dev, max_num_prop, sizeof(u32), GFP_KERNEL); in soctherm_thermtrips_parse()
1562 return -ENOMEM; in soctherm_thermtrips_parse()
1563 ret = of_property_read_u32_array(dev->of_node, "nvidia,thermtrips", in soctherm_thermtrips_parse()
1589 if (of_property_read_bool(np_oc, "nvidia,polarity-active-low")) in soctherm_oc_cfg_parse()
1590 stc->oc_cfg.active_low = 1; in soctherm_oc_cfg_parse()
1592 stc->oc_cfg.active_low = 0; in soctherm_oc_cfg_parse()
1594 if (!of_property_read_u32(np_oc, "nvidia,count-threshold", &val)) { in soctherm_oc_cfg_parse()
1595 stc->oc_cfg.intr_en = 1; in soctherm_oc_cfg_parse()
1596 stc->oc_cfg.alarm_cnt_thresh = val; in soctherm_oc_cfg_parse()
1599 if (!of_property_read_u32(np_oc, "nvidia,throttle-period-us", &val)) in soctherm_oc_cfg_parse()
1600 stc->oc_cfg.throt_period = val; in soctherm_oc_cfg_parse()
1602 if (!of_property_read_u32(np_oc, "nvidia,alarm-filter", &val)) in soctherm_oc_cfg_parse()
1603 stc->oc_cfg.alarm_filter = val; in soctherm_oc_cfg_parse()
1606 stc->oc_cfg.mode = OC_THROTTLE_MODE_BRIEF; in soctherm_oc_cfg_parse()
1619 dev_err(dev, "throttle-cfg: %s: invalid priority\n", stc->name); in soctherm_throt_cfg_parse()
1620 return -EINVAL; in soctherm_throt_cfg_parse()
1622 stc->priority = val; in soctherm_throt_cfg_parse()
1624 ret = of_property_read_u32(np, ts->soc->use_ccroc ? in soctherm_throt_cfg_parse()
1625 "nvidia,cpu-throt-level" : in soctherm_throt_cfg_parse()
1626 "nvidia,cpu-throt-percent", &val); in soctherm_throt_cfg_parse()
1628 if (ts->soc->use_ccroc && in soctherm_throt_cfg_parse()
1630 stc->cpu_throt_level = val; in soctherm_throt_cfg_parse()
1631 else if (!ts->soc->use_ccroc && val <= 100) in soctherm_throt_cfg_parse()
1632 stc->cpu_throt_depth = val; in soctherm_throt_cfg_parse()
1639 ret = of_property_read_u32(np, "nvidia,gpu-throt-level", &val); in soctherm_throt_cfg_parse()
1641 stc->gpu_throt_level = val; in soctherm_throt_cfg_parse()
1648 dev_err(dev, "throttle-cfg: %s: no throt prop or invalid prop\n", in soctherm_throt_cfg_parse()
1649 stc->name); in soctherm_throt_cfg_parse()
1650 return -EINVAL; in soctherm_throt_cfg_parse()
1654 * soctherm_init_hw_throt_cdev() - Parse the HW throttle configurations
1660 struct device *dev = &pdev->dev; in soctherm_init_hw_throt_cdev()
1667 ts->throt_cfgs[i].name = throt_names[i]; in soctherm_init_hw_throt_cdev()
1668 ts->throt_cfgs[i].id = i; in soctherm_init_hw_throt_cdev()
1669 ts->throt_cfgs[i].init = false; in soctherm_init_hw_throt_cdev()
1672 np_stc = of_get_child_by_name(dev->of_node, "throttle-cfgs"); in soctherm_init_hw_throt_cdev()
1675 "throttle-cfg: no throttle-cfgs - not enabling\n"); in soctherm_init_hw_throt_cdev()
1684 name = np_stcc->name; in soctherm_init_hw_throt_cdev()
1688 "throttle-cfg: could not find %s\n", name); in soctherm_init_hw_throt_cdev()
1692 if (stc->init) { in soctherm_init_hw_throt_cdev()
1693 dev_err(dev, "throttle-cfg: %s: redefined!\n", name); in soctherm_init_hw_throt_cdev()
1702 if (stc->id >= THROTTLE_OC1) { in soctherm_init_hw_throt_cdev()
1704 stc->init = true; in soctherm_init_hw_throt_cdev()
1712 "throttle-cfg: %s: failed to register cooling device\n", in soctherm_init_hw_throt_cdev()
1716 stc->cdev = tcd; in soctherm_init_hw_throt_cdev()
1717 stc->init = true; in soctherm_init_hw_throt_cdev()
1726 * throttlectl_cpu_level_cfg() - programs CCROC NV_THERM level config
1730 * It's necessary to set up the CPU-local CCROC NV_THERM instance with
1733 * This function pre-programs the CCROC NV_THERM levels in terms of
1734 * pre-configured "Low", "Medium" or "Heavy" throttle levels which are
1774 * throttlectl_cpu_level_select() - program CPU pulse skipper config
1780 * data. This function is used on SoCs which have CPU-local pulse
1791 switch (ts->throt_cfgs[throt].cpu_throt_level) { in throttlectl_cpu_level_select()
1806 r = readl(ts->regs + THROT_PSKIP_CTRL(throt, THROTTLE_DEV_CPU)); in throttlectl_cpu_level_select()
1810 writel(r, ts->regs + THROT_PSKIP_CTRL(throt, THROTTLE_DEV_CPU)); in throttlectl_cpu_level_select()
1814 writel(r, ts->regs + THROT_PSKIP_RAMP(throt, THROTTLE_DEV_CPU)); in throttlectl_cpu_level_select()
1818 * throttlectl_cpu_mn() - program CPU pulse skipper configuration
1836 depth = ts->throt_cfgs[throt].cpu_throt_depth; in throttlectl_cpu_mn()
1839 r = readl(ts->regs + THROT_PSKIP_CTRL(throt, THROTTLE_DEV_CPU)); in throttlectl_cpu_mn()
1843 writel(r, ts->regs + THROT_PSKIP_CTRL(throt, THROTTLE_DEV_CPU)); in throttlectl_cpu_mn()
1845 r = readl(ts->regs + THROT_PSKIP_RAMP(throt, THROTTLE_DEV_CPU)); in throttlectl_cpu_mn()
1848 writel(r, ts->regs + THROT_PSKIP_RAMP(throt, THROTTLE_DEV_CPU)); in throttlectl_cpu_mn()
1852 * throttlectl_gpu_level_select() - selects throttling level for GPU
1857 * pre-configured "Low", "Medium" or "Heavy" throttle levels.
1866 level = ts->throt_cfgs[throt].gpu_throt_level; in throttlectl_gpu_level_select()
1868 r = readl(ts->regs + THROT_PSKIP_CTRL(throt, THROTTLE_DEV_GPU)); in throttlectl_gpu_level_select()
1871 writel(r, ts->regs + THROT_PSKIP_CTRL(throt, THROTTLE_DEV_GPU)); in throttlectl_gpu_level_select()
1878 struct soctherm_oc_cfg *oc = &ts->throt_cfgs[throt].oc_cfg; in soctherm_oc_cfg_program()
1880 if (oc->mode == OC_THROTTLE_MODE_DISABLED) in soctherm_oc_cfg_program()
1881 return -EINVAL; in soctherm_oc_cfg_program()
1884 r = REG_SET_MASK(r, OC1_CFG_THROTTLE_MODE_MASK, oc->mode); in soctherm_oc_cfg_program()
1885 r = REG_SET_MASK(r, OC1_CFG_ALARM_POLARITY_MASK, oc->active_low); in soctherm_oc_cfg_program()
1887 writel(r, ts->regs + ALARM_CFG(throt)); in soctherm_oc_cfg_program()
1888 writel(oc->throt_period, ts->regs + ALARM_THROTTLE_PERIOD(throt)); in soctherm_oc_cfg_program()
1889 writel(oc->alarm_cnt_thresh, ts->regs + ALARM_CNT_THRESHOLD(throt)); in soctherm_oc_cfg_program()
1890 writel(oc->alarm_filter, ts->regs + ALARM_FILTER(throt)); in soctherm_oc_cfg_program()
1891 soctherm_oc_intr_enable(ts, throt, oc->intr_en); in soctherm_oc_cfg_program()
1897 * soctherm_throttle_program() - programs pulse skippers' configuration
1908 struct soctherm_throt_cfg stc = ts->throt_cfgs[throt]; in soctherm_throttle_program()
1917 if (ts->soc->use_ccroc) in soctherm_throttle_program()
1925 writel(r, ts->regs + THROT_PRIORITY_CTRL(throt)); in soctherm_throttle_program()
1928 writel(r, ts->regs + THROT_DELAY_CTRL(throt)); in soctherm_throttle_program()
1930 r = readl(ts->regs + THROT_PRIORITY_LOCK); in soctherm_throttle_program()
1936 writel(r, ts->regs + THROT_PRIORITY_LOCK); in soctherm_throttle_program()
1946 if (ts->soc->use_ccroc) { in tegra_soctherm_throttle()
1957 if (ts->soc->use_ccroc) { in tegra_soctherm_throttle()
1964 writel(v, ts->regs + THROT_GLOBAL_CFG); in tegra_soctherm_throttle()
1966 v = readl(ts->clk_regs + CAR_SUPER_CCLKG_DIVIDER); in tegra_soctherm_throttle()
1968 writel(v, ts->clk_regs + CAR_SUPER_CCLKG_DIVIDER); in tegra_soctherm_throttle()
1974 writel(v, ts->regs + THERMCTL_STATS_CTL); in tegra_soctherm_throttle()
1980 struct device_node *np = pdev->dev.of_node; in soctherm_interrupts_init()
1985 dev_err(&pdev->dev, "soctherm_oc_int_init failed\n"); in soctherm_interrupts_init()
1989 tegra->thermal_irq = platform_get_irq(pdev, 0); in soctherm_interrupts_init()
1990 if (tegra->thermal_irq < 0) { in soctherm_interrupts_init()
1991 dev_dbg(&pdev->dev, "get 'thermal_irq' failed.\n"); in soctherm_interrupts_init()
1995 tegra->edp_irq = platform_get_irq(pdev, 1); in soctherm_interrupts_init()
1996 if (tegra->edp_irq < 0) { in soctherm_interrupts_init()
1997 dev_dbg(&pdev->dev, "get 'edp_irq' failed.\n"); in soctherm_interrupts_init()
2001 ret = devm_request_threaded_irq(&pdev->dev, in soctherm_interrupts_init()
2002 tegra->thermal_irq, in soctherm_interrupts_init()
2006 dev_name(&pdev->dev), in soctherm_interrupts_init()
2009 dev_err(&pdev->dev, "request_irq 'thermal_irq' failed.\n"); in soctherm_interrupts_init()
2013 ret = devm_request_threaded_irq(&pdev->dev, in soctherm_interrupts_init()
2014 tegra->edp_irq, in soctherm_interrupts_init()
2021 dev_err(&pdev->dev, "request_irq 'edp_irq' failed.\n"); in soctherm_interrupts_init()
2031 const struct tegra_tsensor_group **ttgs = tegra->soc->ttgs; in soctherm_init()
2036 for (i = 0; i < tegra->soc->num_tsensors; ++i) in soctherm_init()
2040 pdiv = readl(tegra->regs + SENSOR_PDIV); in soctherm_init()
2041 hotspot = readl(tegra->regs + SENSOR_HOTSPOT_OFF); in soctherm_init()
2042 for (i = 0; i < tegra->soc->num_ttgs; ++i) { in soctherm_init()
2043 pdiv = REG_SET_MASK(pdiv, ttgs[i]->pdiv_mask, in soctherm_init()
2044 ttgs[i]->pdiv); in soctherm_init()
2046 if (ttgs[i]->id == TEGRA124_SOCTHERM_SENSOR_PLLX) in soctherm_init()
2049 ttgs[i]->pllx_hotspot_mask, in soctherm_init()
2050 ttgs[i]->pllx_hotspot_diff); in soctherm_init()
2052 writel(pdiv, tegra->regs + SENSOR_PDIV); in soctherm_init()
2053 writel(hotspot, tegra->regs + SENSOR_HOTSPOT_OFF); in soctherm_init()
2056 tegra_soctherm_throttle(&pdev->dev); in soctherm_init()
2062 .compatible = "nvidia,tegra124-soctherm",
2068 .compatible = "nvidia,tegra132-soctherm",
2074 .compatible = "nvidia,tegra210-soctherm",
2092 match = of_match_node(tegra_soctherm_of_match, pdev->dev.of_node); in tegra_soctherm_probe()
2094 return -ENODEV; in tegra_soctherm_probe()
2096 soc = (struct tegra_soctherm_soc *)match->data; in tegra_soctherm_probe()
2097 if (soc->num_ttgs > TEGRA124_SOCTHERM_SENSOR_NUM) in tegra_soctherm_probe()
2098 return -EINVAL; in tegra_soctherm_probe()
2100 tegra = devm_kzalloc(&pdev->dev, sizeof(*tegra), GFP_KERNEL); in tegra_soctherm_probe()
2102 return -ENOMEM; in tegra_soctherm_probe()
2104 mutex_init(&tegra->thermctl_lock); in tegra_soctherm_probe()
2105 dev_set_drvdata(&pdev->dev, tegra); in tegra_soctherm_probe()
2107 tegra->soc = soc; in tegra_soctherm_probe()
2109 tegra->regs = devm_platform_ioremap_resource_byname(pdev, "soctherm-reg"); in tegra_soctherm_probe()
2110 if (IS_ERR(tegra->regs)) { in tegra_soctherm_probe()
2111 dev_err(&pdev->dev, "can't get soctherm registers"); in tegra_soctherm_probe()
2112 return PTR_ERR(tegra->regs); in tegra_soctherm_probe()
2115 if (!tegra->soc->use_ccroc) { in tegra_soctherm_probe()
2116 tegra->clk_regs = devm_platform_ioremap_resource_byname(pdev, "car-reg"); in tegra_soctherm_probe()
2117 if (IS_ERR(tegra->clk_regs)) { in tegra_soctherm_probe()
2118 dev_err(&pdev->dev, "can't get car clk registers"); in tegra_soctherm_probe()
2119 return PTR_ERR(tegra->clk_regs); in tegra_soctherm_probe()
2122 tegra->ccroc_regs = devm_platform_ioremap_resource_byname(pdev, "ccroc-reg"); in tegra_soctherm_probe()
2123 if (IS_ERR(tegra->ccroc_regs)) { in tegra_soctherm_probe()
2124 dev_err(&pdev->dev, "can't get ccroc registers"); in tegra_soctherm_probe()
2125 return PTR_ERR(tegra->ccroc_regs); in tegra_soctherm_probe()
2129 tegra->reset = devm_reset_control_get(&pdev->dev, "soctherm"); in tegra_soctherm_probe()
2130 if (IS_ERR(tegra->reset)) { in tegra_soctherm_probe()
2131 dev_err(&pdev->dev, "can't get soctherm reset\n"); in tegra_soctherm_probe()
2132 return PTR_ERR(tegra->reset); in tegra_soctherm_probe()
2135 tegra->clock_tsensor = devm_clk_get(&pdev->dev, "tsensor"); in tegra_soctherm_probe()
2136 if (IS_ERR(tegra->clock_tsensor)) { in tegra_soctherm_probe()
2137 dev_err(&pdev->dev, "can't get tsensor clock\n"); in tegra_soctherm_probe()
2138 return PTR_ERR(tegra->clock_tsensor); in tegra_soctherm_probe()
2141 tegra->clock_soctherm = devm_clk_get(&pdev->dev, "soctherm"); in tegra_soctherm_probe()
2142 if (IS_ERR(tegra->clock_soctherm)) { in tegra_soctherm_probe()
2143 dev_err(&pdev->dev, "can't get soctherm clock\n"); in tegra_soctherm_probe()
2144 return PTR_ERR(tegra->clock_soctherm); in tegra_soctherm_probe()
2147 tegra->calib = devm_kcalloc(&pdev->dev, in tegra_soctherm_probe()
2148 soc->num_tsensors, sizeof(u32), in tegra_soctherm_probe()
2150 if (!tegra->calib) in tegra_soctherm_probe()
2151 return -ENOMEM; in tegra_soctherm_probe()
2154 err = tegra_calc_shared_calib(soc->tfuse, &shared_calib); in tegra_soctherm_probe()
2159 for (i = 0; i < soc->num_tsensors; ++i) { in tegra_soctherm_probe()
2160 err = tegra_calc_tsensor_calib(&soc->tsensors[i], in tegra_soctherm_probe()
2162 &tegra->calib[i]); in tegra_soctherm_probe()
2167 tegra->thermctl_tzs = devm_kcalloc(&pdev->dev, in tegra_soctherm_probe()
2168 soc->num_ttgs, sizeof(z), in tegra_soctherm_probe()
2170 if (!tegra->thermctl_tzs) in tegra_soctherm_probe()
2171 return -ENOMEM; in tegra_soctherm_probe()
2183 for (i = 0; i < soc->num_ttgs; ++i) { in tegra_soctherm_probe()
2185 devm_kzalloc(&pdev->dev, sizeof(*zone), GFP_KERNEL); in tegra_soctherm_probe()
2187 err = -ENOMEM; in tegra_soctherm_probe()
2191 zone->reg = tegra->regs + soc->ttgs[i]->sensor_temp_offset; in tegra_soctherm_probe()
2192 zone->dev = &pdev->dev; in tegra_soctherm_probe()
2193 zone->sg = soc->ttgs[i]; in tegra_soctherm_probe()
2194 zone->ts = tegra; in tegra_soctherm_probe()
2196 z = devm_thermal_of_zone_register(&pdev->dev, in tegra_soctherm_probe()
2197 soc->ttgs[i]->id, zone, in tegra_soctherm_probe()
2201 dev_err(&pdev->dev, "failed to register sensor: %d\n", in tegra_soctherm_probe()
2206 zone->tz = z; in tegra_soctherm_probe()
2207 tegra->thermctl_tzs[soc->ttgs[i]->id] = z; in tegra_soctherm_probe()
2210 err = tegra_soctherm_set_hwtrips(&pdev->dev, soc->ttgs[i], z); in tegra_soctherm_probe()
2231 debugfs_remove_recursive(tegra->debugfs_dir); in tegra_soctherm_remove()
2251 struct tegra_soctherm_soc *soc = tegra->soc; in soctherm_resume()
2256 dev_err(&pdev->dev, in soctherm_resume()
2263 for (i = 0; i < soc->num_ttgs; ++i) { in soctherm_resume()
2266 tz = tegra->thermctl_tzs[soc->ttgs[i]->id]; in soctherm_resume()
2267 err = tegra_soctherm_set_hwtrips(dev, soc->ttgs[i], tz); in soctherm_resume()
2269 dev_err(&pdev->dev, in soctherm_resume()