113 #define CQSPI_REG_CONFIG			0x00  macro
291 	u32 reg = readl(cqspi->iobase + CQSPI_REG_CONFIG);  in cqspi_is_idle()
462 	reg = readl(reg_base + CQSPI_REG_CONFIG);  in cqspi_enable_dtr()
481 	writel(reg, reg_base + CQSPI_REG_CONFIG);  in cqspi_enable_dtr()
798 	reg = readl(cqspi->iobase + CQSPI_REG_CONFIG);  in cqspi_versal_indirect_read_dma()
800 	writel(reg, cqspi->iobase + CQSPI_REG_CONFIG);  in cqspi_versal_indirect_read_dma()
859 	reg = readl(cqspi->iobase + CQSPI_REG_CONFIG);  in cqspi_versal_indirect_read_dma()
861 	writel(reg, cqspi->iobase + CQSPI_REG_CONFIG);  in cqspi_versal_indirect_read_dma()
890 	reg = readl(cqspi->iobase + CQSPI_REG_CONFIG);  in cqspi_versal_indirect_read_dma()
892 	writel(reg, cqspi->iobase + CQSPI_REG_CONFIG);  in cqspi_versal_indirect_read_dma()
1048 	reg = readl(reg_base + CQSPI_REG_CONFIG);  in cqspi_chipselect()
1067 	writel(reg, reg_base + CQSPI_REG_CONFIG);  in cqspi_chipselect()
1122 	reg = readl(reg_base + CQSPI_REG_CONFIG);  in cqspi_config_baudrate_div()
1125 	writel(reg, reg_base + CQSPI_REG_CONFIG);  in cqspi_config_baudrate_div()
1156 	reg = readl(reg_base + CQSPI_REG_CONFIG);  in cqspi_controller_enable()
1163 	writel(reg, reg_base + CQSPI_REG_CONFIG);  in cqspi_controller_enable()
1485 		reg = readl(cqspi->iobase + CQSPI_REG_CONFIG);  in cqspi_controller_init()
1487 		writel(reg, cqspi->iobase + CQSPI_REG_CONFIG);  in cqspi_controller_init()
1492 		reg = readl(cqspi->iobase + CQSPI_REG_CONFIG);  in cqspi_controller_init()
1494 		writel(reg, cqspi->iobase + CQSPI_REG_CONFIG);  in cqspi_controller_init()