Lines Matching +full:lgm +full:- +full:clk
1 // SPDX-License-Identifier: GPL-2.0-only
5 // Copyright Altera Corporation (C) 2012-2014. All rights reserved.
6 // Copyright Intel Corporation (C) 2019-2020. All rights reserved.
7 // Copyright (C) 2020 Texas Instruments Incorporated - http://www.ti.com
9 #include <linux/clk.h>
12 #include <linux/dma-mapping.h>
16 #include <linux/firmware/xlnx-zynqmp.h>
31 #include <linux/spi/spi-mem.h>
34 #define CQSPI_NAME "cadence-qspi"
65 struct clk *clk; member
291 u32 reg = readl(cqspi->iobase + CQSPI_REG_CONFIG); in cqspi_is_idle()
298 u32 reg = readl(cqspi->iobase + CQSPI_REG_SDRAMLEVEL); in cqspi_get_rd_sram_level()
308 dma_status = readl(cqspi->iobase + in cqspi_get_versal_dma_status()
310 writel(dma_status, cqspi->iobase + in cqspi_get_versal_dma_status()
320 struct device *device = &cqspi->pdev->dev; in cqspi_irq_handler()
326 irq_status = readl(cqspi->iobase + CQSPI_REG_IRQSTATUS); in cqspi_irq_handler()
329 writel(irq_status, cqspi->iobase + CQSPI_REG_IRQSTATUS); in cqspi_irq_handler()
331 if (cqspi->use_dma_read && ddata && ddata->get_dma_status) { in cqspi_irq_handler()
332 if (ddata->get_dma_status(cqspi)) { in cqspi_irq_handler()
333 complete(&cqspi->transfer_complete); in cqspi_irq_handler()
338 else if (!cqspi->slow_sram) in cqspi_irq_handler()
344 complete(&cqspi->transfer_complete); in cqspi_irq_handler()
353 rdreg |= CQSPI_OP_WIDTH(op->cmd) << CQSPI_REG_RD_INSTR_TYPE_INSTR_LSB; in cqspi_calc_rdreg()
354 rdreg |= CQSPI_OP_WIDTH(op->addr) << CQSPI_REG_RD_INSTR_TYPE_ADDR_LSB; in cqspi_calc_rdreg()
355 rdreg |= CQSPI_OP_WIDTH(op->data) << CQSPI_REG_RD_INSTR_TYPE_DATA_LSB; in cqspi_calc_rdreg()
364 if (!op->dummy.nbytes) in cqspi_calc_dummy()
367 dummy_clk = op->dummy.nbytes * (8 / op->dummy.buswidth); in cqspi_calc_dummy()
368 if (op->cmd.dtr) in cqspi_calc_dummy()
397 dev_err(&cqspi->pdev->dev, in cqspi_wait_idle()
400 return -ETIMEDOUT; in cqspi_wait_idle()
409 void __iomem *reg_base = cqspi->iobase; in cqspi_exec_flash_cmd()
422 dev_err(&cqspi->pdev->dev, in cqspi_exec_flash_cmd()
435 struct cqspi_st *cqspi = f_pdata->cqspi; in cqspi_setup_opcode_ext()
436 void __iomem *reg_base = cqspi->iobase; in cqspi_setup_opcode_ext()
440 if (op->cmd.nbytes != 2) in cqspi_setup_opcode_ext()
441 return -EINVAL; in cqspi_setup_opcode_ext()
444 ext = op->cmd.opcode & 0xff; in cqspi_setup_opcode_ext()
457 struct cqspi_st *cqspi = f_pdata->cqspi; in cqspi_enable_dtr()
458 void __iomem *reg_base = cqspi->iobase; in cqspi_enable_dtr()
468 if (op->cmd.dtr) { in cqspi_enable_dtr()
489 struct cqspi_st *cqspi = f_pdata->cqspi; in cqspi_command_read()
490 void __iomem *reg_base = cqspi->iobase; in cqspi_command_read()
491 u8 *rxbuf = op->data.buf.in; in cqspi_command_read()
493 size_t n_rx = op->data.nbytes; in cqspi_command_read()
505 dev_err(&cqspi->pdev->dev, in cqspi_command_read()
508 return -EINVAL; in cqspi_command_read()
511 if (op->cmd.dtr) in cqspi_command_read()
512 opcode = op->cmd.opcode >> 8; in cqspi_command_read()
514 opcode = op->cmd.opcode; in cqspi_command_read()
523 return -EOPNOTSUPP; in cqspi_command_read()
532 reg |= (((n_rx - 1) & CQSPI_REG_CMDCTRL_RD_BYTES_MASK) in cqspi_command_read()
548 read_len = n_rx - read_len; in cqspi_command_read()
558 struct cqspi_st *cqspi = f_pdata->cqspi; in cqspi_command_write()
559 void __iomem *reg_base = cqspi->iobase; in cqspi_command_write()
561 const u8 *txbuf = op->data.buf.out; in cqspi_command_write()
562 size_t n_tx = op->data.nbytes; in cqspi_command_write()
573 dev_err(&cqspi->pdev->dev, in cqspi_command_write()
576 return -EINVAL; in cqspi_command_write()
582 if (op->cmd.dtr) in cqspi_command_write()
583 opcode = op->cmd.opcode >> 8; in cqspi_command_write()
585 opcode = op->cmd.opcode; in cqspi_command_write()
589 if (op->addr.nbytes) { in cqspi_command_write()
591 reg |= ((op->addr.nbytes - 1) & in cqspi_command_write()
595 writel(op->addr.val, reg_base + CQSPI_REG_CMDADDRESS); in cqspi_command_write()
600 reg |= ((n_tx - 1) & CQSPI_REG_CMDCTRL_WR_BYTES_MASK) in cqspi_command_write()
610 write_len = n_tx - 4; in cqspi_command_write()
622 struct cqspi_st *cqspi = f_pdata->cqspi; in cqspi_read_setup()
623 void __iomem *reg_base = cqspi->iobase; in cqspi_read_setup()
633 if (op->cmd.dtr) in cqspi_read_setup()
634 opcode = op->cmd.opcode >> 8; in cqspi_read_setup()
636 opcode = op->cmd.opcode; in cqspi_read_setup()
645 return -EOPNOTSUPP; in cqspi_read_setup()
656 reg |= (op->addr.nbytes - 1); in cqspi_read_setup()
665 struct cqspi_st *cqspi = f_pdata->cqspi; in cqspi_indirect_read_execute()
666 struct device *dev = &cqspi->pdev->dev; in cqspi_indirect_read_execute()
667 void __iomem *reg_base = cqspi->iobase; in cqspi_indirect_read_execute()
668 void __iomem *ahb_base = cqspi->ahb_base; in cqspi_indirect_read_execute()
689 if (!cqspi->slow_sram) in cqspi_indirect_read_execute()
694 reinit_completion(&cqspi->transfer_complete); in cqspi_indirect_read_execute()
699 if (!wait_for_completion_timeout(&cqspi->transfer_complete, in cqspi_indirect_read_execute()
701 ret = -ETIMEDOUT; in cqspi_indirect_read_execute()
707 if (cqspi->slow_sram) in cqspi_indirect_read_execute()
720 bytes_to_read *= cqspi->fifo_width; in cqspi_indirect_read_execute()
733 (rxbuf_end - rxbuf), in cqspi_indirect_read_execute()
737 remaining -= bytes_to_read; in cqspi_indirect_read_execute()
742 reinit_completion(&cqspi->transfer_complete); in cqspi_indirect_read_execute()
743 if (cqspi->slow_sram) in cqspi_indirect_read_execute()
778 struct cqspi_st *cqspi = f_pdata->cqspi; in cqspi_versal_indirect_read_dma()
779 struct device *dev = &cqspi->pdev->dev; in cqspi_versal_indirect_read_dma()
780 void __iomem *reg_base = cqspi->iobase; in cqspi_versal_indirect_read_dma()
789 bytes_to_dma = (n_rx - bytes_rem); in cqspi_versal_indirect_read_dma()
794 ret = zynqmp_pm_ospi_mux_select(cqspi->pd_dev_id, PM_OSPI_MUX_SEL_DMA); in cqspi_versal_indirect_read_dma()
798 reg = readl(cqspi->iobase + CQSPI_REG_CONFIG); in cqspi_versal_indirect_read_dma()
800 writel(reg, cqspi->iobase + CQSPI_REG_CONFIG); in cqspi_versal_indirect_read_dma()
805 return -ENOMEM; in cqspi_versal_indirect_read_dma()
830 writel(cqspi->trigger_address, reg_base + in cqspi_versal_indirect_read_dma()
843 reinit_completion(&cqspi->transfer_complete); in cqspi_versal_indirect_read_dma()
845 if (!wait_for_completion_timeout(&cqspi->transfer_complete, in cqspi_versal_indirect_read_dma()
847 ret = -ETIMEDOUT; in cqspi_versal_indirect_read_dma()
852 writel(0x0, cqspi->iobase + CQSPI_REG_VERSAL_DMA_DST_I_DIS); in cqspi_versal_indirect_read_dma()
856 cqspi->iobase + CQSPI_REG_INDIRECTRD); in cqspi_versal_indirect_read_dma()
859 reg = readl(cqspi->iobase + CQSPI_REG_CONFIG); in cqspi_versal_indirect_read_dma()
861 writel(reg, cqspi->iobase + CQSPI_REG_CONFIG); in cqspi_versal_indirect_read_dma()
863 ret = zynqmp_pm_ospi_mux_select(cqspi->pd_dev_id, in cqspi_versal_indirect_read_dma()
890 reg = readl(cqspi->iobase + CQSPI_REG_CONFIG); in cqspi_versal_indirect_read_dma()
892 writel(reg, cqspi->iobase + CQSPI_REG_CONFIG); in cqspi_versal_indirect_read_dma()
894 zynqmp_pm_ospi_mux_select(cqspi->pd_dev_id, PM_OSPI_MUX_SEL_LINEAR); in cqspi_versal_indirect_read_dma()
904 struct cqspi_st *cqspi = f_pdata->cqspi; in cqspi_write_setup()
905 void __iomem *reg_base = cqspi->iobase; in cqspi_write_setup()
912 if (op->cmd.dtr) in cqspi_write_setup()
913 opcode = op->cmd.opcode >> 8; in cqspi_write_setup()
915 opcode = op->cmd.opcode; in cqspi_write_setup()
919 reg |= CQSPI_OP_WIDTH(op->data) << CQSPI_REG_WR_INSTR_TYPE_DATA_LSB; in cqspi_write_setup()
920 reg |= CQSPI_OP_WIDTH(op->addr) << CQSPI_REG_WR_INSTR_TYPE_ADDR_LSB; in cqspi_write_setup()
928 * cypress Semper flash expect a 4-byte dummy address in the Read SR in cqspi_write_setup()
932 * command when doing auto-HW polling. So, disable write completion in cqspi_write_setup()
933 * polling on the controller's side. spinand and spi-nor will take in cqspi_write_setup()
936 if (cqspi->wr_completion) { in cqspi_write_setup()
944 reg |= (op->addr.nbytes - 1); in cqspi_write_setup()
953 struct cqspi_st *cqspi = f_pdata->cqspi; in cqspi_indirect_write_execute()
954 struct device *dev = &cqspi->pdev->dev; in cqspi_indirect_write_execute()
955 void __iomem *reg_base = cqspi->iobase; in cqspi_indirect_write_execute()
968 reinit_completion(&cqspi->transfer_complete); in cqspi_indirect_write_execute()
978 if (cqspi->wr_delay) in cqspi_indirect_write_execute()
979 ndelay(cqspi->wr_delay); in cqspi_indirect_write_execute()
989 iowrite32_rep(cqspi->ahb_base, txbuf, write_words); in cqspi_indirect_write_execute()
996 iowrite32(temp, cqspi->ahb_base); in cqspi_indirect_write_execute()
1000 if (!wait_for_completion_timeout(&cqspi->transfer_complete, in cqspi_indirect_write_execute()
1003 ret = -ETIMEDOUT; in cqspi_indirect_write_execute()
1007 remaining -= write_bytes; in cqspi_indirect_write_execute()
1010 reinit_completion(&cqspi->transfer_complete); in cqspi_indirect_write_execute()
1043 struct cqspi_st *cqspi = f_pdata->cqspi; in cqspi_chipselect()
1044 void __iomem *reg_base = cqspi->iobase; in cqspi_chipselect()
1045 unsigned int chip_select = f_pdata->cs; in cqspi_chipselect()
1049 if (cqspi->is_decoded_cs) { in cqspi_chipselect()
1083 struct cqspi_st *cqspi = f_pdata->cqspi; in cqspi_delay()
1084 void __iomem *iobase = cqspi->iobase; in cqspi_delay()
1085 const unsigned int ref_clk_hz = cqspi->master_ref_clk_hz; in cqspi_delay()
1091 tsclk = DIV_ROUND_UP(ref_clk_hz, cqspi->sclk); in cqspi_delay()
1093 tshsl = calculate_ticks_for_ns(ref_clk_hz, f_pdata->tshsl_ns); in cqspi_delay()
1098 tchsh = calculate_ticks_for_ns(ref_clk_hz, f_pdata->tchsh_ns); in cqspi_delay()
1099 tslch = calculate_ticks_for_ns(ref_clk_hz, f_pdata->tslch_ns); in cqspi_delay()
1100 tsd2d = calculate_ticks_for_ns(ref_clk_hz, f_pdata->tsd2d_ns); in cqspi_delay()
1115 const unsigned int ref_clk_hz = cqspi->master_ref_clk_hz; in cqspi_config_baudrate_div()
1116 void __iomem *reg_base = cqspi->iobase; in cqspi_config_baudrate_div()
1120 div = DIV_ROUND_UP(ref_clk_hz, 2 * cqspi->sclk) - 1; in cqspi_config_baudrate_div()
1132 void __iomem *reg_base = cqspi->iobase; in cqspi_readdata_capture()
1153 void __iomem *reg_base = cqspi->iobase; in cqspi_controller_enable()
1169 struct cqspi_st *cqspi = f_pdata->cqspi; in cqspi_configure()
1170 int switch_cs = (cqspi->current_cs != f_pdata->cs); in cqspi_configure()
1171 int switch_ck = (cqspi->sclk != sclk); in cqspi_configure()
1178 cqspi->current_cs = f_pdata->cs; in cqspi_configure()
1184 cqspi->sclk = sclk; in cqspi_configure()
1187 cqspi_readdata_capture(cqspi, !cqspi->rclk_en, in cqspi_configure()
1188 f_pdata->read_delay); in cqspi_configure()
1198 struct cqspi_st *cqspi = f_pdata->cqspi; in cqspi_write()
1199 loff_t to = op->addr.val; in cqspi_write()
1200 size_t len = op->data.nbytes; in cqspi_write()
1201 const u_char *buf = op->data.buf.out; in cqspi_write()
1209 * Some flashes like the Cypress Semper flash expect a dummy 4-byte in cqspi_write()
1216 if (!op->cmd.dtr && cqspi->use_direct_mode && in cqspi_write()
1217 ((to + len) <= cqspi->ahb_size)) { in cqspi_write()
1218 memcpy_toio(cqspi->ahb_base + to, buf, len); in cqspi_write()
1229 complete(&cqspi->rx_dma_complete); in cqspi_rx_dma_callback()
1235 struct cqspi_st *cqspi = f_pdata->cqspi; in cqspi_direct_read_execute()
1236 struct device *dev = &cqspi->pdev->dev; in cqspi_direct_read_execute()
1238 dma_addr_t dma_src = (dma_addr_t)cqspi->mmap_phys_base + from; in cqspi_direct_read_execute()
1245 if (!cqspi->rx_chan || !virt_addr_valid(buf)) { in cqspi_direct_read_execute()
1246 memcpy_fromio(buf, cqspi->ahb_base + from, len); in cqspi_direct_read_execute()
1250 ddev = cqspi->rx_chan->device->dev; in cqspi_direct_read_execute()
1254 return -ENOMEM; in cqspi_direct_read_execute()
1256 tx = dmaengine_prep_dma_memcpy(cqspi->rx_chan, dma_dst, dma_src, in cqspi_direct_read_execute()
1260 ret = -EIO; in cqspi_direct_read_execute()
1264 tx->callback = cqspi_rx_dma_callback; in cqspi_direct_read_execute()
1265 tx->callback_param = cqspi; in cqspi_direct_read_execute()
1266 cookie = tx->tx_submit(tx); in cqspi_direct_read_execute()
1267 reinit_completion(&cqspi->rx_dma_complete); in cqspi_direct_read_execute()
1272 ret = -EIO; in cqspi_direct_read_execute()
1276 dma_async_issue_pending(cqspi->rx_chan); in cqspi_direct_read_execute()
1277 if (!wait_for_completion_timeout(&cqspi->rx_dma_complete, in cqspi_direct_read_execute()
1279 dmaengine_terminate_sync(cqspi->rx_chan); in cqspi_direct_read_execute()
1281 ret = -ETIMEDOUT; in cqspi_direct_read_execute()
1294 struct cqspi_st *cqspi = f_pdata->cqspi; in cqspi_read()
1295 struct device *dev = &cqspi->pdev->dev; in cqspi_read()
1297 loff_t from = op->addr.val; in cqspi_read()
1298 size_t len = op->data.nbytes; in cqspi_read()
1299 u_char *buf = op->data.buf.in; in cqspi_read()
1309 if (cqspi->use_direct_mode && ((from + len) <= cqspi->ahb_size)) in cqspi_read()
1312 if (cqspi->use_dma_read && ddata && ddata->indirect_read_dma && in cqspi_read()
1314 return ddata->indirect_read_dma(f_pdata, buf, from, len); in cqspi_read()
1321 struct cqspi_st *cqspi = spi_master_get_devdata(mem->spi->master); in cqspi_mem_process()
1324 f_pdata = &cqspi->f_pdata[mem->spi->chip_select]; in cqspi_mem_process()
1325 cqspi_configure(f_pdata, mem->spi->max_speed_hz); in cqspi_mem_process()
1327 if (op->data.dir == SPI_MEM_DATA_IN && op->data.buf.in) { in cqspi_mem_process()
1328 if (!op->addr.nbytes) in cqspi_mem_process()
1334 if (!op->addr.nbytes || !op->data.buf.out) in cqspi_mem_process()
1346 dev_err(&mem->spi->dev, "operation failed with %d\n", ret); in cqspi_exec_mem_op()
1357 * op->dummy.dtr is required for converting nbytes into ncycles. in cqspi_supports_mem_op()
1360 all_true = op->cmd.dtr && in cqspi_supports_mem_op()
1361 (!op->addr.nbytes || op->addr.dtr) && in cqspi_supports_mem_op()
1362 (!op->dummy.nbytes || op->dummy.dtr) && in cqspi_supports_mem_op()
1363 (!op->data.nbytes || op->data.dtr); in cqspi_supports_mem_op()
1365 all_false = !op->cmd.dtr && !op->addr.dtr && !op->dummy.dtr && in cqspi_supports_mem_op()
1366 !op->data.dtr; in cqspi_supports_mem_op()
1369 /* Right now we only support 8-8-8 DTR mode. */ in cqspi_supports_mem_op()
1370 if (op->cmd.nbytes && op->cmd.buswidth != 8) in cqspi_supports_mem_op()
1372 if (op->addr.nbytes && op->addr.buswidth != 8) in cqspi_supports_mem_op()
1374 if (op->data.nbytes && op->data.buswidth != 8) in cqspi_supports_mem_op()
1388 if (of_property_read_u32(np, "cdns,read-delay", &f_pdata->read_delay)) { in cqspi_of_get_flash_pdata()
1389 dev_err(&pdev->dev, "couldn't determine read-delay\n"); in cqspi_of_get_flash_pdata()
1390 return -ENXIO; in cqspi_of_get_flash_pdata()
1393 if (of_property_read_u32(np, "cdns,tshsl-ns", &f_pdata->tshsl_ns)) { in cqspi_of_get_flash_pdata()
1394 dev_err(&pdev->dev, "couldn't determine tshsl-ns\n"); in cqspi_of_get_flash_pdata()
1395 return -ENXIO; in cqspi_of_get_flash_pdata()
1398 if (of_property_read_u32(np, "cdns,tsd2d-ns", &f_pdata->tsd2d_ns)) { in cqspi_of_get_flash_pdata()
1399 dev_err(&pdev->dev, "couldn't determine tsd2d-ns\n"); in cqspi_of_get_flash_pdata()
1400 return -ENXIO; in cqspi_of_get_flash_pdata()
1403 if (of_property_read_u32(np, "cdns,tchsh-ns", &f_pdata->tchsh_ns)) { in cqspi_of_get_flash_pdata()
1404 dev_err(&pdev->dev, "couldn't determine tchsh-ns\n"); in cqspi_of_get_flash_pdata()
1405 return -ENXIO; in cqspi_of_get_flash_pdata()
1408 if (of_property_read_u32(np, "cdns,tslch-ns", &f_pdata->tslch_ns)) { in cqspi_of_get_flash_pdata()
1409 dev_err(&pdev->dev, "couldn't determine tslch-ns\n"); in cqspi_of_get_flash_pdata()
1410 return -ENXIO; in cqspi_of_get_flash_pdata()
1413 if (of_property_read_u32(np, "spi-max-frequency", &f_pdata->clk_rate)) { in cqspi_of_get_flash_pdata()
1414 dev_err(&pdev->dev, "couldn't determine spi-max-frequency\n"); in cqspi_of_get_flash_pdata()
1415 return -ENXIO; in cqspi_of_get_flash_pdata()
1423 struct device *dev = &cqspi->pdev->dev; in cqspi_of_get_pdata()
1424 struct device_node *np = dev->of_node; in cqspi_of_get_pdata()
1427 cqspi->is_decoded_cs = of_property_read_bool(np, "cdns,is-decoded-cs"); in cqspi_of_get_pdata()
1429 if (of_property_read_u32(np, "cdns,fifo-depth", &cqspi->fifo_depth)) { in cqspi_of_get_pdata()
1430 dev_err(dev, "couldn't determine fifo-depth\n"); in cqspi_of_get_pdata()
1431 return -ENXIO; in cqspi_of_get_pdata()
1434 if (of_property_read_u32(np, "cdns,fifo-width", &cqspi->fifo_width)) { in cqspi_of_get_pdata()
1435 dev_err(dev, "couldn't determine fifo-width\n"); in cqspi_of_get_pdata()
1436 return -ENXIO; in cqspi_of_get_pdata()
1439 if (of_property_read_u32(np, "cdns,trigger-address", in cqspi_of_get_pdata()
1440 &cqspi->trigger_address)) { in cqspi_of_get_pdata()
1441 dev_err(dev, "couldn't determine trigger-address\n"); in cqspi_of_get_pdata()
1442 return -ENXIO; in cqspi_of_get_pdata()
1445 if (of_property_read_u32(np, "num-cs", &cqspi->num_chipselect)) in cqspi_of_get_pdata()
1446 cqspi->num_chipselect = CQSPI_MAX_CHIPSELECT; in cqspi_of_get_pdata()
1448 cqspi->rclk_en = of_property_read_bool(np, "cdns,rclk-en"); in cqspi_of_get_pdata()
1450 if (!of_property_read_u32_array(np, "power-domains", id, in cqspi_of_get_pdata()
1452 cqspi->pd_dev_id = id[1]; in cqspi_of_get_pdata()
1464 writel(0, cqspi->iobase + CQSPI_REG_REMAP); in cqspi_controller_init()
1467 writel(0, cqspi->iobase + CQSPI_REG_IRQMASK); in cqspi_controller_init()
1470 writel(cqspi->fifo_depth / 2, cqspi->iobase + CQSPI_REG_SRAMPARTITION); in cqspi_controller_init()
1473 writel(cqspi->trigger_address, in cqspi_controller_init()
1474 cqspi->iobase + CQSPI_REG_INDIRECTTRIGGER); in cqspi_controller_init()
1476 /* Program read watermark -- 1/2 of the FIFO. */ in cqspi_controller_init()
1477 writel(cqspi->fifo_depth * cqspi->fifo_width / 2, in cqspi_controller_init()
1478 cqspi->iobase + CQSPI_REG_INDIRECTRDWATERMARK); in cqspi_controller_init()
1479 /* Program write watermark -- 1/8 of the FIFO. */ in cqspi_controller_init()
1480 writel(cqspi->fifo_depth * cqspi->fifo_width / 8, in cqspi_controller_init()
1481 cqspi->iobase + CQSPI_REG_INDIRECTWRWATERMARK); in cqspi_controller_init()
1484 if (!cqspi->use_direct_mode) { in cqspi_controller_init()
1485 reg = readl(cqspi->iobase + CQSPI_REG_CONFIG); in cqspi_controller_init()
1487 writel(reg, cqspi->iobase + CQSPI_REG_CONFIG); in cqspi_controller_init()
1491 if (cqspi->use_dma_read) { in cqspi_controller_init()
1492 reg = readl(cqspi->iobase + CQSPI_REG_CONFIG); in cqspi_controller_init()
1494 writel(reg, cqspi->iobase + CQSPI_REG_CONFIG); in cqspi_controller_init()
1507 cqspi->rx_chan = dma_request_chan_by_mask(&mask); in cqspi_request_mmap_dma()
1508 if (IS_ERR(cqspi->rx_chan)) { in cqspi_request_mmap_dma()
1509 int ret = PTR_ERR(cqspi->rx_chan); in cqspi_request_mmap_dma()
1511 cqspi->rx_chan = NULL; in cqspi_request_mmap_dma()
1512 return dev_err_probe(&cqspi->pdev->dev, ret, "No Rx DMA available\n"); in cqspi_request_mmap_dma()
1514 init_completion(&cqspi->rx_dma_complete); in cqspi_request_mmap_dma()
1521 struct cqspi_st *cqspi = spi_master_get_devdata(mem->spi->master); in cqspi_get_name()
1522 struct device *dev = &cqspi->pdev->dev; in cqspi_get_name()
1524 return devm_kasprintf(dev, GFP_KERNEL, "%s.%d", dev_name(dev), mem->spi->chip_select); in cqspi_get_name()
1539 struct platform_device *pdev = cqspi->pdev; in cqspi_setup_flash()
1540 struct device *dev = &pdev->dev; in cqspi_setup_flash()
1541 struct device_node *np = dev->of_node; in cqspi_setup_flash()
1547 for_each_available_child_of_node(dev->of_node, np) { in cqspi_setup_flash()
1558 return -EINVAL; in cqspi_setup_flash()
1561 f_pdata = &cqspi->f_pdata[cs]; in cqspi_setup_flash()
1562 f_pdata->cqspi = cqspi; in cqspi_setup_flash()
1563 f_pdata->cs = cs; in cqspi_setup_flash()
1579 struct device *dev = &pdev->dev; in cqspi_probe()
1587 master = devm_spi_alloc_master(&pdev->dev, sizeof(*cqspi)); in cqspi_probe()
1589 dev_err(&pdev->dev, "spi_alloc_master failed\n"); in cqspi_probe()
1590 return -ENOMEM; in cqspi_probe()
1592 master->mode_bits = SPI_RX_QUAD | SPI_RX_DUAL; in cqspi_probe()
1593 master->mem_ops = &cqspi_mem_ops; in cqspi_probe()
1594 master->mem_caps = &cqspi_mem_caps; in cqspi_probe()
1595 master->dev.of_node = pdev->dev.of_node; in cqspi_probe()
1599 cqspi->pdev = pdev; in cqspi_probe()
1600 cqspi->master = master; in cqspi_probe()
1607 return -ENODEV; in cqspi_probe()
1611 cqspi->clk = devm_clk_get(dev, NULL); in cqspi_probe()
1612 if (IS_ERR(cqspi->clk)) { in cqspi_probe()
1614 ret = PTR_ERR(cqspi->clk); in cqspi_probe()
1620 cqspi->iobase = devm_ioremap_resource(dev, res); in cqspi_probe()
1621 if (IS_ERR(cqspi->iobase)) { in cqspi_probe()
1623 ret = PTR_ERR(cqspi->iobase); in cqspi_probe()
1629 cqspi->ahb_base = devm_ioremap_resource(dev, res_ahb); in cqspi_probe()
1630 if (IS_ERR(cqspi->ahb_base)) { in cqspi_probe()
1632 ret = PTR_ERR(cqspi->ahb_base); in cqspi_probe()
1635 cqspi->mmap_phys_base = (dma_addr_t)res_ahb->start; in cqspi_probe()
1636 cqspi->ahb_size = resource_size(res_ahb); in cqspi_probe()
1638 init_completion(&cqspi->transfer_complete); in cqspi_probe()
1643 return -ENXIO; in cqspi_probe()
1650 ret = clk_prepare_enable(cqspi->clk); in cqspi_probe()
1664 rstc_ocp = devm_reset_control_get_optional_exclusive(dev, "qspi-ocp"); in cqspi_probe()
1677 cqspi->master_ref_clk_hz = clk_get_rate(cqspi->clk); in cqspi_probe()
1678 master->max_speed_hz = cqspi->master_ref_clk_hz; in cqspi_probe()
1681 cqspi->wr_completion = true; in cqspi_probe()
1685 if (ddata->quirks & CQSPI_NEEDS_WR_DELAY) in cqspi_probe()
1686 cqspi->wr_delay = 50 * DIV_ROUND_UP(NSEC_PER_SEC, in cqspi_probe()
1687 cqspi->master_ref_clk_hz); in cqspi_probe()
1688 if (ddata->hwcaps_mask & CQSPI_SUPPORTS_OCTAL) in cqspi_probe()
1689 master->mode_bits |= SPI_RX_OCTAL | SPI_TX_OCTAL; in cqspi_probe()
1690 if (!(ddata->quirks & CQSPI_DISABLE_DAC_MODE)) in cqspi_probe()
1691 cqspi->use_direct_mode = true; in cqspi_probe()
1692 if (ddata->quirks & CQSPI_SUPPORT_EXTERNAL_DMA) in cqspi_probe()
1693 cqspi->use_dma_read = true; in cqspi_probe()
1694 if (ddata->quirks & CQSPI_NO_SUPPORT_WR_COMPLETION) in cqspi_probe()
1695 cqspi->wr_completion = false; in cqspi_probe()
1696 if (ddata->quirks & CQSPI_SLOW_SRAM) in cqspi_probe()
1697 cqspi->slow_sram = true; in cqspi_probe()
1699 if (of_device_is_compatible(pdev->dev.of_node, in cqspi_probe()
1700 "xlnx,versal-ospi-1.0")) in cqspi_probe()
1701 dma_set_mask(&pdev->dev, DMA_BIT_MASK(64)); in cqspi_probe()
1705 pdev->name, cqspi); in cqspi_probe()
1713 cqspi->current_cs = -1; in cqspi_probe()
1714 cqspi->sclk = 0; in cqspi_probe()
1716 master->num_chipselect = cqspi->num_chipselect; in cqspi_probe()
1724 if (cqspi->use_direct_mode) { in cqspi_probe()
1726 if (ret == -EPROBE_DEFER) in cqspi_probe()
1732 dev_err(&pdev->dev, "failed to register SPI ctlr %d\n", ret); in cqspi_probe()
1740 clk_disable_unprepare(cqspi->clk); in cqspi_probe()
1752 spi_unregister_master(cqspi->master); in cqspi_remove()
1755 if (cqspi->rx_chan) in cqspi_remove()
1756 dma_release_channel(cqspi->rx_chan); in cqspi_remove()
1758 clk_disable_unprepare(cqspi->clk); in cqspi_remove()
1760 pm_runtime_put_sync(&pdev->dev); in cqspi_remove()
1761 pm_runtime_disable(&pdev->dev); in cqspi_remove()
1825 .compatible = "cdns,qspi-nor",
1829 .compatible = "ti,k2g-qspi",
1833 .compatible = "ti,am654-ospi",
1837 .compatible = "intel,lgm-qspi",
1841 .compatible = "xlnx,versal-ospi-1.0",
1845 .compatible = "intel,socfpga-qspi",