33 #define TO_DMA_MASK(m)	(~((unsigned long long)m & 0xffffffff))
51 static int gvp11_xfer_mask = 0;
69 	static int scsi_alloc_out_of_range = 0;  in dma_setup()
88 		wh->dma_bounce_len = (scsi_pointer->this_residual + 511) & ~0x1ff;  in dma_setup()
103 				wh->dma_bounce_len = 0;  in dma_setup()
149 				wh->dma_bounce_len = 0;  in dma_setup()
180 	bank_mask = (~wh->dma_xfer_mask >> 18) & 0x01c0;  in dma_setup()
188 	return 0;  in dma_setup()
221 		wh->dma_bounce_len = 0;  in dma_stop()
267 	if (q & 0x08)	/* bit 3 should always be clear */  in check_wd33c93()
278 	if (*scmd_3393 != q)	/* and so should the image at 0x1f */  in check_wd33c93()
297 	*sasr_3393 = 0x1e;	/* this register is unimplemented */  in check_wd33c93()
299 	*sasr_3393 = 0x1e;  in check_wd33c93()
301 	*sasr_3393 = 0x1e;  in check_wd33c93()
303 	*sasr_3393 = 0x1e;  in check_wd33c93()
305 	if (qq != q || qq != 0xff)	/* should be read only, all 1's */  in check_wd33c93()
315 	if (qq != (~q & 0xff))	/* should be read/write */  in check_wd33c93()
319 	return 0;  in check_wd33c93()
347 	if (zorro_resource_len(z) != 0x10000)  in gvp11_probe()
371 	regs->secret1 = 0;  in gvp11_probe()
375 	regs->CNTR = 0;  in gvp11_probe()
376 	regs->BANK = 0;  in gvp11_probe()
394 	hdata->wh.no_sync = 0xff;  in gvp11_probe()
395 	hdata->wh.fast = 0;  in gvp11_probe()
402 	epc = *(unsigned short *)(ZTWO_VADDR(address) + 0x8000);  in gvp11_probe()
420 	return 0;  in gvp11_probe()
436 	hdata->regs->CNTR = 0;  in gvp11_remove()
450 	{ ZORRO_PROD_GVP_COMBO_030_R3_SCSI,	~0x00ffffff },
451 	{ ZORRO_PROD_GVP_SERIES_II,		~0x00ffffff },
452 	{ ZORRO_PROD_GVP_GFORCE_030_SCSI,	~0x01ffffff },
453 	{ ZORRO_PROD_GVP_A530_SCSI,		~0x01ffffff },
454 	{ ZORRO_PROD_GVP_COMBO_030_R4_SCSI,	~0x01ffffff },
455 	{ ZORRO_PROD_GVP_A1291,			~0x07ffffff },
456 	{ ZORRO_PROD_GVP_GFORCE_040_SCSI_1,	~0x07ffffff },
457 	{ 0 }