Lines Matching +full:0 +full:x80c00000
40 .tx_start_ptr = 0,
42 .tx_wrap_mask = 0,
44 .rx_wrap_mask = 0,
48 .ring_flag_sop = 0,
49 .ring_flag_eop = 0,
50 .ring_flag_xs_sop = 0,
51 .ring_flag_xs_eop = 0,
52 .ring_tx_start_ptr = 0,
53 .pfu_enabled = 0,
55 .msix_support = 0,
73 .tx_mask = 0x03FF0000,
74 .tx_wrap_mask = 0x07FF0000,
75 .rx_mask = 0x000003FF,
76 .rx_wrap_mask = 0x000007FF,
86 .sleep_cookie = 0,
89 .fw_dump_end = 0xcff,
90 .fw_dump_host_ready = 0xee,
91 .fw_dump_read_done = 0xfe,
92 .msix_support = 0,
102 .tx_rdptr = 0xC1A4,
103 .tx_wrptr = 0xC174,
104 .rx_rdptr = 0xC174,
105 .rx_wrptr = 0xC1A4,
110 .tx_mask = 0x0FFF0000,
111 .tx_wrap_mask = 0x1FFF0000,
112 .rx_mask = 0x00000FFF,
113 .rx_wrap_mask = 0x00001FFF,
123 .sleep_cookie = 0,
126 .fw_dump_end = 0xcff,
127 .fw_dump_host_ready = 0xcc,
128 .fw_dump_read_done = 0xdd,
129 .msix_support = 0,
133 {"ITCM", NULL, 0, 0xF0},
134 {"DTCM", NULL, 0, 0xF1},
135 {"SQRAM", NULL, 0, 0xF2},
136 {"IRAM", NULL, 0, 0xF3},
137 {"APU", NULL, 0, 0xF4},
138 {"CIU", NULL, 0, 0xF5},
139 {"ICU", NULL, 0, 0xF6},
140 {"MAC", NULL, 0, 0xF7},
144 {"DUMP", NULL, 0, 0xDD},
188 return 0; in mwifiex_pcie_probe_of()
207 return 0; in mwifiex_map_pci_memory()
229 return 0; in mwifiex_write_reg()
239 if (*data == 0xffffffff) in mwifiex_read_reg()
240 return 0xffffffff; in mwifiex_read_reg()
242 return 0; in mwifiex_read_reg()
253 return 0; in mwifiex_read_reg_byte()
271 "info: ACCESS_HW: sleep cookie=0x%x\n", in mwifiex_pcie_ok_to_access_hw()
301 return 0; in mwifiex_pcie_suspend()
321 return 0; in mwifiex_pcie_suspend()
340 return 0; in mwifiex_pcie_resume()
348 return 0; in mwifiex_pcie_resume()
357 return 0; in mwifiex_pcie_resume()
373 pr_debug("info: vendor=0x%4.04X device=0x%4.04X rev=%d\n", in mwifiex_pcie_probe()
412 return 0; in mwifiex_pcie_probe()
476 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
481 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
486 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
491 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
514 "%s: vendor=0x%4.04x device=0x%4.04x rev=%d Pre-FLR\n", in mwifiex_pcie_reset_prepare()
550 "%s: vendor=0x%4.04x device=0x%4.04x rev=%d Post-FLR\n", in mwifiex_pcie_reset_done()
594 int i = 0; in mwifiex_pcie_dev_wakeup_delay()
615 for (count = 0; count < max_delay_loop_cnt; count++) { in mwifiex_delay_for_sleep_cookie()
660 READ_ONCE(adapter->int_status) != 0, in mwifiex_pm_wakeup_card()
665 READ_ONCE(adapter->int_status) != 0, in mwifiex_pm_wakeup_card()
682 return 0; in mwifiex_pm_wakeup_card()
695 return 0; in mwifiex_pm_wakeup_card_complete()
708 0x00000000)) { in mwifiex_pcie_disable_host_int()
715 atomic_set(&adapter->tx_hw_pending, 0); in mwifiex_pcie_disable_host_int()
716 return 0; in mwifiex_pcie_disable_host_int()
742 return 0; in mwifiex_pcie_enable_host_int()
756 for (i = 0; i < MWIFIEX_MAX_TXRX_BD; i++) { in mwifiex_init_txq_ring()
762 memset(desc2, 0, sizeof(*desc2)); in mwifiex_init_txq_ring()
767 memset(desc, 0, sizeof(*desc)); in mwifiex_init_txq_ring()
771 return 0; in mwifiex_init_txq_ring()
788 for (i = 0; i < MWIFIEX_MAX_TXRX_BD; i++) { in mwifiex_init_rxq_ring()
820 desc2->offset = 0; in mwifiex_init_rxq_ring()
827 desc->flags = 0; in mwifiex_init_rxq_ring()
831 return 0; in mwifiex_init_rxq_ring()
846 for (i = 0; i < MWIFIEX_MAX_EVT_BD; i++) { in mwifiex_pcie_init_evt_ring()
877 desc->flags = 0; in mwifiex_pcie_init_evt_ring()
880 return 0; in mwifiex_pcie_init_evt_ring()
895 for (i = 0; i < MWIFIEX_MAX_TXRX_BD; i++) { in mwifiex_cleanup_txq_ring()
904 memset(desc2, 0, sizeof(*desc2)); in mwifiex_cleanup_txq_ring()
913 memset(desc, 0, sizeof(*desc)); in mwifiex_cleanup_txq_ring()
918 atomic_set(&adapter->tx_hw_pending, 0); in mwifiex_cleanup_txq_ring()
934 for (i = 0; i < MWIFIEX_MAX_TXRX_BD; i++) { in mwifiex_cleanup_rxq_ring()
943 memset(desc2, 0, sizeof(*desc2)); in mwifiex_cleanup_rxq_ring()
952 memset(desc, 0, sizeof(*desc)); in mwifiex_cleanup_rxq_ring()
970 for (i = 0; i < MWIFIEX_MAX_EVT_BD; i++) { in mwifiex_cleanup_evt_ring()
979 memset(desc, 0, sizeof(*desc)); in mwifiex_cleanup_evt_ring()
994 * pointer. The write pointer starts at 0 (zero) while the read pointer in mwifiex_pcie_create_txbd_ring()
997 card->txbd_wrptr = 0; in mwifiex_pcie_create_txbd_ring()
1000 card->txbd_rdptr = 0; in mwifiex_pcie_create_txbd_ring()
1047 card->txbd_ring_size = 0; in mwifiex_pcie_delete_txbd_ring()
1048 card->txbd_wrptr = 0; in mwifiex_pcie_delete_txbd_ring()
1049 card->txbd_rdptr = 0 | reg->tx_rollover_ind; in mwifiex_pcie_delete_txbd_ring()
1051 card->txbd_ring_pbase = 0; in mwifiex_pcie_delete_txbd_ring()
1053 return 0; in mwifiex_pcie_delete_txbd_ring()
1066 * pointer. The write pointer starts at 0 (zero) while the read pointer in mwifiex_pcie_create_rxbd_ring()
1069 card->rxbd_wrptr = 0; in mwifiex_pcie_create_rxbd_ring()
1116 card->rxbd_ring_size = 0; in mwifiex_pcie_delete_rxbd_ring()
1117 card->rxbd_wrptr = 0; in mwifiex_pcie_delete_rxbd_ring()
1118 card->rxbd_rdptr = 0 | reg->rx_rollover_ind; in mwifiex_pcie_delete_rxbd_ring()
1120 card->rxbd_ring_pbase = 0; in mwifiex_pcie_delete_rxbd_ring()
1122 return 0; in mwifiex_pcie_delete_rxbd_ring()
1135 * pointer. The write pointer starts at 0 (zero) while the read pointer in mwifiex_pcie_create_evtbd_ring()
1138 card->evtbd_wrptr = 0; in mwifiex_pcie_create_evtbd_ring()
1181 card->evtbd_wrptr = 0; in mwifiex_pcie_delete_evtbd_ring()
1182 card->evtbd_rdptr = 0 | reg->evt_rollover_ind; in mwifiex_pcie_delete_evtbd_ring()
1183 card->evtbd_ring_size = 0; in mwifiex_pcie_delete_evtbd_ring()
1185 card->evtbd_ring_pbase = 0; in mwifiex_pcie_delete_evtbd_ring()
1187 return 0; in mwifiex_pcie_delete_evtbd_ring()
1214 return 0; in mwifiex_pcie_alloc_cmdrsp_buf()
1225 return 0; in mwifiex_pcie_delete_cmdrsp_buf()
1242 return 0; in mwifiex_pcie_delete_cmdrsp_buf()
1266 mwifiex_dbg(adapter, INFO, "alloc_scook: sleep cookie=0x%x\n", *cookie); in mwifiex_pcie_alloc_sleep_cookie_buf()
1268 return 0; in mwifiex_pcie_alloc_sleep_cookie_buf()
1279 return 0; in mwifiex_pcie_delete_sleep_cookie_buf()
1290 return 0; in mwifiex_pcie_delete_sleep_cookie_buf()
1313 return 0; in mwifiex_clean_pcie_ring_buf()
1322 u32 wrdoneidx, rdptr, num_tx_buffs, unmap_count = 0; in mwifiex_pcie_send_data_complete()
1339 "SEND COMP: rdptr_prev=0x%x, rdptr=0x%x\n", in mwifiex_pcie_send_data_complete()
1363 mwifiex_write_data_complete(adapter, skb, 0, in mwifiex_pcie_send_data_complete()
1366 mwifiex_write_data_complete(adapter, skb, 0, 0); in mwifiex_pcie_send_data_complete()
1374 memset(desc2, 0, sizeof(*desc2)); in mwifiex_pcie_send_data_complete()
1377 memset(desc, 0, sizeof(*desc)); in mwifiex_pcie_send_data_complete()
1401 card->txbd_flush = 0; in mwifiex_pcie_send_data_complete()
1406 return 0; in mwifiex_pcie_send_data_complete()
1447 put_unaligned_le16((u16)skb->len, payload + 0); in mwifiex_pcie_send_data()
1464 desc2->offset = 0; in mwifiex_pcie_send_data()
1545 memset(desc2, 0, sizeof(*desc2)); in mwifiex_pcie_send_data()
1547 memset(desc, 0, sizeof(*desc)); in mwifiex_pcie_send_data()
1562 int ret = 0; in mwifiex_pcie_process_recv_data()
1648 desc2->offset = 0; in mwifiex_pcie_process_recv_data()
1654 desc->flags = 0; in mwifiex_pcie_process_recv_data()
1756 return 0; in mwifiex_pcie_send_boot_cmd()
1775 return 0; in mwifiex_pcie_init_fw_port()
1785 int ret = 0; in mwifiex_pcie_send_cmd()
1808 put_unaligned_le16((u16)skb->len, &payload[0]); in mwifiex_pcie_send_cmd()
1893 return 0; in mwifiex_pcie_send_cmd()
1904 int count = 0; in mwifiex_pcie_process_cmd_complete()
1974 if (mwifiex_write_reg(adapter, reg->cmdrsp_addr_lo, 0)) { in mwifiex_pcie_process_cmd_complete()
1981 if (mwifiex_write_reg(adapter, reg->cmdrsp_addr_hi, 0)) { in mwifiex_pcie_process_cmd_complete()
1988 return 0; in mwifiex_pcie_process_cmd_complete()
2007 return 0; in mwifiex_pcie_cmdrsp_complete()
2028 return 0; in mwifiex_pcie_process_event_ready()
2045 "info: EventReady: Initial <Rd: 0x%x, Wr: 0x%x>", in mwifiex_pcie_process_event_ready()
2052 __le16 data_len = 0; in mwifiex_pcie_process_event_ready()
2064 memset(desc, 0, sizeof(*desc)); in mwifiex_pcie_process_event_ready()
2100 return 0; in mwifiex_pcie_process_event_ready()
2111 int ret = 0; in mwifiex_pcie_event_complete()
2117 return 0; in mwifiex_pcie_event_complete()
2121 "event_complete: Invalid rdptr 0x%x\n", in mwifiex_pcie_event_complete()
2144 desc->flags = 0; in mwifiex_pcie_event_complete()
2159 "info: Updated <Rd: 0x%x, Wr: 0x%x>", in mwifiex_pcie_event_complete()
2184 * that is start with CMD1, return 0.
2190 u32 offset = 0, data_len, dnld_cmd; in mwifiex_extract_wifi_fw()
2191 int ret = 0; in mwifiex_extract_wifi_fw()
2223 return 0; in mwifiex_extract_wifi_fw()
2290 u32 offset = 0; in mwifiex_prog_fw_w_helper()
2292 u32 txlen, tx_blocks = 0, tries, len, val; in mwifiex_prog_fw_w_helper()
2293 u32 block_retry_cnt = 0; in mwifiex_prog_fw_w_helper()
2328 if (ret < 0) { in mwifiex_prog_fw_w_helper()
2339 u32 ireg_intr = 0; in mwifiex_prog_fw_w_helper()
2345 for (tries = 0; tries < MAX_POLL_TRIES; tries++) { in mwifiex_prog_fw_w_helper()
2370 if (len & BIT(0)) { in mwifiex_prog_fw_w_helper()
2381 "helper: len = 0x%04X, txlen = %d\n", in mwifiex_prog_fw_w_helper()
2383 len &= ~BIT(0); in mwifiex_prog_fw_w_helper()
2384 /* Setting this to 0 to resend from same offset */ in mwifiex_prog_fw_w_helper()
2385 txlen = 0; in mwifiex_prog_fw_w_helper()
2387 block_retry_cnt = 0; in mwifiex_prog_fw_w_helper()
2412 for (tries = 0; tries < MAX_POLL_TRIES; tries++) { in mwifiex_prog_fw_w_helper()
2445 ret = 0; in mwifiex_prog_fw_w_helper()
2458 int ret = 0; in mwifiex_check_fw_status()
2482 for (tries = 0; tries < poll_num; tries++) { in mwifiex_check_fw_status()
2487 ret = 0; in mwifiex_check_fw_status()
2495 ret = 0; in mwifiex_check_fw_status()
2511 u32 winner = 0; in mwifiex_check_winner_status()
2512 int ret = 0; in mwifiex_check_winner_status()
2549 if (card->msix_enable && msg_id >= 0) { in mwifiex_interrupt_status()
2558 if ((pcie_ireg == 0xFFFFFFFF) || !pcie_ireg) in mwifiex_interrupt_status()
2588 mwifiex_dbg(adapter, INTR, "ireg: 0x%08x\n", pcie_ireg); in mwifiex_interrupt_status()
2643 u32 pcie_ireg = 0; in mwifiex_process_int_status()
2652 adapter->int_status = 0; in mwifiex_process_int_status()
2664 if ((pcie_ireg != 0xFFFFFFFF) && (pcie_ireg)) { in mwifiex_process_int_status()
2719 return 0; in mwifiex_process_int_status()
2747 return 0; in mwifiex_pcie_host_to_card()
2766 return 0; in mwifiex_pcie_reg_dump()
2772 return 0; in mwifiex_pcie_reg_dump()
2777 for (i = 0; i < ARRAY_SIZE(pcie_scratch_reg); i++) { in mwifiex_pcie_reg_dump()
2779 ptr += sprintf(ptr, "reg:0x%x, value=0x%x\n", in mwifiex_pcie_reg_dump()
2812 for (tries = 0; tries < MAX_POLL_TRIES; tries++) { in mwifiex_pcie_rdwr_firmware()
2843 u8 idx, i, read_reg, doneflag = 0; in mwifiex_pcie_fw_dump()
2851 for (idx = 0; idx < adapter->num_mem_types; idx++) { in mwifiex_pcie_fw_dump()
2859 entry->mem_size = 0; in mwifiex_pcie_fw_dump()
2873 if (fw_dump_num == 0) in mwifiex_pcie_fw_dump()
2879 for (idx = 0; idx < dump_num; idx++) { in mwifiex_pcie_fw_dump()
2882 memory_size = 0; in mwifiex_pcie_fw_dump()
2883 if (fw_dump_num != 0) { in mwifiex_pcie_fw_dump()
2889 for (i = 0; i < 4; i++) { in mwifiex_pcie_fw_dump()
2898 if (memory_size == 0) { in mwifiex_pcie_fw_dump()
2910 "%s_SIZE=0x%x\n", entry->mem_name, memory_size); in mwifiex_pcie_fw_dump()
2957 "%s done: size=0x%tx\n", in mwifiex_pcie_fw_dump()
3062 return 0; in mwifiex_pcie_alloc_buffers()
3113 ret = pci_request_region(pdev, 0, DRV_NAME); in mwifiex_init_pcie()
3115 pr_err("req_reg(0) error\n"); in mwifiex_init_pcie()
3118 card->pci_mmap = pci_iomap(pdev, 0, 0); in mwifiex_init_pcie()
3120 pr_err("iomap(0) error\n"); in mwifiex_init_pcie()
3129 card->pci_mmap1 = pci_iomap(pdev, 2, 0); in mwifiex_init_pcie()
3146 return 0; in mwifiex_init_pcie()
3155 pci_release_region(pdev, 0); in mwifiex_init_pcie()
3191 if (mwifiex_write_reg(adapter, reg->drv_rdy, 0x00000000)) in mwifiex_cleanup_pcie()
3201 pci_release_region(pdev, 0); in mwifiex_cleanup_pcie()
3213 for (i = 0; i < MWIFIEX_NUM_MSIX_VECTORS; i++) in mwifiex_pcie_request_irq()
3218 for (i = 0; i < MWIFIEX_NUM_MSIX_VECTORS; i++) { in mwifiex_pcie_request_irq()
3223 mwifiex_pcie_interrupt, 0, in mwifiex_pcie_request_irq()
3233 for (j = 0; j < i; j++) in mwifiex_pcie_request_irq()
3240 return 0; in mwifiex_pcie_request_irq()
3245 if (pci_enable_msi(pdev) != 0) in mwifiex_pcie_request_irq()
3261 return 0; in mwifiex_pcie_request_irq()
3271 int revision_id = 0; in mwifiex_pcie_get_fw_name()
3280 mwifiex_write_reg(adapter, 0x0c58, 0x80c00000); in mwifiex_pcie_get_fw_name()
3281 mwifiex_read_reg(adapter, 0x0c58, &revision_id); in mwifiex_pcie_get_fw_name()
3282 revision_id &= 0xff00; in mwifiex_pcie_get_fw_name()
3297 mwifiex_read_reg(adapter, 0x8, &revision_id); in mwifiex_pcie_get_fw_name()
3298 mwifiex_read_reg(adapter, 0x0cd0, &version); in mwifiex_pcie_get_fw_name()
3299 mwifiex_read_reg(adapter, 0x0cd4, &magic); in mwifiex_pcie_get_fw_name()
3300 revision_id &= 0xff; in mwifiex_pcie_get_fw_name()
3301 version &= 0x7; in mwifiex_pcie_get_fw_name()
3302 magic &= 0xff; in mwifiex_pcie_get_fw_name()
3336 return 0; in mwifiex_register_dev()
3352 for (i = 0; i < MWIFIEX_NUM_MSIX_VECTORS; i++) in mwifiex_unregister_dev()
3355 for (i = 0; i < MWIFIEX_NUM_MSIX_VECTORS; i++) in mwifiex_unregister_dev()
3359 card->msix_enable = 0; in mwifiex_unregister_dev()
3398 if (mwifiex_write_reg(adapter, reg->drv_rdy, 0x00000000)) in mwifiex_pcie_down_dev()
3403 adapter->seq_num = 0; in mwifiex_pcie_down_dev()