33  * The 1-bit ECC hardware is supported, as well as the newer 4-bit ECC
85  * 1-bit hardware ECC ... context maintained for each core chipselect
104 	/* Reset ECC hardware */  in nand_davinci_hwctl_1bit()
109 	/* Restart ECC hardware */  in nand_davinci_hwctl_1bit()
118  * Read hardware ECC value and pack into three bytes
126 	/* invert so that erased block ecc is correct */  in nand_davinci_calculate_1bit()
147 			if ((diff >> (12 + 3)) < chip->ecc.size) {  in nand_davinci_correct_1bit()
154 			/* Single bit ECC error in the ECC itself,  in nand_davinci_correct_1bit()
169  * 4-bit hardware ECC ... context maintained over entire AEMIF
174  * Also, and specific to this hardware, it ECC-protects the "prepad"
175  * in the OOB ... while having ECC protection for parts of OOB would
177  * OOB without recomputing ECC.
186 	/* Reset ECC hardware */  in nand_davinci_hwctl_4bit()
191 	/* Start 4-bit ECC calculation for read/write */  in nand_davinci_hwctl_4bit()
202 /* Read raw ECC code after writing to NAND. */
214 /* Terminate read ECC; or return ECC (as bytes) of data written to NAND. */
222 	/* After a read, terminate ECC calculation by a dummy read  in nand_davinci_calculate_4bit()
223 	 * of some 4-bit ECC register.  ECC covers everything that  in nand_davinci_calculate_4bit()
232 	/* Pack eight raw 10-bit ecc values into ten bytes, making  in nand_davinci_calculate_4bit()
280 	/* Tell ECC controller about the expected ECC codes. */  in nand_davinci_correct_4bit()
311 	 * long as ECC_STATE reads less than 4. After that, ECC HW has entered  in nand_davinci_correct_4bit()
376 /* An ECC layout for using 4-bit ECC with small-page flash, storing
377  * ten ECC bytes plus the manufacturer's bad block marker byte, and
418 	.ecc = hwecc4_ooblayout_small_ecc,
460 			"ti,davinci-ecc-mode", &mode)) {  in nand_davinci_get_pdata()
469 			"ti,davinci-ecc-bits", &prop))  in nand_davinci_get_pdata()
482 		 * use of 4-bit hardware ECC with subpages and verified on  in nand_davinci_get_pdata()
517 	/* Use board-specific ECC config */  in davinci_nand_attach_chip()
518 	chip->ecc.engine_type = pdata->engine_type;  in davinci_nand_attach_chip()
519 	chip->ecc.placement = pdata->ecc_placement;  in davinci_nand_attach_chip()
521 	switch (chip->ecc.engine_type) {  in davinci_nand_attach_chip()
528 		 * This driver expects Hamming based ECC when engine_type is set  in davinci_nand_attach_chip()
529 		 * to NAND_ECC_ENGINE_TYPE_SOFT. Force ecc.algo to  in davinci_nand_attach_chip()
533 		chip->ecc.algo = NAND_ECC_ALGO_HAMMING;  in davinci_nand_attach_chip()
560 			chip->ecc.calculate = nand_davinci_calculate_4bit;  in davinci_nand_attach_chip()
561 			chip->ecc.correct = nand_davinci_correct_4bit;  in davinci_nand_attach_chip()
562 			chip->ecc.hwctl = nand_davinci_hwctl_4bit;  in davinci_nand_attach_chip()
563 			chip->ecc.bytes = 10;  in davinci_nand_attach_chip()
564 			chip->ecc.options = NAND_ECC_GENERIC_ERASED_CHECK;  in davinci_nand_attach_chip()
565 			chip->ecc.algo = NAND_ECC_ALGO_BCH;  in davinci_nand_attach_chip()
568 			 * Update ECC layout if needed ... for 1-bit HW ECC, the  in davinci_nand_attach_chip()
570 			 * are needed (for each 512 bytes). For 4-bit HW ECC,  in davinci_nand_attach_chip()
583 				chip->ecc.read_page = nand_read_page_hwecc_oob_first;  in davinci_nand_attach_chip()
588 			/* 1bit ecc hamming */  in davinci_nand_attach_chip()
589 			chip->ecc.calculate = nand_davinci_calculate_1bit;  in davinci_nand_attach_chip()
590 			chip->ecc.correct = nand_davinci_correct_1bit;  in davinci_nand_attach_chip()
591 			chip->ecc.hwctl = nand_davinci_hwctl_1bit;  in davinci_nand_attach_chip()
592 			chip->ecc.bytes = 3;  in davinci_nand_attach_chip()
593 			chip->ecc.algo = NAND_ECC_ALGO_HAMMING;  in davinci_nand_attach_chip()
595 		chip->ecc.size = 512;  in davinci_nand_attach_chip()
596 		chip->ecc.strength = pdata->ecc_bits;  in davinci_nand_attach_chip()
831 	if (chip->ecc.placement == NAND_ECC_PLACEMENT_INTERLEAVED)  in nand_davinci_remove()