22 #define OV2740_REG_CHIP_ID		0x300a
23 #define OV2740_CHIP_ID			0x2740
25 #define OV2740_REG_MODE_SELECT		0x0100
26 #define OV2740_MODE_STANDBY		0x00
27 #define OV2740_MODE_STREAMING		0x01
30 #define OV2740_REG_VTS			0x380e
31 #define OV2740_VTS_DEF			0x088a
32 #define OV2740_VTS_MIN			0x0460
33 #define OV2740_VTS_MAX			0x7fff
36 #define OV2740_REG_HTS			0x380c
39 #define OV2740_REG_EXPOSURE		0x3500
45 #define OV2740_REG_ANALOG_GAIN		0x3508
51 #define OV2740_REG_MWB_R_GAIN		0x500a
52 #define OV2740_REG_MWB_G_GAIN		0x500c
53 #define OV2740_REG_MWB_B_GAIN		0x500e
60 #define OV2740_REG_TEST_PATTERN		0x5040
65 #define OV2740_REG_GROUP_ACCESS		0x3208
66 #define OV2740_GROUP_HOLD_START		0x0
67 #define OV2740_GROUP_HOLD_END		0x10
68 #define OV2740_GROUP_HOLD_LAUNCH	0xa0
71 #define OV2740_REG_ISP_CTRL00		0x5000
73 #define OV2740_REG_ISP_CTRL01		0x5001
74 /* Customer Addresses: 0x7010 - 0x710F */
75 #define CUSTOMER_USE_OTP_SIZE		0x100
77 #define OV2740_REG_OTP_CUSTOMER		0x7010
128 	{0x0103, 0x01},
129 	{0x0302, 0x4b},
130 	{0x030d, 0x4b},
131 	{0x030e, 0x02},
132 	{0x030a, 0x01},
133 	{0x0312, 0x11},
137 	{0x3000, 0x00},
138 	{0x3018, 0x32},
139 	{0x3031, 0x0a},
140 	{0x3080, 0x08},
141 	{0x3083, 0xB4},
142 	{0x3103, 0x00},
143 	{0x3104, 0x01},
144 	{0x3106, 0x01},
145 	{0x3500, 0x00},
146 	{0x3501, 0x44},
147 	{0x3502, 0x40},
148 	{0x3503, 0x88},
149 	{0x3507, 0x00},
150 	{0x3508, 0x00},
151 	{0x3509, 0x80},
152 	{0x350c, 0x00},
153 	{0x350d, 0x80},
154 	{0x3510, 0x00},
155 	{0x3511, 0x00},
156 	{0x3512, 0x20},
157 	{0x3632, 0x00},
158 	{0x3633, 0x10},
159 	{0x3634, 0x10},
160 	{0x3635, 0x10},
161 	{0x3645, 0x13},
162 	{0x3646, 0x81},
163 	{0x3636, 0x10},
164 	{0x3651, 0x0a},
165 	{0x3656, 0x02},
166 	{0x3659, 0x04},
167 	{0x365a, 0xda},
168 	{0x365b, 0xa2},
169 	{0x365c, 0x04},
170 	{0x365d, 0x1d},
171 	{0x365e, 0x1a},
172 	{0x3662, 0xd7},
173 	{0x3667, 0x78},
174 	{0x3669, 0x0a},
175 	{0x366a, 0x92},
176 	{0x3700, 0x54},
177 	{0x3702, 0x10},
178 	{0x3706, 0x42},
179 	{0x3709, 0x30},
180 	{0x370b, 0xc2},
181 	{0x3714, 0x63},
182 	{0x3715, 0x01},
183 	{0x3716, 0x00},
184 	{0x371a, 0x3e},
185 	{0x3732, 0x0e},
186 	{0x3733, 0x10},
187 	{0x375f, 0x0e},
188 	{0x3768, 0x30},
189 	{0x3769, 0x44},
190 	{0x376a, 0x22},
191 	{0x377b, 0x20},
192 	{0x377c, 0x00},
193 	{0x377d, 0x0c},
194 	{0x3798, 0x00},
195 	{0x37a1, 0x55},
196 	{0x37a8, 0x6d},
197 	{0x37c2, 0x04},
198 	{0x37c5, 0x00},
199 	{0x37c8, 0x00},
200 	{0x3800, 0x00},
201 	{0x3801, 0x00},
202 	{0x3802, 0x00},
203 	{0x3803, 0x00},
204 	{0x3804, 0x07},
205 	{0x3805, 0x8f},
206 	{0x3806, 0x04},
207 	{0x3807, 0x47},
208 	{0x3808, 0x07},
209 	{0x3809, 0x88},
210 	{0x380a, 0x04},
211 	{0x380b, 0x40},
212 	{0x380c, 0x04},
213 	{0x380d, 0x38},
214 	{0x380e, 0x04},
215 	{0x380f, 0x60},
216 	{0x3810, 0x00},
217 	{0x3811, 0x04},
218 	{0x3812, 0x00},
219 	{0x3813, 0x04},
220 	{0x3814, 0x01},
221 	{0x3815, 0x01},
222 	{0x3820, 0x80},
223 	{0x3821, 0x46},
224 	{0x3822, 0x84},
225 	{0x3829, 0x00},
226 	{0x382a, 0x01},
227 	{0x382b, 0x01},
228 	{0x3830, 0x04},
229 	{0x3836, 0x01},
230 	{0x3837, 0x08},
231 	{0x3839, 0x01},
232 	{0x383a, 0x00},
233 	{0x383b, 0x08},
234 	{0x383c, 0x00},
235 	{0x3f0b, 0x00},
236 	{0x4001, 0x20},
237 	{0x4009, 0x07},
238 	{0x4003, 0x10},
239 	{0x4010, 0xe0},
240 	{0x4016, 0x00},
241 	{0x4017, 0x10},
242 	{0x4044, 0x02},
243 	{0x4304, 0x08},
244 	{0x4307, 0x30},
245 	{0x4320, 0x80},
246 	{0x4322, 0x00},
247 	{0x4323, 0x00},
248 	{0x4324, 0x00},
249 	{0x4325, 0x00},
250 	{0x4326, 0x00},
251 	{0x4327, 0x00},
252 	{0x4328, 0x00},
253 	{0x4329, 0x00},
254 	{0x432c, 0x03},
255 	{0x432d, 0x81},
256 	{0x4501, 0x84},
257 	{0x4502, 0x40},
258 	{0x4503, 0x18},
259 	{0x4504, 0x04},
260 	{0x4508, 0x02},
261 	{0x4601, 0x10},
262 	{0x4800, 0x00},
263 	{0x4816, 0x52},
264 	{0x4837, 0x16},
265 	{0x5000, 0x7f},
266 	{0x5001, 0x00},
267 	{0x5005, 0x38},
268 	{0x501e, 0x0d},
269 	{0x5040, 0x00},
270 	{0x5901, 0x00},
271 	{0x3800, 0x00},
272 	{0x3801, 0x00},
273 	{0x3802, 0x00},
274 	{0x3803, 0x00},
275 	{0x3804, 0x07},
276 	{0x3805, 0x8f},
277 	{0x3806, 0x04},
278 	{0x3807, 0x47},
279 	{0x3808, 0x07},
280 	{0x3809, 0x8c},
281 	{0x380a, 0x04},
282 	{0x380b, 0x44},
283 	{0x3810, 0x00},
284 	{0x3811, 0x00},
285 	{0x3812, 0x00},
286 	{0x3813, 0x01},
381 	u8 data_buf[4] = {0};  in ov2740_read_reg()
382 	int ret = 0;  in ov2740_read_reg()
388 	msgs[0].addr = client->addr;  in ov2740_read_reg()
389 	msgs[0].flags = 0;  in ov2740_read_reg()
390 	msgs[0].len = sizeof(addr_buf);  in ov2740_read_reg()
391 	msgs[0].buf = addr_buf;  in ov2740_read_reg()
399 		return ret < 0 ? ret : -EIO;  in ov2740_read_reg()
403 	return 0;  in ov2740_read_reg()
410 	int ret = 0;  in ov2740_write_reg()
420 		return ret < 0 ? ret : -EIO;  in ov2740_write_reg()
422 	return 0;  in ov2740_write_reg()
430 	int ret = 0;  in ov2740_write_reg_list()
432 	for (i = 0; i < r_list->num_of_regs; i++) {  in ov2740_write_reg_list()
437 					    "write reg 0x%4.4x return err = %d",  in ov2740_write_reg_list()
443 	return 0;  in ov2740_write_reg_list()
453 		return 0;  in ov2740_identify_module()
467 	return 0;  in ov2740_identify_module()
472 	int ret = 0;  in ov2740_update_digital_gain()
516 	int ret = 0;  in ov2740_set_ctrl()
531 		return 0;  in ov2740_set_ctrl()
579 	int ret = 0;  in ov2740_init_controls()
592 						   size - 1, 0,  in ov2740_init_controls()
599 					       V4L2_CID_PIXEL_RATE, 0,  in ov2740_init_controls()
632 				     0, 0, ov2740_test_pattern_menu);  in ov2740_init_controls()
638 	return 0;  in ov2740_init_controls()
654 	u32 isp_ctrl00 = 0;  in ov2740_load_otp_data()
655 	u32 isp_ctrl01 = 0;  in ov2740_load_otp_data()
662 		return 0;  in ov2740_load_otp_data()
708 	 * during the 20 ms period after streaming starts (0x100 = 0x01).  in ov2740_load_otp_data()
738 	return 0;  in ov2740_load_otp_data()
752 	int ret = 0;  in ov2740_start_streaming()
800 	int ret = 0;  in ov2740_set_stream()
803 		return 0;  in ov2740_set_stream()
808 		if (ret < 0) {  in ov2740_set_stream()
815 			enable = 0;  in ov2740_set_stream()
841 	return 0;  in ov2740_suspend()
848 	int ret = 0;  in ov2740_resume()
902 	return 0;  in ov2740_set_format()
921 	return 0;  in ov2740_get_format()
928 	if (code->index > 0)  in ov2740_enum_mbus_code()
933 	return 0;  in ov2740_enum_mbus_code()
951 	return 0;  in ov2740_enum_frame_size()
959 	ov2740_update_pad_format(&supported_modes[0],  in ov2740_open()
960 				 v4l2_subdev_get_try_format(sd, fh->state, 0));  in ov2740_open()
963 	return 0;  in ov2740_open()
1035 	for (i = 0; i < ARRAY_SIZE(link_freq_menu_items); i++) {  in ov2740_check_hwcfg()
1036 		for (j = 0; j < bus_cfg.nr_of_link_frequencies; j++) {  in ov2740_check_hwcfg()
1075 	int ret = 0;  in ov2740_nvmem_read()
1085 	if (ret < 0) {  in ov2740_nvmem_read()
1149 	int ret = 0;  in ov2740_probe()
1174 	ov2740->cur_mode = &supported_modes[0];  in ov2740_probe()
1193 	if (ret < 0) {  in ov2740_probe()
1209 	return 0;  in ov2740_probe()