42 			   ((*(sent) & 3) == 0) || ((*(sent) & 3) == 3))
49 #define lv2ent_fault(pent) ((*(pent) & 3) == 0)
55  * v5.0 introduced support for 36bit physical address space by shifting
59  * value (0 or 4).
62 #define SYSMMU_PG_ENT_SHIFT 0
67 	((0 << 15) | (0 << 10)), /* no access */
69 	((0 << 15) | (1 << 10)), /* IOMMU_WRITE not supported, use read/write */
70 	((0 << 15) | (1 << 10)), /* IOMMU_READ | IOMMU_WRITE */
73 	(0 << 4), /* no access */
81 	((0 << 9) | (0 << 4)), /* no access */
83 	((0 << 9) | (1 << 4)), /* IOMMU_WRITE not supported, use read/write */
84 	((0 << 9) | (1 << 4)), /* IOMMU_READ | IOMMU_WRITE */
87 	(0 << 2), /* no access */
120 #define lv2table_base(sent) (sect_to_phys(*(sent) & 0xFFFFFFC0))
127 #define CTRL_ENABLE	0x5
128 #define CTRL_BLOCK	0x7
129 #define CTRL_DISABLE	0x0
131 #define CFG_LRU		0x1
133 #define CFG_QOS(n)	((n & 0xF) << 7)
138 #define CTRL_VM_ENABLE			BIT(0)
144 #define REG_MMU_CTRL		0x000
145 #define REG_MMU_CFG		0x004
146 #define REG_MMU_STATUS		0x008
147 #define REG_MMU_VERSION		0x034
150 #define MMU_MIN_VER(val)	((val) & 0x7F)
153 #define MAKE_MMU_VER(maj, min)	((((maj) & 0xF) << 7) | ((min) & 0x7F))
156 #define REG_PAGE_FAULT_ADDR	0x024
157 #define REG_AW_FAULT_ADDR	0x028
158 #define REG_AR_FAULT_ADDR	0x02C
159 #define REG_DEFAULT_SLAVE_ADDR	0x030
162 #define REG_V5_FAULT_AR_VA	0x070
163 #define REG_V5_FAULT_AW_VA	0x080
166 #define REG_V7_CAPA0		0x870
167 #define REG_V7_CAPA1		0x874
168 #define REG_V7_CTRL_VM		0x8000
199 	{ 0, REG_PAGE_FAULT_ADDR, "PAGE", IOMMU_FAULT_READ },
210 	{ 0, REG_V5_FAULT_AR_VA, "AR PTW", IOMMU_FAULT_READ },
298 	.flush_all	= 0x0c,
299 	.flush_entry	= 0x10,
300 	.pt_base	= 0x14,
301 	.int_status	= 0x18,
302 	.int_clear	= 0x1c,
307 	.pt_base	= 0x0c,
308 	.flush_all	= 0x10,
309 	.flush_entry	= 0x14,
310 	.flush_range	= 0x18,
311 	.flush_start	= 0x20,
312 	.flush_end	= 0x24,
313 	.int_status	= 0x60,
314 	.int_clear	= 0x64,
319 	.pt_base	= 0x800c,
320 	.flush_all	= 0x8010,
321 	.flush_entry	= 0x8014,
322 	.flush_range	= 0x8018,
323 	.flush_start	= 0x8020,
324 	.flush_end	= 0x8024,
325 	.int_status	= 0x60,
326 	.int_clear	= 0x64,
344 	while ((i > 0) && !(readl(data->sfrbase + REG_MMU_STATUS) & 1))  in sysmmu_block()
357 	writel(0x1, SYSMMU_REG(data, flush_all));  in __sysmmu_tlb_invalidate()
366 		for (i = 0; i < num_inv; i++) {  in __sysmmu_tlb_invalidate_entry()
375 		writel(0x1, SYSMMU_REG(data, flush_range));  in __sysmmu_tlb_invalidate_entry()
431 	if (ver == 0x80000001u)  in __sysmmu_get_version()
432 		data->version = MAKE_MMU_VER(1, 0);  in __sysmmu_get_version()
496 	for (i = 0; i < n; i++, finfo++)  in exynos_sysmmu_irq()
510 	BUG_ON(ret != 0);  in exynos_sysmmu_irq()
531 	writel(0, data->sfrbase + REG_MMU_CFG);  in __sysmmu_disable()
599 			if (data->version >= MAKE_MMU_VER(5, 0))  in sysmmu_tlb_invalidate_flpdcache()
656 	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);  in exynos_sysmmu_probe()
661 	irq = platform_get_irq(pdev, 0);  in exynos_sysmmu_probe()
662 	if (irq <= 0)  in exynos_sysmmu_probe()
665 	ret = devm_request_irq(dev, irq, exynos_sysmmu_irq, 0,  in exynos_sysmmu_probe()
717 	if (PG_ENT_SHIFT < 0) {  in exynos_sysmmu_probe()
746 	return 0;  in exynos_sysmmu_probe()
770 	return 0;  in exynos_sysmmu_suspend()
788 	return 0;  in exynos_sysmmu_resume()
828 	BUG_ON(PG_ENT_SHIFT < 0 || !dma_dev);  in exynos_iommu_domain_alloc()
846 	for (i = 0; i < NUM_LV1ENTRIES; i++)  in exynos_iommu_domain_alloc()
860 	domain->domain.geometry.aperture_start = 0;  in exynos_iommu_domain_alloc()
861 	domain->domain.geometry.aperture_end   = ~0UL;  in exynos_iommu_domain_alloc()
889 		data->pgtable = 0;  in exynos_iommu_domain_free()
900 	for (i = 0; i < NUM_LV1ENTRIES; i++)  in exynos_iommu_domain_free()
939 		data->pgtable = 0;  in exynos_iommu_detach_device()
993 	return 0;  in exynos_iommu_attach_device()
1071 		kmem_cache_free(lv2table_kmem_cache, page_entry(sent, 0));  in lv1set_section()
1072 		*pgcnt = 0;  in lv1set_section()
1089 	return 0;  in lv1set_section()
1108 		for (i = 0; i < SPAGES_PER_LPAGE; i++, pent++) {  in lv2set_page()
1110 				if (i > 0)  in lv2set_page()
1111 					memset(pent - i, 0, sizeof(*pent) * i);  in lv2set_page()
1123 	return 0;  in lv2set_page()
1252 		exynos_iommu_set_pte(ent, 0);  in exynos_iommu_unmap()
1267 	memset(ent, 0, sizeof(*ent) * SPAGES_PER_LPAGE);  in exynos_iommu_unmap()
1285 	return 0;  in exynos_iommu_unmap()
1294 	phys_addr_t phys = 0;  in exynos_iommu_iova_to_phys()
1392 			return 0;  in exynos_iommu_of_xlate()
1397 	return 0;  in exynos_iommu_of_xlate()
1424 		return 0;  in exynos_iommu_init()
1429 				LV2TABLE_SIZE, LV2TABLE_SIZE, 0, NULL);  in exynos_iommu_init()
1449 	return 0;  in exynos_iommu_init()