Lines Matching +full:meson +full:- +full:hhi +full:- +full:sysctrl
1 // SPDX-License-Identifier: GPL-2.0
3 * Amlogic Meson Successive Approximation Register (SAR) A/D Converter
10 #include <linux/clk-provider.h>
15 #include <linux/nvmem-consumer.h>
96 (8 + (((_chan) - 2) * 3))
153 * and u-boot source served as reference). These only seem to be relevant on
306 regmap_read(priv->regmap, MESON_SAR_ADC_REG0, ®val); in meson_sar_adc_get_fifo_count()
317 tmp = div_s64((s64)val * priv->calibscale, MILLION) + priv->calibbias; in meson_sar_adc_calib_val()
319 return clamp(tmp, 0, (1 << priv->param->resolution) - 1); in meson_sar_adc_calib_val()
333 return regmap_read_poll_timeout_atomic(priv->regmap, MESON_SAR_ADC_REG0, val, in meson_sar_adc_wait_busy_clear()
343 struct device *dev = indio_dev->dev.parent; in meson_sar_adc_read_raw_sample()
346 if (!wait_for_completion_timeout(&priv->done, in meson_sar_adc_read_raw_sample()
348 return -ETIMEDOUT; in meson_sar_adc_read_raw_sample()
353 return -EINVAL; in meson_sar_adc_read_raw_sample()
356 regmap_read(priv->regmap, MESON_SAR_ADC_FIFO_RD, ®val); in meson_sar_adc_read_raw_sample()
358 if (fifo_chan != chan->address) { in meson_sar_adc_read_raw_sample()
360 fifo_chan, chan->address); in meson_sar_adc_read_raw_sample()
361 return -EINVAL; in meson_sar_adc_read_raw_sample()
365 fifo_val &= GENMASK(priv->param->resolution - 1, 0); in meson_sar_adc_read_raw_sample()
377 int val, address = chan->address; in meson_sar_adc_set_averaging()
380 regmap_update_bits(priv->regmap, MESON_SAR_ADC_AVG_CNTL, in meson_sar_adc_set_averaging()
385 regmap_update_bits(priv->regmap, MESON_SAR_ADC_AVG_CNTL, in meson_sar_adc_set_averaging()
401 regmap_update_bits(priv->regmap, MESON_SAR_ADC_CHAN_LIST, in meson_sar_adc_enable_channel()
406 chan->address); in meson_sar_adc_enable_channel()
407 regmap_update_bits(priv->regmap, MESON_SAR_ADC_CHAN_LIST, in meson_sar_adc_enable_channel()
411 chan->address); in meson_sar_adc_enable_channel()
412 regmap_update_bits(priv->regmap, MESON_SAR_ADC_DETECT_IDLE_SW, in meson_sar_adc_enable_channel()
417 chan->address); in meson_sar_adc_enable_channel()
418 regmap_update_bits(priv->regmap, MESON_SAR_ADC_DETECT_IDLE_SW, in meson_sar_adc_enable_channel()
422 if (chan->address == MESON_SAR_ADC_VOLTAGE_AND_TEMP_CHANNEL) { in meson_sar_adc_enable_channel()
423 if (chan->type == IIO_TEMP) in meson_sar_adc_enable_channel()
428 regmap_update_bits(priv->regmap, in meson_sar_adc_enable_channel()
441 regmap_update_bits(priv->regmap, MESON_SAR_ADC_REG3, in meson_sar_adc_set_chan7_mux()
451 reinit_completion(&priv->done); in meson_sar_adc_start_sample_engine()
453 regmap_update_bits(priv->regmap, MESON_SAR_ADC_REG0, in meson_sar_adc_start_sample_engine()
457 regmap_update_bits(priv->regmap, MESON_SAR_ADC_REG0, in meson_sar_adc_start_sample_engine()
461 regmap_update_bits(priv->regmap, MESON_SAR_ADC_REG0, in meson_sar_adc_start_sample_engine()
470 regmap_update_bits(priv->regmap, MESON_SAR_ADC_REG0, in meson_sar_adc_stop_sample_engine()
473 regmap_update_bits(priv->regmap, MESON_SAR_ADC_REG0, in meson_sar_adc_stop_sample_engine()
480 regmap_update_bits(priv->regmap, MESON_SAR_ADC_REG0, in meson_sar_adc_stop_sample_engine()
489 mutex_lock(&indio_dev->mlock); in meson_sar_adc_lock()
491 if (priv->param->has_bl30_integration) { in meson_sar_adc_lock()
493 regmap_update_bits(priv->regmap, MESON_SAR_ADC_DELAY, in meson_sar_adc_lock()
503 ret = regmap_read_poll_timeout_atomic(priv->regmap, MESON_SAR_ADC_DELAY, val, in meson_sar_adc_lock()
507 mutex_unlock(&indio_dev->mlock); in meson_sar_adc_lock()
519 if (priv->param->has_bl30_integration) in meson_sar_adc_unlock()
521 regmap_update_bits(priv->regmap, MESON_SAR_ADC_DELAY, in meson_sar_adc_unlock()
524 mutex_unlock(&indio_dev->mlock); in meson_sar_adc_unlock()
536 regmap_read(priv->regmap, MESON_SAR_ADC_FIFO_RD, &tmp); in meson_sar_adc_clear_fifo()
547 struct device *dev = indio_dev->dev.parent; in meson_sar_adc_get_sample()
550 if (chan->type == IIO_TEMP && !priv->temperature_sensor_calibrated) in meson_sar_adc_get_sample()
551 return -ENOTSUPP; in meson_sar_adc_get_sample()
572 chan->address, ret); in meson_sar_adc_get_sample()
584 struct device *dev = indio_dev->dev.parent; in meson_sar_adc_iio_info_read_raw()
598 if (chan->type == IIO_VOLTAGE) { in meson_sar_adc_iio_info_read_raw()
599 ret = regulator_get_voltage(priv->vref); in meson_sar_adc_iio_info_read_raw()
606 *val2 = priv->param->resolution; in meson_sar_adc_iio_info_read_raw()
608 } else if (chan->type == IIO_TEMP) { in meson_sar_adc_iio_info_read_raw()
610 *val = priv->param->temperature_multiplier; in meson_sar_adc_iio_info_read_raw()
611 *val2 = priv->param->temperature_divider; in meson_sar_adc_iio_info_read_raw()
618 return -EINVAL; in meson_sar_adc_iio_info_read_raw()
622 *val = priv->calibbias; in meson_sar_adc_iio_info_read_raw()
626 *val = priv->calibscale / MILLION; in meson_sar_adc_iio_info_read_raw()
627 *val2 = priv->calibscale % MILLION; in meson_sar_adc_iio_info_read_raw()
632 priv->param->temperature_divider, in meson_sar_adc_iio_info_read_raw()
633 priv->param->temperature_multiplier); in meson_sar_adc_iio_info_read_raw()
634 *val -= priv->temperature_sensor_adc_val; in meson_sar_adc_iio_info_read_raw()
638 return -EINVAL; in meson_sar_adc_iio_info_read_raw()
646 struct device *dev = indio_dev->dev.parent; in meson_sar_adc_clk_init()
652 return -ENOMEM; in meson_sar_adc_clk_init()
656 clk_parents[0] = __clk_get_name(priv->clkin); in meson_sar_adc_clk_init()
660 priv->clk_div.reg = base + MESON_SAR_ADC_REG3; in meson_sar_adc_clk_init()
661 priv->clk_div.shift = MESON_SAR_ADC_REG3_ADC_CLK_DIV_SHIFT; in meson_sar_adc_clk_init()
662 priv->clk_div.width = MESON_SAR_ADC_REG3_ADC_CLK_DIV_WIDTH; in meson_sar_adc_clk_init()
663 priv->clk_div.hw.init = &init; in meson_sar_adc_clk_init()
664 priv->clk_div.flags = 0; in meson_sar_adc_clk_init()
666 priv->adc_div_clk = devm_clk_register(dev, &priv->clk_div.hw); in meson_sar_adc_clk_init()
667 if (WARN_ON(IS_ERR(priv->adc_div_clk))) in meson_sar_adc_clk_init()
668 return PTR_ERR(priv->adc_div_clk); in meson_sar_adc_clk_init()
672 return -ENOMEM; in meson_sar_adc_clk_init()
676 clk_parents[0] = __clk_get_name(priv->adc_div_clk); in meson_sar_adc_clk_init()
680 priv->clk_gate.reg = base + MESON_SAR_ADC_REG3; in meson_sar_adc_clk_init()
681 priv->clk_gate.bit_idx = __ffs(MESON_SAR_ADC_REG3_CLK_EN); in meson_sar_adc_clk_init()
682 priv->clk_gate.hw.init = &init; in meson_sar_adc_clk_init()
684 priv->adc_clk = devm_clk_register(dev, &priv->clk_gate.hw); in meson_sar_adc_clk_init()
685 if (WARN_ON(IS_ERR(priv->adc_clk))) in meson_sar_adc_clk_init()
686 return PTR_ERR(priv->adc_clk); in meson_sar_adc_clk_init()
695 struct device *dev = indio_dev->dev.parent; in meson_sar_adc_temp_sensor_init()
706 * was passed via nvmem-cells. in meson_sar_adc_temp_sensor_init()
708 if (ret == -ENODEV) in meson_sar_adc_temp_sensor_init()
714 priv->tsc_regmap = syscon_regmap_lookup_by_phandle(dev->of_node, "amlogic,hhi-sysctrl"); in meson_sar_adc_temp_sensor_init()
715 if (IS_ERR(priv->tsc_regmap)) in meson_sar_adc_temp_sensor_init()
716 return dev_err_probe(dev, PTR_ERR(priv->tsc_regmap), in meson_sar_adc_temp_sensor_init()
717 "failed to get amlogic,hhi-sysctrl regmap\n"); in meson_sar_adc_temp_sensor_init()
725 return dev_err_probe(dev, -EINVAL, "invalid read size of temperature_calib cell\n"); in meson_sar_adc_temp_sensor_init()
728 trimming_bits = priv->param->temperature_trimming_bits; in meson_sar_adc_temp_sensor_init()
729 trimming_mask = BIT(trimming_bits) - 1; in meson_sar_adc_temp_sensor_init()
731 priv->temperature_sensor_calibrated = in meson_sar_adc_temp_sensor_init()
733 priv->temperature_sensor_coefficient = buf[2] & trimming_mask; in meson_sar_adc_temp_sensor_init()
738 priv->temperature_sensor_adc_val = buf[2]; in meson_sar_adc_temp_sensor_init()
739 priv->temperature_sensor_adc_val |= upper_adc_val << BITS_PER_BYTE; in meson_sar_adc_temp_sensor_init()
740 priv->temperature_sensor_adc_val >>= trimming_bits; in meson_sar_adc_temp_sensor_init()
750 struct device *dev = indio_dev->dev.parent; in meson_sar_adc_init()
759 if (priv->param->has_bl30_integration) { in meson_sar_adc_init()
765 regmap_read(priv->regmap, MESON_SAR_ADC_REG3, ®val); in meson_sar_adc_init()
776 regmap_update_bits(priv->regmap, MESON_SAR_ADC_REG0, in meson_sar_adc_init()
780 regmap_write(priv->regmap, MESON_SAR_ADC_CHAN_LIST, 0x0); in meson_sar_adc_init()
782 regmap_update_bits(priv->regmap, MESON_SAR_ADC_REG3, in meson_sar_adc_init()
784 regmap_update_bits(priv->regmap, MESON_SAR_ADC_REG3, in meson_sar_adc_init()
789 regmap_update_bits(priv->regmap, MESON_SAR_ADC_DELAY, in meson_sar_adc_init()
793 regmap_update_bits(priv->regmap, MESON_SAR_ADC_DELAY, in meson_sar_adc_init()
799 regmap_update_bits(priv->regmap, MESON_SAR_ADC_DELAY, in meson_sar_adc_init()
803 regmap_update_bits(priv->regmap, MESON_SAR_ADC_DELAY, in meson_sar_adc_init()
813 regmap_update_bits(priv->regmap, MESON_SAR_ADC_CHAN_10_SW, in meson_sar_adc_init()
817 regmap_update_bits(priv->regmap, MESON_SAR_ADC_CHAN_10_SW, in meson_sar_adc_init()
832 regmap_write(priv->regmap, MESON_SAR_ADC_AUX_SW, regval); in meson_sar_adc_init()
834 if (priv->temperature_sensor_calibrated) { in meson_sar_adc_init()
835 regmap_update_bits(priv->regmap, MESON_SAR_ADC_DELTA_10, in meson_sar_adc_init()
838 regmap_update_bits(priv->regmap, MESON_SAR_ADC_DELTA_10, in meson_sar_adc_init()
847 priv->temperature_sensor_coefficient); in meson_sar_adc_init()
848 regmap_update_bits(priv->regmap, MESON_SAR_ADC_DELTA_10, in meson_sar_adc_init()
851 if (priv->param->temperature_trimming_bits == 5) { in meson_sar_adc_init()
852 if (priv->temperature_sensor_coefficient & BIT(4)) in meson_sar_adc_init()
859 * of the TSC is located in the HHI register area. in meson_sar_adc_init()
861 regmap_update_bits(priv->tsc_regmap, in meson_sar_adc_init()
867 regmap_update_bits(priv->regmap, MESON_SAR_ADC_DELTA_10, in meson_sar_adc_init()
869 regmap_update_bits(priv->regmap, MESON_SAR_ADC_DELTA_10, in meson_sar_adc_init()
873 ret = clk_set_parent(priv->adc_sel_clk, priv->clkin); in meson_sar_adc_init()
877 ret = clk_set_rate(priv->adc_clk, priv->param->clock_rate); in meson_sar_adc_init()
887 const struct meson_sar_adc_param *param = priv->param; in meson_sar_adc_set_bandgap()
890 if (param->bandgap_reg == MESON_SAR_ADC_REG11) in meson_sar_adc_set_bandgap()
895 regmap_update_bits(priv->regmap, param->bandgap_reg, enable_mask, in meson_sar_adc_set_bandgap()
902 struct device *dev = indio_dev->dev.parent; in meson_sar_adc_hw_enable()
910 ret = regulator_enable(priv->vref); in meson_sar_adc_hw_enable()
916 ret = clk_prepare_enable(priv->core_clk); in meson_sar_adc_hw_enable()
923 regmap_update_bits(priv->regmap, MESON_SAR_ADC_REG0, in meson_sar_adc_hw_enable()
928 regmap_update_bits(priv->regmap, MESON_SAR_ADC_REG3, in meson_sar_adc_hw_enable()
934 ret = clk_prepare_enable(priv->adc_clk); in meson_sar_adc_hw_enable()
945 regmap_update_bits(priv->regmap, MESON_SAR_ADC_REG3, in meson_sar_adc_hw_enable()
948 clk_disable_unprepare(priv->core_clk); in meson_sar_adc_hw_enable()
950 regulator_disable(priv->vref); in meson_sar_adc_hw_enable()
966 clk_disable_unprepare(priv->adc_clk); in meson_sar_adc_hw_disable()
968 regmap_update_bits(priv->regmap, MESON_SAR_ADC_REG3, in meson_sar_adc_hw_disable()
973 clk_disable_unprepare(priv->core_clk); in meson_sar_adc_hw_disable()
975 regulator_disable(priv->vref); in meson_sar_adc_hw_disable()
989 regmap_read(priv->regmap, MESON_SAR_ADC_REG0, ®val); in meson_sar_adc_irq()
996 complete(&priv->done); in meson_sar_adc_irq()
1007 nominal0 = (1 << priv->param->resolution) / 4; in meson_sar_adc_calib()
1008 nominal1 = (1 << priv->param->resolution) * 3 / 4; in meson_sar_adc_calib()
1013 &indio_dev->channels[7], in meson_sar_adc_calib()
1021 &indio_dev->channels[7], in meson_sar_adc_calib()
1027 ret = -EINVAL; in meson_sar_adc_calib()
1031 priv->calibscale = div_s64((nominal1 - nominal0) * (s64)MILLION, in meson_sar_adc_calib()
1032 value1 - value0); in meson_sar_adc_calib()
1033 priv->calibbias = nominal0 - div_s64((s64)value0 * priv->calibscale, in meson_sar_adc_calib()
1094 .name = "meson-meson8-saradc",
1099 .name = "meson-meson8b-saradc",
1104 .name = "meson-meson8m2-saradc",
1109 .name = "meson-gxbb-saradc",
1114 .name = "meson-gxl-saradc",
1119 .name = "meson-gxm-saradc",
1124 .name = "meson-axg-saradc",
1129 .name = "meson-g12a-saradc",
1134 .compatible = "amlogic,meson8-saradc",
1137 .compatible = "amlogic,meson8b-saradc",
1140 .compatible = "amlogic,meson8m2-saradc",
1143 .compatible = "amlogic,meson-gxbb-saradc",
1146 .compatible = "amlogic,meson-gxl-saradc",
1149 .compatible = "amlogic,meson-gxm-saradc",
1152 .compatible = "amlogic,meson-axg-saradc",
1155 .compatible = "amlogic,meson-g12a-saradc",
1166 struct device *dev = &pdev->dev; in meson_sar_adc_probe()
1173 return dev_err_probe(dev, -ENOMEM, "failed allocating iio device\n"); in meson_sar_adc_probe()
1176 init_completion(&priv->done); in meson_sar_adc_probe()
1180 return dev_err_probe(dev, -ENODEV, "failed to get match data\n"); in meson_sar_adc_probe()
1182 priv->param = match_data->param; in meson_sar_adc_probe()
1184 indio_dev->name = match_data->name; in meson_sar_adc_probe()
1185 indio_dev->modes = INDIO_DIRECT_MODE; in meson_sar_adc_probe()
1186 indio_dev->info = &meson_sar_adc_iio_info; in meson_sar_adc_probe()
1192 priv->regmap = devm_regmap_init_mmio(dev, base, priv->param->regmap_config); in meson_sar_adc_probe()
1193 if (IS_ERR(priv->regmap)) in meson_sar_adc_probe()
1194 return PTR_ERR(priv->regmap); in meson_sar_adc_probe()
1196 irq = irq_of_parse_and_map(dev->of_node, 0); in meson_sar_adc_probe()
1198 return -EINVAL; in meson_sar_adc_probe()
1204 priv->clkin = devm_clk_get(dev, "clkin"); in meson_sar_adc_probe()
1205 if (IS_ERR(priv->clkin)) in meson_sar_adc_probe()
1206 return dev_err_probe(dev, PTR_ERR(priv->clkin), "failed to get clkin\n"); in meson_sar_adc_probe()
1208 priv->core_clk = devm_clk_get(dev, "core"); in meson_sar_adc_probe()
1209 if (IS_ERR(priv->core_clk)) in meson_sar_adc_probe()
1210 return dev_err_probe(dev, PTR_ERR(priv->core_clk), "failed to get core clk\n"); in meson_sar_adc_probe()
1212 priv->adc_clk = devm_clk_get_optional(dev, "adc_clk"); in meson_sar_adc_probe()
1213 if (IS_ERR(priv->adc_clk)) in meson_sar_adc_probe()
1214 return dev_err_probe(dev, PTR_ERR(priv->adc_clk), "failed to get adc clk\n"); in meson_sar_adc_probe()
1216 priv->adc_sel_clk = devm_clk_get_optional(dev, "adc_sel"); in meson_sar_adc_probe()
1217 if (IS_ERR(priv->adc_sel_clk)) in meson_sar_adc_probe()
1218 return dev_err_probe(dev, PTR_ERR(priv->adc_sel_clk), "failed to get adc_sel clk\n"); in meson_sar_adc_probe()
1220 /* on pre-GXBB SoCs the SAR ADC itself provides the ADC clock: */ in meson_sar_adc_probe()
1221 if (!priv->adc_clk) { in meson_sar_adc_probe()
1227 priv->vref = devm_regulator_get(dev, "vref"); in meson_sar_adc_probe()
1228 if (IS_ERR(priv->vref)) in meson_sar_adc_probe()
1229 return dev_err_probe(dev, PTR_ERR(priv->vref), "failed to get vref regulator\n"); in meson_sar_adc_probe()
1231 priv->calibscale = MILLION; in meson_sar_adc_probe()
1233 if (priv->param->temperature_trimming_bits) { in meson_sar_adc_probe()
1239 if (priv->temperature_sensor_calibrated) { in meson_sar_adc_probe()
1240 indio_dev->channels = meson_sar_adc_and_temp_iio_channels; in meson_sar_adc_probe()
1241 indio_dev->num_channels = in meson_sar_adc_probe()
1244 indio_dev->channels = meson_sar_adc_iio_channels; in meson_sar_adc_probe()
1245 indio_dev->num_channels = in meson_sar_adc_probe()
1305 .name = "meson-saradc",
1314 MODULE_DESCRIPTION("Amlogic Meson SAR ADC driver");