Lines Matching +full:tegra194 +full:- +full:dc
1 // SPDX-License-Identifier: GPL-2.0-only
5 * Copyright (c) 2014-2022, NVIDIA CORPORATION. All rights reserved.
10 #include <linux/dma-mapping.h>
21 #include <dt-bindings/memory/tegra186-mc.h>
22 #include "virt-dma.h"
118 (GENMASK((fls(bs) - 2), 0) << TEGRA_GPCDMA_MMIOSEQ_BURST_SHIFT)
158 * on-flight burst and update DMA status register.
200 * sub-transfer as per requester details and hw support. This sub transfer
259 writel_relaxed(val, tdc->tdma->base_addr + tdc->chan_base_offset + reg); in tdc_write()
264 return readl_relaxed(tdc->tdma->base_addr + tdc->chan_base_offset + reg); in tdc_read()
267 static inline struct tegra_dma_channel *to_tegra_dma_chan(struct dma_chan *dc) in to_tegra_dma_chan() argument
269 return container_of(dc, struct tegra_dma_channel, vc.chan); in to_tegra_dma_chan()
279 return tdc->vc.chan.device->dev; in tdc2dev()
285 tdc->id, tdc->name); in tegra_dma_dump_chan_regs()
307 struct tegra_dma *tdma = tdc->tdma; in tegra_dma_sid_reserve()
308 int sid = tdc->slave_id; in tegra_dma_sid_reserve()
315 if (test_and_set_bit(sid, &tdma->sid_m2d_reserved)) { in tegra_dma_sid_reserve()
316 dev_err(tdma->dev, "slave id already in use\n"); in tegra_dma_sid_reserve()
317 return -EINVAL; in tegra_dma_sid_reserve()
321 if (test_and_set_bit(sid, &tdma->sid_d2m_reserved)) { in tegra_dma_sid_reserve()
322 dev_err(tdma->dev, "slave id already in use\n"); in tegra_dma_sid_reserve()
323 return -EINVAL; in tegra_dma_sid_reserve()
330 tdc->sid_dir = direction; in tegra_dma_sid_reserve()
337 struct tegra_dma *tdma = tdc->tdma; in tegra_dma_sid_free()
338 int sid = tdc->slave_id; in tegra_dma_sid_free()
340 switch (tdc->sid_dir) { in tegra_dma_sid_free()
342 clear_bit(sid, &tdma->sid_m2d_reserved); in tegra_dma_sid_free()
345 clear_bit(sid, &tdma->sid_d2m_reserved); in tegra_dma_sid_free()
351 tdc->sid_dir = DMA_TRANS_NONE; in tegra_dma_sid_free()
359 static int tegra_dma_slave_config(struct dma_chan *dc, in tegra_dma_slave_config() argument
362 struct tegra_dma_channel *tdc = to_tegra_dma_chan(dc); in tegra_dma_slave_config()
364 memcpy(&tdc->dma_sconfig, sconfig, sizeof(*sconfig)); in tegra_dma_slave_config()
365 tdc->config_init = true; in tegra_dma_slave_config()
379 /* Wait until busy bit is de-asserted */ in tegra_dma_pause()
380 ret = readl_relaxed_poll_timeout_atomic(tdc->tdma->base_addr + in tegra_dma_pause()
381 tdc->chan_base_offset + TEGRA_GPCDMA_CHAN_STATUS, in tegra_dma_pause()
395 static int tegra_dma_device_pause(struct dma_chan *dc) in tegra_dma_device_pause() argument
397 struct tegra_dma_channel *tdc = to_tegra_dma_chan(dc); in tegra_dma_device_pause()
401 if (!tdc->tdma->chip_data->hw_support_pause) in tegra_dma_device_pause()
402 return -ENOSYS; in tegra_dma_device_pause()
404 spin_lock_irqsave(&tdc->vc.lock, flags); in tegra_dma_device_pause()
406 spin_unlock_irqrestore(&tdc->vc.lock, flags); in tegra_dma_device_pause()
420 static int tegra_dma_device_resume(struct dma_chan *dc) in tegra_dma_device_resume() argument
422 struct tegra_dma_channel *tdc = to_tegra_dma_chan(dc); in tegra_dma_device_resume()
425 if (!tdc->tdma->chip_data->hw_support_pause) in tegra_dma_device_resume()
426 return -ENOSYS; in tegra_dma_device_resume()
428 spin_lock_irqsave(&tdc->vc.lock, flags); in tegra_dma_device_resume()
430 spin_unlock_irqrestore(&tdc->vc.lock, flags); in tegra_dma_device_resume()
469 struct tegra_dma_desc *dma_desc = tdc->dma_desc; in tegra_dma_configure_next_sg()
474 dma_desc->sg_idx++; in tegra_dma_configure_next_sg()
477 if (dma_desc->sg_idx == dma_desc->sg_count) in tegra_dma_configure_next_sg()
478 dma_desc->sg_idx = 0; in tegra_dma_configure_next_sg()
481 ret = readl_relaxed_poll_timeout_atomic(tdc->tdma->base_addr + in tegra_dma_configure_next_sg()
482 tdc->chan_base_offset + TEGRA_GPCDMA_CHAN_STATUS, in tegra_dma_configure_next_sg()
489 ch_regs = &dma_desc->sg_req[dma_desc->sg_idx].ch_regs; in tegra_dma_configure_next_sg()
491 tdc_write(tdc, TEGRA_GPCDMA_CHAN_WCOUNT, ch_regs->wcount); in tegra_dma_configure_next_sg()
492 tdc_write(tdc, TEGRA_GPCDMA_CHAN_SRC_PTR, ch_regs->src_ptr); in tegra_dma_configure_next_sg()
493 tdc_write(tdc, TEGRA_GPCDMA_CHAN_DST_PTR, ch_regs->dst_ptr); in tegra_dma_configure_next_sg()
494 tdc_write(tdc, TEGRA_GPCDMA_CHAN_HIGH_ADDR_PTR, ch_regs->high_addr_ptr); in tegra_dma_configure_next_sg()
498 ch_regs->csr | TEGRA_GPCDMA_CSR_ENB); in tegra_dma_configure_next_sg()
503 struct tegra_dma_desc *dma_desc = tdc->dma_desc; in tegra_dma_start()
508 vdesc = vchan_next_desc(&tdc->vc); in tegra_dma_start()
513 list_del(&vdesc->node); in tegra_dma_start()
514 dma_desc->tdc = tdc; in tegra_dma_start()
515 tdc->dma_desc = dma_desc; in tegra_dma_start()
520 ch_regs = &dma_desc->sg_req[dma_desc->sg_idx].ch_regs; in tegra_dma_start()
522 tdc_write(tdc, TEGRA_GPCDMA_CHAN_WCOUNT, ch_regs->wcount); in tegra_dma_start()
524 tdc_write(tdc, TEGRA_GPCDMA_CHAN_SRC_PTR, ch_regs->src_ptr); in tegra_dma_start()
525 tdc_write(tdc, TEGRA_GPCDMA_CHAN_DST_PTR, ch_regs->dst_ptr); in tegra_dma_start()
526 tdc_write(tdc, TEGRA_GPCDMA_CHAN_HIGH_ADDR_PTR, ch_regs->high_addr_ptr); in tegra_dma_start()
527 tdc_write(tdc, TEGRA_GPCDMA_CHAN_FIXED_PATTERN, ch_regs->fixed_pattern); in tegra_dma_start()
528 tdc_write(tdc, TEGRA_GPCDMA_CHAN_MMIOSEQ, ch_regs->mmio_seq); in tegra_dma_start()
529 tdc_write(tdc, TEGRA_GPCDMA_CHAN_MCSEQ, ch_regs->mc_seq); in tegra_dma_start()
530 tdc_write(tdc, TEGRA_GPCDMA_CHAN_CSR, ch_regs->csr); in tegra_dma_start()
534 ch_regs->csr | TEGRA_GPCDMA_CSR_ENB); in tegra_dma_start()
539 vchan_cookie_complete(&tdc->dma_desc->vd); in tegra_dma_xfer_complete()
542 tdc->dma_desc = NULL; in tegra_dma_xfer_complete()
550 dev_err(tdc->tdma->dev, in tegra_dma_chan_decode_error()
551 "GPCDMA CH%d bm fifo full\n", tdc->id); in tegra_dma_chan_decode_error()
555 dev_err(tdc->tdma->dev, in tegra_dma_chan_decode_error()
556 "GPCDMA CH%d peripheral fifo full\n", tdc->id); in tegra_dma_chan_decode_error()
560 dev_err(tdc->tdma->dev, in tegra_dma_chan_decode_error()
561 "GPCDMA CH%d illegal peripheral id\n", tdc->id); in tegra_dma_chan_decode_error()
565 dev_err(tdc->tdma->dev, in tegra_dma_chan_decode_error()
566 "GPCDMA CH%d illegal stream id\n", tdc->id); in tegra_dma_chan_decode_error()
570 dev_err(tdc->tdma->dev, in tegra_dma_chan_decode_error()
571 "GPCDMA CH%d mc slave error\n", tdc->id); in tegra_dma_chan_decode_error()
575 dev_err(tdc->tdma->dev, in tegra_dma_chan_decode_error()
576 "GPCDMA CH%d mmio slave error\n", tdc->id); in tegra_dma_chan_decode_error()
580 dev_err(tdc->tdma->dev, in tegra_dma_chan_decode_error()
581 "GPCDMA CH%d security violation %x\n", tdc->id, in tegra_dma_chan_decode_error()
589 struct tegra_dma_desc *dma_desc = tdc->dma_desc; in tegra_dma_isr()
601 spin_lock(&tdc->vc.lock); in tegra_dma_isr()
612 sg_req = dma_desc->sg_req; in tegra_dma_isr()
613 dma_desc->bytes_xfer += sg_req[dma_desc->sg_idx].len; in tegra_dma_isr()
615 if (dma_desc->cyclic) { in tegra_dma_isr()
616 vchan_cyclic_callback(&dma_desc->vd); in tegra_dma_isr()
619 dma_desc->sg_idx++; in tegra_dma_isr()
620 if (dma_desc->sg_idx == dma_desc->sg_count) in tegra_dma_isr()
627 spin_unlock(&tdc->vc.lock); in tegra_dma_isr()
631 static void tegra_dma_issue_pending(struct dma_chan *dc) in tegra_dma_issue_pending() argument
633 struct tegra_dma_channel *tdc = to_tegra_dma_chan(dc); in tegra_dma_issue_pending()
636 if (tdc->dma_desc) in tegra_dma_issue_pending()
639 spin_lock_irqsave(&tdc->vc.lock, flags); in tegra_dma_issue_pending()
640 if (vchan_issue_pending(&tdc->vc)) in tegra_dma_issue_pending()
650 if (tdc->dma_desc && tdc->dma_desc->cyclic) in tegra_dma_issue_pending()
653 spin_unlock_irqrestore(&tdc->vc.lock, flags); in tegra_dma_issue_pending()
678 ret = readl_relaxed_poll_timeout_atomic(tdc->tdma->base_addr + in tegra_dma_stop_client()
679 tdc->chan_base_offset + in tegra_dma_stop_client()
694 static int tegra_dma_terminate_all(struct dma_chan *dc) in tegra_dma_terminate_all() argument
696 struct tegra_dma_channel *tdc = to_tegra_dma_chan(dc); in tegra_dma_terminate_all()
701 spin_lock_irqsave(&tdc->vc.lock, flags); in tegra_dma_terminate_all()
703 if (tdc->dma_desc) { in tegra_dma_terminate_all()
704 err = tdc->tdma->chip_data->terminate(tdc); in tegra_dma_terminate_all()
706 spin_unlock_irqrestore(&tdc->vc.lock, flags); in tegra_dma_terminate_all()
711 tdc->dma_desc = NULL; in tegra_dma_terminate_all()
715 vchan_get_all_descriptors(&tdc->vc, &head); in tegra_dma_terminate_all()
716 spin_unlock_irqrestore(&tdc->vc.lock, flags); in tegra_dma_terminate_all()
718 vchan_dma_desc_free_list(&tdc->vc, &head); in tegra_dma_terminate_all()
725 struct tegra_dma_desc *dma_desc = tdc->dma_desc; in tegra_dma_get_residual()
726 struct tegra_dma_sg_req *sg_req = dma_desc->sg_req; in tegra_dma_get_residual()
741 bytes_xfer = dma_desc->bytes_xfer + in tegra_dma_get_residual()
742 sg_req[dma_desc->sg_idx].len - (wcount * 4); in tegra_dma_get_residual()
744 residual = dma_desc->bytes_req - (bytes_xfer % dma_desc->bytes_req); in tegra_dma_get_residual()
749 static enum dma_status tegra_dma_tx_status(struct dma_chan *dc, in tegra_dma_tx_status() argument
753 struct tegra_dma_channel *tdc = to_tegra_dma_chan(dc); in tegra_dma_tx_status()
760 ret = dma_cookie_status(dc, cookie, txstate); in tegra_dma_tx_status()
764 spin_lock_irqsave(&tdc->vc.lock, flags); in tegra_dma_tx_status()
765 vd = vchan_find_desc(&tdc->vc, cookie); in tegra_dma_tx_status()
768 residual = dma_desc->bytes_req; in tegra_dma_tx_status()
770 } else if (tdc->dma_desc && tdc->dma_desc->vd.tx.cookie == cookie) { in tegra_dma_tx_status()
776 spin_unlock_irqrestore(&tdc->vc.lock, flags); in tegra_dma_tx_status()
793 return -EINVAL; in get_bus_width()
830 *apb_addr = tdc->dma_sconfig.dst_addr; in get_transfer_param()
831 *mmio_seq = get_bus_width(tdc, tdc->dma_sconfig.dst_addr_width); in get_transfer_param()
832 *burst_size = tdc->dma_sconfig.dst_maxburst; in get_transfer_param()
833 *slave_bw = tdc->dma_sconfig.dst_addr_width; in get_transfer_param()
837 *apb_addr = tdc->dma_sconfig.src_addr; in get_transfer_param()
838 *mmio_seq = get_bus_width(tdc, tdc->dma_sconfig.src_addr_width); in get_transfer_param()
839 *burst_size = tdc->dma_sconfig.src_maxburst; in get_transfer_param()
840 *slave_bw = tdc->dma_sconfig.src_addr_width; in get_transfer_param()
847 return -EINVAL; in get_transfer_param()
851 tegra_dma_prep_dma_memset(struct dma_chan *dc, dma_addr_t dest, int value, in tegra_dma_prep_dma_memset() argument
854 struct tegra_dma_channel *tdc = to_tegra_dma_chan(dc); in tegra_dma_prep_dma_memset()
855 unsigned int max_dma_count = tdc->tdma->chip_data->max_dma_count; in tegra_dma_prep_dma_memset()
879 /* retain stream-id and clean rest */ in tegra_dma_prep_dma_memset()
897 dma_desc->bytes_req = len; in tegra_dma_prep_dma_memset()
898 dma_desc->sg_count = 1; in tegra_dma_prep_dma_memset()
899 sg_req = dma_desc->sg_req; in tegra_dma_prep_dma_memset()
907 sg_req[0].ch_regs.wcount = ((len - 4) >> 2); in tegra_dma_prep_dma_memset()
913 dma_desc->cyclic = false; in tegra_dma_prep_dma_memset()
914 return vchan_tx_prep(&tdc->vc, &dma_desc->vd, flags); in tegra_dma_prep_dma_memset()
918 tegra_dma_prep_dma_memcpy(struct dma_chan *dc, dma_addr_t dest, in tegra_dma_prep_dma_memcpy() argument
921 struct tegra_dma_channel *tdc = to_tegra_dma_chan(dc); in tegra_dma_prep_dma_memcpy()
927 max_dma_count = tdc->tdma->chip_data->max_dma_count; in tegra_dma_prep_dma_memcpy()
947 /* retain stream-id and clean rest */ in tegra_dma_prep_dma_memcpy()
966 dma_desc->bytes_req = len; in tegra_dma_prep_dma_memcpy()
967 dma_desc->sg_count = 1; in tegra_dma_prep_dma_memcpy()
968 sg_req = dma_desc->sg_req; in tegra_dma_prep_dma_memcpy()
977 sg_req[0].ch_regs.wcount = ((len - 4) >> 2); in tegra_dma_prep_dma_memcpy()
983 dma_desc->cyclic = false; in tegra_dma_prep_dma_memcpy()
984 return vchan_tx_prep(&tdc->vc, &dma_desc->vd, flags); in tegra_dma_prep_dma_memcpy()
988 tegra_dma_prep_slave_sg(struct dma_chan *dc, struct scatterlist *sgl, in tegra_dma_prep_slave_sg() argument
992 struct tegra_dma_channel *tdc = to_tegra_dma_chan(dc); in tegra_dma_prep_slave_sg()
993 unsigned int max_dma_count = tdc->tdma->chip_data->max_dma_count; in tegra_dma_prep_slave_sg()
1003 if (!tdc->config_init) { in tegra_dma_prep_slave_sg()
1024 csr |= FIELD_PREP(TEGRA_GPCDMA_CSR_REQ_SEL_MASK, tdc->slave_id); in tegra_dma_prep_slave_sg()
1035 /* retain stream-id and clean rest */ in tegra_dma_prep_slave_sg()
1059 dma_desc->sg_count = sg_len; in tegra_dma_prep_slave_sg()
1060 sg_req = dma_desc->sg_req; in tegra_dma_prep_slave_sg()
1078 dma_desc->bytes_req += len; in tegra_dma_prep_slave_sg()
1096 sg_req[i].ch_regs.wcount = ((len - 4) >> 2); in tegra_dma_prep_slave_sg()
1103 dma_desc->cyclic = false; in tegra_dma_prep_slave_sg()
1104 return vchan_tx_prep(&tdc->vc, &dma_desc->vd, flags); in tegra_dma_prep_slave_sg()
1108 tegra_dma_prep_dma_cyclic(struct dma_chan *dc, dma_addr_t buf_addr, size_t buf_len, in tegra_dma_prep_dma_cyclic() argument
1115 struct tegra_dma_channel *tdc = to_tegra_dma_chan(dc); in tegra_dma_prep_dma_cyclic()
1126 if (!tdc->config_init) { in tegra_dma_prep_dma_cyclic()
1145 max_dma_count = tdc->tdma->chip_data->max_dma_count; in tegra_dma_prep_dma_cyclic()
1159 csr |= FIELD_PREP(TEGRA_GPCDMA_CSR_REQ_SEL_MASK, tdc->slave_id); in tegra_dma_prep_dma_cyclic()
1172 /* retain stream-id and clean rest */ in tegra_dma_prep_dma_cyclic()
1195 dma_desc->bytes_req = buf_len; in tegra_dma_prep_dma_cyclic()
1196 dma_desc->sg_count = period_count; in tegra_dma_prep_dma_cyclic()
1197 sg_req = dma_desc->sg_req; in tegra_dma_prep_dma_cyclic()
1217 sg_req[i].ch_regs.wcount = ((len - 4) >> 2); in tegra_dma_prep_dma_cyclic()
1226 dma_desc->cyclic = true; in tegra_dma_prep_dma_cyclic()
1228 return vchan_tx_prep(&tdc->vc, &dma_desc->vd, flags); in tegra_dma_prep_dma_cyclic()
1231 static int tegra_dma_alloc_chan_resources(struct dma_chan *dc) in tegra_dma_alloc_chan_resources() argument
1233 struct tegra_dma_channel *tdc = to_tegra_dma_chan(dc); in tegra_dma_alloc_chan_resources()
1236 ret = request_irq(tdc->irq, tegra_dma_isr, 0, tdc->name, tdc); in tegra_dma_alloc_chan_resources()
1238 dev_err(tdc2dev(tdc), "request_irq failed for %s\n", tdc->name); in tegra_dma_alloc_chan_resources()
1242 dma_cookie_init(&tdc->vc.chan); in tegra_dma_alloc_chan_resources()
1243 tdc->config_init = false; in tegra_dma_alloc_chan_resources()
1247 static void tegra_dma_chan_synchronize(struct dma_chan *dc) in tegra_dma_chan_synchronize() argument
1249 struct tegra_dma_channel *tdc = to_tegra_dma_chan(dc); in tegra_dma_chan_synchronize()
1251 synchronize_irq(tdc->irq); in tegra_dma_chan_synchronize()
1252 vchan_synchronize(&tdc->vc); in tegra_dma_chan_synchronize()
1255 static void tegra_dma_free_chan_resources(struct dma_chan *dc) in tegra_dma_free_chan_resources() argument
1257 struct tegra_dma_channel *tdc = to_tegra_dma_chan(dc); in tegra_dma_free_chan_resources()
1259 dev_dbg(tdc2dev(tdc), "Freeing channel %d\n", tdc->id); in tegra_dma_free_chan_resources()
1261 tegra_dma_terminate_all(dc); in tegra_dma_free_chan_resources()
1262 synchronize_irq(tdc->irq); in tegra_dma_free_chan_resources()
1264 tasklet_kill(&tdc->vc.task); in tegra_dma_free_chan_resources()
1265 tdc->config_init = false; in tegra_dma_free_chan_resources()
1266 tdc->slave_id = -1; in tegra_dma_free_chan_resources()
1267 tdc->sid_dir = DMA_TRANS_NONE; in tegra_dma_free_chan_resources()
1268 free_irq(tdc->irq, tdc); in tegra_dma_free_chan_resources()
1270 vchan_free_chan_resources(&tdc->vc); in tegra_dma_free_chan_resources()
1276 struct tegra_dma *tdma = ofdma->of_dma_data; in tegra_dma_of_xlate()
1280 chan = dma_get_any_slave_channel(&tdma->dma_dev); in tegra_dma_of_xlate()
1285 tdc->slave_id = dma_spec->args[0]; in tegra_dma_of_xlate()
1316 .compatible = "nvidia,tegra186-gpcdma",
1319 .compatible = "nvidia,tegra194-gpcdma",
1322 .compatible = "nvidia,tegra234-gpcdma",
1351 cdata = of_device_get_match_data(&pdev->dev); in tegra_dma_probe()
1353 tdma = devm_kzalloc(&pdev->dev, in tegra_dma_probe()
1354 struct_size(tdma, channels, cdata->nr_channels), in tegra_dma_probe()
1357 return -ENOMEM; in tegra_dma_probe()
1359 tdma->dev = &pdev->dev; in tegra_dma_probe()
1360 tdma->chip_data = cdata; in tegra_dma_probe()
1363 tdma->base_addr = devm_platform_ioremap_resource(pdev, 0); in tegra_dma_probe()
1364 if (IS_ERR(tdma->base_addr)) in tegra_dma_probe()
1365 return PTR_ERR(tdma->base_addr); in tegra_dma_probe()
1367 tdma->rst = devm_reset_control_get_exclusive(&pdev->dev, "gpcdma"); in tegra_dma_probe()
1368 if (IS_ERR(tdma->rst)) { in tegra_dma_probe()
1369 return dev_err_probe(&pdev->dev, PTR_ERR(tdma->rst), in tegra_dma_probe()
1372 reset_control_reset(tdma->rst); in tegra_dma_probe()
1374 tdma->dma_dev.dev = &pdev->dev; in tegra_dma_probe()
1376 iommu_spec = dev_iommu_fwspec_get(&pdev->dev); in tegra_dma_probe()
1378 dev_err(&pdev->dev, "Missing iommu stream-id\n"); in tegra_dma_probe()
1379 return -EINVAL; in tegra_dma_probe()
1381 stream_id = iommu_spec->ids[0] & 0xffff; in tegra_dma_probe()
1383 INIT_LIST_HEAD(&tdma->dma_dev.channels); in tegra_dma_probe()
1384 for (i = 0; i < cdata->nr_channels; i++) { in tegra_dma_probe()
1385 struct tegra_dma_channel *tdc = &tdma->channels[i]; in tegra_dma_probe()
1387 tdc->irq = platform_get_irq(pdev, i); in tegra_dma_probe()
1388 if (tdc->irq < 0) in tegra_dma_probe()
1389 return tdc->irq; in tegra_dma_probe()
1391 tdc->chan_base_offset = TEGRA_GPCDMA_CHANNEL_BASE_ADD_OFFSET + in tegra_dma_probe()
1392 i * cdata->channel_reg_size; in tegra_dma_probe()
1393 snprintf(tdc->name, sizeof(tdc->name), "gpcdma.%d", i); in tegra_dma_probe()
1394 tdc->tdma = tdma; in tegra_dma_probe()
1395 tdc->id = i; in tegra_dma_probe()
1396 tdc->slave_id = -1; in tegra_dma_probe()
1398 vchan_init(&tdc->vc, &tdma->dma_dev); in tegra_dma_probe()
1399 tdc->vc.desc_free = tegra_dma_desc_free; in tegra_dma_probe()
1401 /* program stream-id for this channel */ in tegra_dma_probe()
1403 tdc->stream_id = stream_id; in tegra_dma_probe()
1406 dma_cap_set(DMA_SLAVE, tdma->dma_dev.cap_mask); in tegra_dma_probe()
1407 dma_cap_set(DMA_PRIVATE, tdma->dma_dev.cap_mask); in tegra_dma_probe()
1408 dma_cap_set(DMA_MEMCPY, tdma->dma_dev.cap_mask); in tegra_dma_probe()
1409 dma_cap_set(DMA_MEMSET, tdma->dma_dev.cap_mask); in tegra_dma_probe()
1410 dma_cap_set(DMA_CYCLIC, tdma->dma_dev.cap_mask); in tegra_dma_probe()
1416 tdma->dma_dev.copy_align = 2; in tegra_dma_probe()
1417 tdma->dma_dev.fill_align = 2; in tegra_dma_probe()
1418 tdma->dma_dev.device_alloc_chan_resources = in tegra_dma_probe()
1420 tdma->dma_dev.device_free_chan_resources = in tegra_dma_probe()
1422 tdma->dma_dev.device_prep_slave_sg = tegra_dma_prep_slave_sg; in tegra_dma_probe()
1423 tdma->dma_dev.device_prep_dma_memcpy = tegra_dma_prep_dma_memcpy; in tegra_dma_probe()
1424 tdma->dma_dev.device_prep_dma_memset = tegra_dma_prep_dma_memset; in tegra_dma_probe()
1425 tdma->dma_dev.device_prep_dma_cyclic = tegra_dma_prep_dma_cyclic; in tegra_dma_probe()
1426 tdma->dma_dev.device_config = tegra_dma_slave_config; in tegra_dma_probe()
1427 tdma->dma_dev.device_terminate_all = tegra_dma_terminate_all; in tegra_dma_probe()
1428 tdma->dma_dev.device_tx_status = tegra_dma_tx_status; in tegra_dma_probe()
1429 tdma->dma_dev.device_issue_pending = tegra_dma_issue_pending; in tegra_dma_probe()
1430 tdma->dma_dev.device_pause = tegra_dma_device_pause; in tegra_dma_probe()
1431 tdma->dma_dev.device_resume = tegra_dma_device_resume; in tegra_dma_probe()
1432 tdma->dma_dev.device_synchronize = tegra_dma_chan_synchronize; in tegra_dma_probe()
1433 tdma->dma_dev.residue_granularity = DMA_RESIDUE_GRANULARITY_BURST; in tegra_dma_probe()
1435 ret = dma_async_device_register(&tdma->dma_dev); in tegra_dma_probe()
1437 dev_err_probe(&pdev->dev, ret, in tegra_dma_probe()
1442 ret = of_dma_controller_register(pdev->dev.of_node, in tegra_dma_probe()
1445 dev_err_probe(&pdev->dev, ret, in tegra_dma_probe()
1448 dma_async_device_unregister(&tdma->dma_dev); in tegra_dma_probe()
1452 dev_info(&pdev->dev, "GPC DMA driver register %d channels\n", in tegra_dma_probe()
1453 cdata->nr_channels); in tegra_dma_probe()
1462 of_dma_controller_free(pdev->dev.of_node); in tegra_dma_remove()
1463 dma_async_device_unregister(&tdma->dma_dev); in tegra_dma_remove()
1473 for (i = 0; i < tdma->chip_data->nr_channels; i++) { in tegra_dma_pm_suspend()
1474 struct tegra_dma_channel *tdc = &tdma->channels[i]; in tegra_dma_pm_suspend()
1476 if (tdc->dma_desc) { in tegra_dma_pm_suspend()
1477 dev_err(tdma->dev, "channel %u busy\n", i); in tegra_dma_pm_suspend()
1478 return -EBUSY; in tegra_dma_pm_suspend()
1490 reset_control_reset(tdma->rst); in tegra_dma_pm_resume()
1492 for (i = 0; i < tdma->chip_data->nr_channels; i++) { in tegra_dma_pm_resume()
1493 struct tegra_dma_channel *tdc = &tdma->channels[i]; in tegra_dma_pm_resume()
1495 tegra_dma_program_sid(tdc, tdc->stream_id); in tegra_dma_pm_resume()
1507 .name = "tegra-gpcdma",