Lines Matching +full:0 +full:x17c00000
23 /* Register Offset definitions for CMU_TOP (0x1b240000) */
24 #define PLL_LOCKTIME_PLL_SHARED0 0x0000
25 #define PLL_LOCKTIME_PLL_SHARED1 0x0004
26 #define PLL_LOCKTIME_PLL_SHARED2 0x0008
27 #define PLL_LOCKTIME_PLL_SHARED3 0x000c
28 #define PLL_LOCKTIME_PLL_SHARED4 0x0010
29 #define PLL_CON0_PLL_SHARED0 0x0100
30 #define PLL_CON3_PLL_SHARED0 0x010c
31 #define PLL_CON0_PLL_SHARED1 0x0140
32 #define PLL_CON3_PLL_SHARED1 0x014c
33 #define PLL_CON0_PLL_SHARED2 0x0180
34 #define PLL_CON3_PLL_SHARED2 0x018c
35 #define PLL_CON0_PLL_SHARED3 0x01c0
36 #define PLL_CON3_PLL_SHARED3 0x01cc
37 #define PLL_CON0_PLL_SHARED4 0x0200
38 #define PLL_CON3_PLL_SHARED4 0x020c
41 #define CLK_CON_MUX_MUX_CLKCMU_ACC_BUS 0x1000
42 #define CLK_CON_MUX_MUX_CLKCMU_APM_BUS 0x1004
43 #define CLK_CON_MUX_MUX_CLKCMU_AUD_BUS 0x1008
44 #define CLK_CON_MUX_MUX_CLKCMU_AUD_CPU 0x100c
45 #define CLK_CON_MUX_MUX_CLKCMU_BUSC_BUS 0x1010
46 #define CLK_CON_MUX_MUX_CLKCMU_BUSMC_BUS 0x1018
47 #define CLK_CON_MUX_MUX_CLKCMU_CMU_BOOST 0x101c
48 #define CLK_CON_MUX_MUX_CLKCMU_CORE_BUS 0x1020
49 #define CLK_CON_MUX_MUX_CLKCMU_CPUCL0_CLUSTER 0x1024
50 #define CLK_CON_MUX_MUX_CLKCMU_CPUCL0_SWITCH 0x102c
51 #define CLK_CON_MUX_MUX_CLKCMU_CPUCL1_CLUSTER 0x1030
52 #define CLK_CON_MUX_MUX_CLKCMU_CPUCL1_SWITCH 0x1034
53 #define CLK_CON_MUX_MUX_CLKCMU_DPTX_BUS 0x1040
54 #define CLK_CON_MUX_MUX_CLKCMU_DPTX_DPGTC 0x1044
55 #define CLK_CON_MUX_MUX_CLKCMU_DPUM_BUS 0x1048
56 #define CLK_CON_MUX_MUX_CLKCMU_DPUS0_BUS 0x104c
57 #define CLK_CON_MUX_MUX_CLKCMU_DPUS1_BUS 0x1050
58 #define CLK_CON_MUX_MUX_CLKCMU_FSYS0_BUS 0x1054
59 #define CLK_CON_MUX_MUX_CLKCMU_FSYS0_PCIE 0x1058
60 #define CLK_CON_MUX_MUX_CLKCMU_FSYS1_BUS 0x105c
61 #define CLK_CON_MUX_MUX_CLKCMU_FSYS1_MMC_CARD 0x1060
62 #define CLK_CON_MUX_MUX_CLKCMU_FSYS1_USBDRD 0x1064
63 #define CLK_CON_MUX_MUX_CLKCMU_FSYS2_BUS 0x1068
64 #define CLK_CON_MUX_MUX_CLKCMU_FSYS2_ETHERNET 0x106c
65 #define CLK_CON_MUX_MUX_CLKCMU_FSYS2_UFS_EMBD 0x1070
66 #define CLK_CON_MUX_MUX_CLKCMU_G2D_G2D 0x1074
67 #define CLK_CON_MUX_MUX_CLKCMU_G2D_MSCL 0x1078
68 #define CLK_CON_MUX_MUX_CLKCMU_G3D00_SWITCH 0x107c
69 #define CLK_CON_MUX_MUX_CLKCMU_G3D01_SWITCH 0x1080
70 #define CLK_CON_MUX_MUX_CLKCMU_G3D1_SWITCH 0x1084
71 #define CLK_CON_MUX_MUX_CLKCMU_ISPB_BUS 0x108c
72 #define CLK_CON_MUX_MUX_CLKCMU_MFC_MFC 0x1090
73 #define CLK_CON_MUX_MUX_CLKCMU_MFC_WFD 0x1094
74 #define CLK_CON_MUX_MUX_CLKCMU_MIF_SWITCH 0x109c
75 #define CLK_CON_MUX_MUX_CLKCMU_MIF_BUSP 0x1098
76 #define CLK_CON_MUX_MUX_CLKCMU_MIF_SWITCH 0x109c
77 #define CLK_CON_MUX_MUX_CLKCMU_NPU_BUS 0x10a0
78 #define CLK_CON_MUX_MUX_CLKCMU_PERIC0_BUS 0x10a4
79 #define CLK_CON_MUX_MUX_CLKCMU_PERIC0_IP 0x10a8
80 #define CLK_CON_MUX_MUX_CLKCMU_PERIC1_BUS 0x10ac
81 #define CLK_CON_MUX_MUX_CLKCMU_PERIC1_IP 0x10b0
82 #define CLK_CON_MUX_MUX_CLKCMU_PERIS_BUS 0x10b4
83 #define CLK_CON_MUX_MUX_CMU_CMUREF 0x10c0
86 #define CLK_CON_DIV_CLKCMU_ACC_BUS 0x1800
87 #define CLK_CON_DIV_CLKCMU_APM_BUS 0x1804
88 #define CLK_CON_DIV_CLKCMU_AUD_BUS 0x1808
89 #define CLK_CON_DIV_CLKCMU_AUD_CPU 0x180c
90 #define CLK_CON_DIV_CLKCMU_BUSC_BUS 0x1810
91 #define CLK_CON_DIV_CLKCMU_BUSMC_BUS 0x1818
92 #define CLK_CON_DIV_CLKCMU_CORE_BUS 0x181c
93 #define CLK_CON_DIV_CLKCMU_CPUCL0_CLUSTER 0x1820
94 #define CLK_CON_DIV_CLKCMU_CPUCL0_SWITCH 0x1828
95 #define CLK_CON_DIV_CLKCMU_CPUCL1_CLUSTER 0x182c
96 #define CLK_CON_DIV_CLKCMU_CPUCL1_SWITCH 0x1830
97 #define CLK_CON_DIV_CLKCMU_DPTX_BUS 0x183c
98 #define CLK_CON_DIV_CLKCMU_DPTX_DPGTC 0x1840
99 #define CLK_CON_DIV_CLKCMU_DPUM_BUS 0x1844
100 #define CLK_CON_DIV_CLKCMU_DPUS0_BUS 0x1848
101 #define CLK_CON_DIV_CLKCMU_DPUS1_BUS 0x184c
102 #define CLK_CON_DIV_CLKCMU_FSYS0_BUS 0x1850
103 #define CLK_CON_DIV_CLKCMU_FSYS0_PCIE 0x1854
104 #define CLK_CON_DIV_CLKCMU_FSYS1_BUS 0x1858
105 #define CLK_CON_DIV_CLKCMU_FSYS1_USBDRD 0x185c
106 #define CLK_CON_DIV_CLKCMU_FSYS2_BUS 0x1860
107 #define CLK_CON_DIV_CLKCMU_FSYS2_ETHERNET 0x1864
108 #define CLK_CON_DIV_CLKCMU_FSYS2_UFS_EMBD 0x1868
109 #define CLK_CON_DIV_CLKCMU_G2D_G2D 0x186c
110 #define CLK_CON_DIV_CLKCMU_G2D_MSCL 0x1870
111 #define CLK_CON_DIV_CLKCMU_G3D00_SWITCH 0x1874
112 #define CLK_CON_DIV_CLKCMU_G3D01_SWITCH 0x1878
113 #define CLK_CON_DIV_CLKCMU_G3D1_SWITCH 0x187c
114 #define CLK_CON_DIV_CLKCMU_ISPB_BUS 0x1884
115 #define CLK_CON_DIV_CLKCMU_MFC_MFC 0x1888
116 #define CLK_CON_DIV_CLKCMU_MFC_WFD 0x188c
117 #define CLK_CON_DIV_CLKCMU_MIF_BUSP 0x1890
118 #define CLK_CON_DIV_CLKCMU_NPU_BUS 0x1894
119 #define CLK_CON_DIV_CLKCMU_PERIC0_BUS 0x1898
120 #define CLK_CON_DIV_CLKCMU_PERIC0_IP 0x189c
121 #define CLK_CON_DIV_CLKCMU_PERIC1_BUS 0x18a0
122 #define CLK_CON_DIV_CLKCMU_PERIC1_IP 0x18a4
123 #define CLK_CON_DIV_CLKCMU_PERIS_BUS 0x18a8
124 #define CLK_CON_DIV_DIV_CLKCMU_CMU_BOOST 0x18b4
126 #define CLK_CON_DIV_PLL_SHARED0_DIV2 0x18b8
127 #define CLK_CON_DIV_PLL_SHARED0_DIV3 0x18bc
128 #define CLK_CON_DIV_PLL_SHARED1_DIV2 0x18c0
129 #define CLK_CON_DIV_PLL_SHARED1_DIV3 0x18c4
130 #define CLK_CON_DIV_PLL_SHARED1_DIV4 0x18c8
131 #define CLK_CON_DIV_PLL_SHARED2_DIV2 0x18cc
132 #define CLK_CON_DIV_PLL_SHARED2_DIV3 0x18d0
133 #define CLK_CON_DIV_PLL_SHARED2_DIV4 0x18d4
134 #define CLK_CON_DIV_PLL_SHARED4_DIV2 0x18d4
135 #define CLK_CON_DIV_PLL_SHARED4_DIV4 0x18d8
138 #define CLK_CON_GAT_CLKCMU_CMU_BUSC_BOOST 0x2000
139 #define CLK_CON_GAT_CLKCMU_CMU_BUSMC_BOOST 0x2004
140 #define CLK_CON_GAT_CLKCMU_CMU_CORE_BOOST 0x2008
141 #define CLK_CON_GAT_CLKCMU_CMU_CPUCL0_BOOST 0x2010
142 #define CLK_CON_GAT_CLKCMU_CMU_CPUCL1_BOOST 0x2018
143 #define CLK_CON_GAT_CLKCMU_CMU_MIF_BOOST 0x2020
144 #define CLK_CON_GAT_GATE_CLKCMU_FSYS1_MMC_CARD 0x2024
145 #define CLK_CON_GAT_GATE_CLKCMU_MIF_SWITCH 0x2028
146 #define CLK_CON_GAT_GATE_CLKCMU_ACC_BUS 0x202c
147 #define CLK_CON_GAT_GATE_CLKCMU_APM_BUS 0x2030
148 #define CLK_CON_GAT_GATE_CLKCMU_AUD_BUS 0x2034
149 #define CLK_CON_GAT_GATE_CLKCMU_AUD_CPU 0x2038
150 #define CLK_CON_GAT_GATE_CLKCMU_BUSC_BUS 0x203c
151 #define CLK_CON_GAT_GATE_CLKCMU_BUSMC_BUS 0x2044
152 #define CLK_CON_GAT_GATE_CLKCMU_CMU_BOOST 0x2048
153 #define CLK_CON_GAT_GATE_CLKCMU_CORE_BUS 0x204c
154 #define CLK_CON_GAT_GATE_CLKCMU_CPUCL0_CLUSTER 0x2050
155 #define CLK_CON_GAT_GATE_CLKCMU_CPUCL0_SWITCH 0x2058
156 #define CLK_CON_GAT_GATE_CLKCMU_CPUCL1_CLUSTER 0x205c
157 #define CLK_CON_GAT_GATE_CLKCMU_CPUCL1_SWITCH 0x2060
158 #define CLK_CON_GAT_GATE_CLKCMU_DPTX_BUS 0x206c
159 #define CLK_CON_GAT_GATE_CLKCMU_DPTX_DPGTC 0x2070
160 #define CLK_CON_GAT_GATE_CLKCMU_DPUM_BUS 0x2060
161 #define CLK_CON_GAT_GATE_CLKCMU_DPUS0_BUS 0x2064
162 #define CLK_CON_GAT_GATE_CLKCMU_DPUS1_BUS 0x207c
163 #define CLK_CON_GAT_GATE_CLKCMU_FSYS0_BUS 0x2080
164 #define CLK_CON_GAT_GATE_CLKCMU_FSYS0_PCIE 0x2084
165 #define CLK_CON_GAT_GATE_CLKCMU_FSYS1_BUS 0x2088
166 #define CLK_CON_GAT_GATE_CLKCMU_FSYS1_USBDRD 0x208c
167 #define CLK_CON_GAT_GATE_CLKCMU_FSYS2_BUS 0x2090
168 #define CLK_CON_GAT_GATE_CLKCMU_FSYS2_ETHERNET 0x2094
169 #define CLK_CON_GAT_GATE_CLKCMU_FSYS2_UFS_EMBD 0x2098
170 #define CLK_CON_GAT_GATE_CLKCMU_G2D_G2D 0x209c
171 #define CLK_CON_GAT_GATE_CLKCMU_G2D_MSCL 0x20a0
172 #define CLK_CON_GAT_GATE_CLKCMU_G3D00_SWITCH 0x20a4
173 #define CLK_CON_GAT_GATE_CLKCMU_G3D01_SWITCH 0x20a8
174 #define CLK_CON_GAT_GATE_CLKCMU_G3D1_SWITCH 0x20ac
175 #define CLK_CON_GAT_GATE_CLKCMU_ISPB_BUS 0x20b4
176 #define CLK_CON_GAT_GATE_CLKCMU_MFC_MFC 0x20b8
177 #define CLK_CON_GAT_GATE_CLKCMU_MFC_WFD 0x20bc
178 #define CLK_CON_GAT_GATE_CLKCMU_MIF_BUSP 0x20c0
179 #define CLK_CON_GAT_GATE_CLKCMU_NPU_BUS 0x20c4
180 #define CLK_CON_GAT_GATE_CLKCMU_PERIC0_BUS 0x20c8
181 #define CLK_CON_GAT_GATE_CLKCMU_PERIC0_IP 0x20cc
182 #define CLK_CON_GAT_GATE_CLKCMU_PERIC1_BUS 0x20d0
183 #define CLK_CON_GAT_GATE_CLKCMU_PERIC1_IP 0x20d4
184 #define CLK_CON_GAT_GATE_CLKCMU_PERIS_BUS 0x20d8
446 mout_clkcmu_cmu_boost_p, CLK_CON_MUX_MUX_CLKCMU_CMU_BOOST, 0, 2),
448 mout_clkcmu_cmu_cmuref_p, CLK_CON_MUX_MUX_CMU_CMUREF, 0, 1),
452 CLK_CON_MUX_MUX_CLKCMU_ACC_BUS, 0, 2),
456 CLK_CON_MUX_MUX_CLKCMU_APM_BUS, 0, 2),
460 CLK_CON_MUX_MUX_CLKCMU_AUD_CPU, 0, 3),
462 CLK_CON_MUX_MUX_CLKCMU_AUD_BUS, 0, 2),
466 mout_clkcmu_busc_bus_p, CLK_CON_MUX_MUX_CLKCMU_BUSC_BUS, 0, 2),
470 mout_clkcmu_busc_bus_p, CLK_CON_MUX_MUX_CLKCMU_BUSMC_BUS, 0, 2),
474 mout_clkcmu_core_bus_p, CLK_CON_MUX_MUX_CLKCMU_CORE_BUS, 0, 3),
479 0, 2),
482 CLK_CON_MUX_MUX_CLKCMU_CPUCL0_CLUSTER, 0, 3),
487 0, 2),
490 CLK_CON_MUX_MUX_CLKCMU_CPUCL1_CLUSTER, 0, 3),
494 mout_clkcmu_dptx_bus_p, CLK_CON_MUX_MUX_CLKCMU_DPTX_BUS, 0, 2),
496 mout_clkcmu_dptx_dpgtc_p, CLK_CON_MUX_MUX_CLKCMU_DPTX_DPGTC, 0, 2),
500 mout_clkcmu_dpum_bus_p, CLK_CON_MUX_MUX_CLKCMU_DPUM_BUS, 0, 3),
504 mout_clkcmu_dpum_bus_p, CLK_CON_MUX_MUX_CLKCMU_DPUS0_BUS, 0, 3),
506 mout_clkcmu_dpum_bus_p, CLK_CON_MUX_MUX_CLKCMU_DPUS1_BUS, 0, 3),
510 mout_clkcmu_fsys0_bus_p, CLK_CON_MUX_MUX_CLKCMU_FSYS0_BUS, 0, 2),
512 mout_clkcmu_fsys0_pcie_p, CLK_CON_MUX_MUX_CLKCMU_FSYS0_PCIE, 0, 1),
516 mout_clkcmu_fsys1_bus_p, CLK_CON_MUX_MUX_CLKCMU_FSYS1_BUS, 0, 2),
519 0, 2),
522 CLK_CON_MUX_MUX_CLKCMU_FSYS1_MMC_CARD, 0, 2),
526 mout_clkcmu_fsys0_bus_p, CLK_CON_MUX_MUX_CLKCMU_FSYS2_BUS, 0, 2),
529 0, 2),
532 CLK_CON_MUX_MUX_CLKCMU_FSYS2_ETHERNET, 0, 3),
536 CLK_CON_MUX_MUX_CLKCMU_G2D_G2D, 0, 3),
538 mout_clkcmu_fsys1_bus_p, CLK_CON_MUX_MUX_CLKCMU_G2D_MSCL, 0, 2),
543 0, 2),
546 0, 2),
551 0, 2),
555 mout_clkcmu_acc_bus_p, CLK_CON_MUX_MUX_CLKCMU_ISPB_BUS, 0, 2),
559 mout_clkcmu_g3d1_switch_p, CLK_CON_MUX_MUX_CLKCMU_MFC_MFC, 0, 2),
561 mout_clkcmu_fsys0_bus_p, CLK_CON_MUX_MUX_CLKCMU_MFC_WFD, 0, 2),
565 mout_clkcmu_mif_switch_p, CLK_CON_MUX_MUX_CLKCMU_MIF_SWITCH, 0, 3),
567 mout_clkcmu_fsys1_bus_p, CLK_CON_MUX_MUX_CLKCMU_MIF_BUSP, 0, 2),
571 CLK_CON_MUX_MUX_CLKCMU_NPU_BUS, 0, 3),
575 mout_clkcmu_peric0_bus_p, CLK_CON_MUX_MUX_CLKCMU_PERIC0_BUS, 0, 1),
577 mout_clkcmu_peric0_bus_p, CLK_CON_MUX_MUX_CLKCMU_PERIC0_IP, 0, 1),
581 mout_clkcmu_peric0_bus_p, CLK_CON_MUX_MUX_CLKCMU_PERIC1_BUS, 0, 1),
583 mout_clkcmu_peric0_bus_p, CLK_CON_MUX_MUX_CLKCMU_PERIC1_IP, 0, 1),
587 mout_clkcmu_peric0_bus_p, CLK_CON_MUX_MUX_CLKCMU_PERIS_BUS, 0, 1),
593 CLK_CON_DIV_PLL_SHARED0_DIV3, 0, 2),
595 CLK_CON_DIV_PLL_SHARED0_DIV2, 0, 1),
598 CLK_CON_DIV_PLL_SHARED1_DIV3, 0, 2),
600 CLK_CON_DIV_PLL_SHARED1_DIV2, 0, 1),
602 CLK_CON_DIV_PLL_SHARED1_DIV4, 0, 1),
605 CLK_CON_DIV_PLL_SHARED2_DIV3, 0, 2),
607 CLK_CON_DIV_PLL_SHARED2_DIV2, 0, 1),
609 CLK_CON_DIV_PLL_SHARED2_DIV4, 0, 1),
612 CLK_CON_DIV_PLL_SHARED4_DIV2, 0, 1),
614 CLK_CON_DIV_PLL_SHARED4_DIV4, 0, 1),
618 "gout_clkcmu_cmu_boost", CLK_CON_DIV_DIV_CLKCMU_CMU_BOOST, 0, 2),
622 CLK_CON_DIV_CLKCMU_ACC_BUS, 0, 4),
626 CLK_CON_DIV_CLKCMU_APM_BUS, 0, 3),
630 CLK_CON_DIV_CLKCMU_AUD_CPU, 0, 3),
632 CLK_CON_DIV_CLKCMU_AUD_BUS, 0, 4),
636 "gout_clkcmu_busc_bus", CLK_CON_DIV_CLKCMU_BUSC_BUS, 0, 4),
640 "gout_clkcmu_busmc_bus", CLK_CON_DIV_CLKCMU_BUSMC_BUS, 0, 4),
644 "gout_clkcmu_core_bus", CLK_CON_DIV_CLKCMU_CORE_BUS, 0, 4),
649 0, 3),
652 0, 3),
657 0, 3),
660 0, 3),
664 "gout_clkcmu_dptx_bus", CLK_CON_DIV_CLKCMU_DPTX_BUS, 0, 4),
666 "gout_clkcmu_dptx_dpgtc", CLK_CON_DIV_CLKCMU_DPTX_DPGTC, 0, 3),
670 "gout_clkcmu_dpum_bus", CLK_CON_DIV_CLKCMU_DPUM_BUS, 0, 4),
674 "gout_clkcmu_dpus0_bus", CLK_CON_DIV_CLKCMU_DPUS0_BUS, 0, 4),
676 "gout_clkcmu_dpus1_bus", CLK_CON_DIV_CLKCMU_DPUS1_BUS, 0, 4),
680 "gout_clkcmu_fsys0_bus", CLK_CON_DIV_CLKCMU_FSYS0_BUS, 0, 4),
684 "gout_clkcmu_fsys1_bus", CLK_CON_DIV_CLKCMU_FSYS1_BUS, 0, 4),
686 "gout_clkcmu_fsys1_usbdrd", CLK_CON_DIV_CLKCMU_FSYS1_USBDRD, 0, 4),
690 "gout_clkcmu_fsys2_bus", CLK_CON_DIV_CLKCMU_FSYS2_BUS, 0, 4),
693 0, 3),
696 0, 3),
700 CLK_CON_DIV_CLKCMU_G2D_G2D, 0, 4),
702 "gout_clkcmu_g2d_mscl", CLK_CON_DIV_CLKCMU_G2D_MSCL, 0, 4),
706 "gout_clkcmu_g3d00_switch", CLK_CON_DIV_CLKCMU_G3D00_SWITCH, 0, 3),
708 "gout_clkcmu_g3d01_switch", CLK_CON_DIV_CLKCMU_G3D01_SWITCH, 0, 3),
712 "gout_clkcmu_g3d1_switch", CLK_CON_DIV_CLKCMU_G3D1_SWITCH, 0, 3),
716 "gout_clkcmu_ispb_bus", CLK_CON_DIV_CLKCMU_ISPB_BUS, 0, 4),
720 CLK_CON_DIV_CLKCMU_MFC_MFC, 0, 4),
722 CLK_CON_DIV_CLKCMU_MFC_WFD, 0, 4),
726 "gout_clkcmu_mif_busp", CLK_CON_DIV_CLKCMU_MIF_BUSP, 0, 4),
730 CLK_CON_DIV_CLKCMU_NPU_BUS, 0, 4),
734 "gout_clkcmu_peric0_bus", CLK_CON_DIV_CLKCMU_PERIC0_BUS, 0, 4),
736 "gout_clkcmu_peric0_ip", CLK_CON_DIV_CLKCMU_PERIC0_IP, 0, 4),
740 "gout_clkcmu_peric1_bus", CLK_CON_DIV_CLKCMU_PERIC1_BUS, 0, 4),
742 "gout_clkcmu_peric1_ip", CLK_CON_DIV_CLKCMU_PERIC1_IP, 0, 4),
746 "gout_clkcmu_peris_bus", CLK_CON_DIV_CLKCMU_PERIS_BUS, 0, 4),
751 "gout_clkcmu_fsys0_pcie", 1, 4, 0),
758 21, 0, 0),
761 "dout_cmu_boost", CLK_CON_GAT_CLKCMU_CMU_CPUCL0_BOOST, 21, 0, 0),
763 "dout_cmu_boost", CLK_CON_GAT_CLKCMU_CMU_CPUCL1_BOOST, 21, 0, 0),
765 "dout_cmu_boost", CLK_CON_GAT_CLKCMU_CMU_CORE_BOOST, 21, 0, 0),
767 "dout_cmu_boost", CLK_CON_GAT_CLKCMU_CMU_BUSC_BOOST, 21, 0, 0),
770 "dout_cmu_boost", CLK_CON_GAT_CLKCMU_CMU_BUSMC_BOOST, 21, 0, 0),
772 CLK_CON_GAT_CLKCMU_CMU_MIF_BOOST, 21, 0, 0),
776 CLK_CON_GAT_GATE_CLKCMU_ACC_BUS, 21, 0, 0),
780 CLK_CON_GAT_GATE_CLKCMU_APM_BUS, 21, CLK_IGNORE_UNUSED, 0),
784 CLK_CON_GAT_GATE_CLKCMU_AUD_CPU, 21, 0, 0),
786 CLK_CON_GAT_GATE_CLKCMU_AUD_BUS, 21, 0, 0),
791 CLK_IS_CRITICAL, 0),
796 CLK_IS_CRITICAL, 0),
801 21, 0, 0),
806 CLK_CON_GAT_GATE_CLKCMU_CPUCL0_SWITCH, 21, CLK_IGNORE_UNUSED, 0),
809 CLK_CON_GAT_GATE_CLKCMU_CPUCL0_CLUSTER, 21, CLK_IGNORE_UNUSED, 0),
814 CLK_CON_GAT_GATE_CLKCMU_CPUCL1_SWITCH, 21, CLK_IGNORE_UNUSED, 0),
817 CLK_CON_GAT_GATE_CLKCMU_CPUCL1_CLUSTER, 21, CLK_IGNORE_UNUSED, 0),
822 21, 0, 0),
825 21, 0, 0),
830 21, 0, 0),
835 21, 0, 0),
838 21, 0, 0),
843 21, 0, 0),
846 21, 0, 0),
851 21, 0, 0),
854 21, 0, 0),
857 CLK_CON_GAT_GATE_CLKCMU_FSYS1_MMC_CARD, 21, 0, 0),
862 21, 0, 0),
865 CLK_CON_GAT_GATE_CLKCMU_FSYS2_UFS_EMBD, 21, 0, 0),
868 CLK_CON_GAT_GATE_CLKCMU_FSYS2_ETHERNET, 21, 0, 0),
872 "mout_clkcmu_g2d_g2d", CLK_CON_GAT_GATE_CLKCMU_G2D_G2D, 21, 0, 0),
875 21, 0, 0),
880 21, 0, 0),
883 21, 0, 0),
888 21, 0, 0),
893 21, 0, 0),
897 CLK_CON_GAT_GATE_CLKCMU_MFC_MFC, 21, 0, 0),
899 CLK_CON_GAT_GATE_CLKCMU_MFC_WFD, 21, 0, 0),
904 21, CLK_IGNORE_UNUSED, 0),
907 21, CLK_IGNORE_UNUSED, 0),
911 CLK_CON_GAT_GATE_CLKCMU_NPU_BUS, 21, 0, 0),
916 21, 0, 0),
919 21, 0, 0),
924 21, 0, 0),
927 21, 0, 0),
932 21, CLK_IGNORE_UNUSED, 0),
962 /* Register Offset definitions for CMU_BUSMC (0x1b200000) */
963 #define PLL_CON0_MUX_CLKCMU_BUSMC_BUS_USER 0x0600
964 #define CLK_CON_DIV_DIV_CLK_BUSMC_BUSP 0x1800
965 #define CLK_CON_GAT_GOUT_BLK_BUSMC_UID_QE_PDMA0_IPCLKPORT_PCLK 0x2078
966 #define CLK_CON_GAT_GOUT_BLK_BUSMC_UID_QE_SPDMA_IPCLKPORT_PCLK 0x2080
985 CLK_CON_DIV_DIV_CLK_BUSMC_BUSP, 0, 3),
992 0, 0),
996 0, 0),
1014 /* Register Offset definitions for CMU_CORE (0x1b030000) */
1015 #define PLL_CON0_MUX_CLKCMU_CORE_BUS_USER 0x0600
1016 #define CLK_CON_MUX_MUX_CORE_CMUREF 0x1000
1017 #define CLK_CON_DIV_DIV_CLK_CORE_BUSP 0x1800
1018 #define CLK_CON_GAT_CLK_BLK_CORE_UID_CCI_IPCLKPORT_CLK 0x2000
1019 #define CLK_CON_GAT_CLK_BLK_CORE_UID_CCI_IPCLKPORT_PCLK 0x2004
1020 #define CLK_CON_GAT_CLK_BLK_CORE_UID_CORE_CMU_CORE_IPCLKPORT_PCLK 0x2008
1041 CLK_CON_DIV_DIV_CLK_CORE_BUSP, 0, 3),
1047 CLK_IS_CRITICAL, 0),
1050 CLK_IS_CRITICAL, 0),
1054 CLK_IS_CRITICAL, 0),
1072 /* Register Offset definitions for CMU_FSYS2 (0x17700000) */
1073 #define PLL_CON0_MUX_CLKCMU_FSYS0_BUS_USER 0x0600
1074 #define PLL_CON0_MUX_CLKCMU_FSYS0_PCIE_USER 0x0610
1075 #define CLK_CON_GAT_CLK_BLK_FSYS0_UID_FSYS0_CMU_FSYS0_IPCLKPORT_PCLK 0x2000
1077 #define CLK_CON_GAT_CLK_BLK_FSYS0_UID_PCIE_GEN3_2L0_X1_PHY_REFCLK_IN 0x2004
1078 #define CLK_CON_GAT_CLK_BLK_FSYS0_UID_PCIE_GEN3_2L0_X2_PHY_REFCLK_IN 0x2008
1079 #define CLK_CON_GAT_CLK_BLK_FSYS0_UID_PCIE_GEN3_2L1_X1_PHY_REFCLK_IN 0x200c
1080 #define CLK_CON_GAT_CLK_BLK_FSYS0_UID_PCIE_GEN3_2L1_X2_PHY_REFCLK_IN 0x2010
1081 #define CLK_CON_GAT_CLK_BLK_FSYS0_UID_PCIE_GEN3_4L_X2_PHY_REFCLK_IN 0x2014
1082 #define CLK_CON_GAT_CLK_BLK_FSYS0_UID_PCIE_GEN3_4L_X4_PHY_REFCLK_IN 0x2018
1084 #define CLK_CON_GAT_GOUT_BLK_FSYS0_UID_PCIE_GEN3_2L0_X1_DBI_ACLK 0x205c
1085 #define CLK_CON_GAT_GOUT_BLK_FSYS0_UID_PCIE_GEN3_2L0_X1_MSTR_ACLK 0x2060
1086 #define CLK_CON_GAT_GOUT_BLK_FSYS0_UID_PCIE_GEN3_2L0_X1_SLV_ACLK 0x2064
1087 #define CLK_CON_GAT_GOUT_BLK_FSYS0_UID_PCIE_GEN3_2L0_X2_DBI_ACLK 0x206c
1088 #define CLK_CON_GAT_GOUT_BLK_FSYS0_UID_PCIE_GEN3_2L0_X2_MSTR_ACLK 0x2070
1089 #define CLK_CON_GAT_GOUT_BLK_FSYS0_UID_PCIE_GEN3_2L0_X2_SLV_ACLK 0x2074
1090 #define CLK_CON_GAT_GOUT_BLK_FSYS0_UID_PCIE_GEN3_2L0_X2_PIPE_CLK 0x207c
1092 #define CLK_CON_GAT_GOUT_BLK_FSYS0_UID_PCIE_GEN3_2L1_X1_DBI_ACLK 0x2084
1093 #define CLK_CON_GAT_GOUT_BLK_FSYS0_UID_PCIE_GEN3_2L1_X1_MSTR_ACLK 0x2088
1094 #define CLK_CON_GAT_GOUT_BLK_FSYS0_UID_PCIE_GEN3_2L1_X1_SLV_ACLK 0x208c
1095 #define CLK_CON_GAT_GOUT_BLK_FSYS0_UID_PCIE_GEN3_2L1_X2_DBI_ACLK 0x2094
1096 #define CLK_CON_GAT_GOUT_BLK_FSYS0_UID_PCIE_GEN3_2L1_X2_MSTR_ACLK 0x2098
1097 #define CLK_CON_GAT_GOUT_BLK_FSYS0_UID_PCIE_GEN3_2L1_X2_SLV_ACLK 0x209c
1098 #define CLK_CON_GAT_GOUT_BLK_FSYS0_UID_PCIE_GEN3_2L1_X2_PIPE_CLK 0x20a4
1100 #define CLK_CON_GAT_GOUT_BLK_FSYS0_UID_PCIE_GEN3_4L_X2_DBI_ACLK 0x20ac
1101 #define CLK_CON_GAT_GOUT_BLK_FSYS0_UID_PCIE_GEN3_4L_X2_MSTR_ACLK 0x20b0
1102 #define CLK_CON_GAT_GOUT_BLK_FSYS0_UID_PCIE_GEN3_4L_X2_SLV_ACLK 0x20b4
1103 #define CLK_CON_GAT_GOUT_BLK_FSYS0_UID_PCIE_GEN3_4L_X4_DBI_ACLK 0x20bc
1104 #define CLK_CON_GAT_GOUT_BLK_FSYS0_UID_PCIE_GEN3_4L_X4_MSTR_ACLK 0x20c0
1105 #define CLK_CON_GAT_GOUT_BLK_FSYS0_UID_PCIE_GEN3_4L_X4_SLV_ACLK 0x20c4
1106 #define CLK_CON_GAT_GOUT_BLK_FSYS0_UID_PCIE_GEN3_4L_X4_PIPE_CLK 0x20cc
1108 #define CLK_CON_GAT_GOUT_BLK_FSYS0_UID_PCIE_GEN3A_2L0_CLK 0x20d4
1109 #define CLK_CON_GAT_GOUT_BLK_FSYS0_UID_PCIE_GEN3A_2L1_CLK 0x20d8
1110 #define CLK_CON_GAT_GOUT_BLK_FSYS0_UID_PCIE_GEN3A_4L_CLK 0x20dc
1111 #define CLK_CON_GAT_GOUT_BLK_FSYS0_UID_PCIE_GEN3B_2L0_CLK 0x20e0
1112 #define CLK_CON_GAT_GOUT_BLK_FSYS0_UID_PCIE_GEN3B_2L1_CLK 0x20e4
1113 #define CLK_CON_GAT_GOUT_BLK_FSYS0_UID_PCIE_GEN3B_4L_CLK 0x20e8
1170 21, CLK_IGNORE_UNUSED, 0),
1176 21, 0, 0),
1180 21, 0, 0),
1184 21, 0, 0),
1188 21, 0, 0),
1192 21, 0, 0),
1196 21, 0, 0),
1200 21, 0, 0),
1204 21, 0, 0),
1208 21, 0, 0),
1212 21, 0, 0),
1218 21, 0, 0),
1222 21, 0, 0),
1226 21, 0, 0),
1230 21, 0, 0),
1234 21, 0, 0),
1238 21, 0, 0),
1242 21, 0, 0),
1246 21, 0, 0),
1250 21, 0, 0),
1254 21, 0, 0),
1260 21, 0, 0),
1264 21, 0, 0),
1268 21, 0, 0),
1272 21, 0, 0),
1276 21, 0, 0),
1280 21, 0, 0),
1284 21, 0, 0),
1288 21, 0, 0),
1292 21, 0, 0),
1296 21, 0, 0),
1312 /* Register Offset definitions for CMU_FSYS1 (0x17040000) */
1313 #define PLL_LOCKTIME_PLL_MMC 0x0000
1314 #define PLL_CON0_PLL_MMC 0x0100
1315 #define PLL_CON3_PLL_MMC 0x010c
1316 #define PLL_CON0_MUX_CLKCMU_FSYS1_BUS_USER 0x0600
1317 #define PLL_CON0_MUX_CLKCMU_FSYS1_MMC_CARD_USER 0x0610
1318 #define PLL_CON0_MUX_CLKCMU_FSYS1_USBDRD_USER 0x0620
1320 #define CLK_CON_MUX_MUX_CLK_FSYS1_MMC_CARD 0x1000
1321 #define CLK_CON_DIV_DIV_CLK_FSYS1_MMC_CARD 0x1800
1323 #define CLK_CON_GAT_GOUT_BLK_FSYS1_UID_FSYS1_CMU_FSYS1_IPCLKPORT_PCLK 0x2018
1324 #define CLK_CON_GAT_GOUT_BLK_FSYS1_UID_MMC_CARD_IPCLKPORT_SDCLKIN 0x202c
1325 #define CLK_CON_GAT_GOUT_BLK_FSYS1_UID_MMC_CARD_IPCLKPORT_I_ACLK 0x2028
1327 #define CLK_CON_GAT_GOUT_BLK_FSYS1_UID_USB20DRD_0_REF_CLK_40 0x204c
1328 #define CLK_CON_GAT_GOUT_BLK_FSYS1_UID_USB20DRD_1_REF_CLK_40 0x2058
1329 #define CLK_CON_GAT_GOUT_BLK_FSYS1_UID_USB30DRD_0_REF_CLK_40 0x2064
1330 #define CLK_CON_GAT_GOUT_BLK_FSYS1_UID_USB30DRD_1_REF_CLK_40 0x2070
1332 #define CLK_CON_GAT_GOUT_BLK_FSYS1_UID_US_D_USB2_0_IPCLKPORT_ACLK 0x2074
1333 #define CLK_CON_GAT_GOUT_BLK_FSYS1_UID_US_D_USB2_1_IPCLKPORT_ACLK 0x2078
1334 #define CLK_CON_GAT_GOUT_BLK_FSYS1_UID_US_D_USB3_0_IPCLKPORT_ACLK 0x207c
1335 #define CLK_CON_GAT_GOUT_BLK_FSYS1_UID_US_D_USB3_1_IPCLKPORT_ACLK 0x2080
1367 0, 1),
1373 CLK_CON_DIV_DIV_CLK_FSYS1_MMC_CARD, 0, 9),
1379 21, CLK_IGNORE_UNUSED, 0),
1383 21, CLK_SET_RATE_PARENT, 0),
1387 21, 0, 0),
1391 21, 0, 0),
1395 21, 0, 0),
1399 21, 0, 0),
1403 21, 0, 0),
1407 21, 0, 0),
1411 21, 0, 0),
1415 21, 0, 0),
1419 21, 0, 0),
1439 /* Register Offset definitions for CMU_FSYS2 (0x17c00000) */
1440 #define PLL_CON0_MUX_CLKCMU_FSYS2_BUS_USER 0x0600
1441 #define PLL_CON0_MUX_CLKCMU_FSYS2_UFS_EMBD_USER 0x0620
1442 #define PLL_CON0_MUX_CLKCMU_FSYS2_ETHERNET_USER 0x0610
1443 #define CLK_CON_GAT_GOUT_BLK_FSYS2_UID_UFS_EMBD0_IPCLKPORT_I_ACLK 0x2098
1444 #define CLK_CON_GAT_GOUT_BLK_FSYS2_UID_UFS_EMBD0_IPCLKPORT_I_CLK_UNIPRO 0x209c
1445 #define CLK_CON_GAT_GOUT_BLK_FSYS2_UID_UFS_EMBD1_IPCLKPORT_I_ACLK 0x20a4
1446 #define CLK_CON_GAT_GOUT_BLK_FSYS2_UID_UFS_EMBD1_IPCLKPORT_I_CLK_UNIPRO 0x20a8
1478 0, 0),
1482 21, 0, 0),
1486 0, 0),
1490 21, 0, 0),
1506 /* Register Offset definitions for CMU_PERIC0 (0x10200000) */
1507 #define PLL_CON0_MUX_CLKCMU_PERIC0_BUS_USER 0x0600
1508 #define PLL_CON0_MUX_CLKCMU_PERIC0_IP_USER 0x0610
1509 #define CLK_CON_MUX_MUX_CLK_PERIC0_USI00_USI 0x1000
1510 #define CLK_CON_MUX_MUX_CLK_PERIC0_USI01_USI 0x1004
1511 #define CLK_CON_MUX_MUX_CLK_PERIC0_USI02_USI 0x1008
1512 #define CLK_CON_MUX_MUX_CLK_PERIC0_USI03_USI 0x100c
1513 #define CLK_CON_MUX_MUX_CLK_PERIC0_USI04_USI 0x1010
1514 #define CLK_CON_MUX_MUX_CLK_PERIC0_USI05_USI 0x1014
1515 #define CLK_CON_MUX_MUX_CLK_PERIC0_USI_I2C 0x1018
1516 #define CLK_CON_DIV_DIV_CLK_PERIC0_USI00_USI 0x1800
1517 #define CLK_CON_DIV_DIV_CLK_PERIC0_USI01_USI 0x1804
1518 #define CLK_CON_DIV_DIV_CLK_PERIC0_USI02_USI 0x1808
1519 #define CLK_CON_DIV_DIV_CLK_PERIC0_USI03_USI 0x180c
1520 #define CLK_CON_DIV_DIV_CLK_PERIC0_USI04_USI 0x1810
1521 #define CLK_CON_DIV_DIV_CLK_PERIC0_USI05_USI 0x1814
1522 #define CLK_CON_DIV_DIV_CLK_PERIC0_USI_I2C 0x1818
1523 #define CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_IPCLK_0 0x2014
1524 #define CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_IPCLK_1 0x2018
1525 #define CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_IPCLK_2 0x2024
1526 #define CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_IPCLK_3 0x2028
1527 #define CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_IPCLK_4 0x202c
1528 #define CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_IPCLK_5 0x2030
1529 #define CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_IPCLK_6 0x2034
1530 #define CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_IPCLK_7 0x2038
1531 #define CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_IPCLK_8 0x203c
1532 #define CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_IPCLK_9 0x2040
1533 #define CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_IPCLK_10 0x201c
1534 #define CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_IPCLK_11 0x2020
1535 #define CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_PCLK_0 0x2044
1536 #define CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_PCLK_1 0x2048
1537 #define CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_PCLK_2 0x2058
1538 #define CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_PCLK_3 0x205c
1539 #define CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_PCLK_4 0x2060
1540 #define CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_PCLK_5 0x2064
1541 #define CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_PCLK_6 0x2068
1542 #define CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_PCLK_7 0x206c
1543 #define CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_PCLK_8 0x2070
1544 #define CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_PCLK_9 0x2074
1545 #define CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_PCLK_10 0x204c
1546 #define CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_PCLK_11 0x2050
1603 mout_peric0_usi_p, CLK_CON_MUX_MUX_CLK_PERIC0_USI00_USI, 0, 1),
1605 mout_peric0_usi_p, CLK_CON_MUX_MUX_CLK_PERIC0_USI01_USI, 0, 1),
1607 mout_peric0_usi_p, CLK_CON_MUX_MUX_CLK_PERIC0_USI02_USI, 0, 1),
1609 mout_peric0_usi_p, CLK_CON_MUX_MUX_CLK_PERIC0_USI03_USI, 0, 1),
1611 mout_peric0_usi_p, CLK_CON_MUX_MUX_CLK_PERIC0_USI04_USI, 0, 1),
1613 mout_peric0_usi_p, CLK_CON_MUX_MUX_CLK_PERIC0_USI05_USI, 0, 1),
1616 mout_peric0_usi_p, CLK_CON_MUX_MUX_CLK_PERIC0_USI_I2C, 0, 1),
1623 0, 4),
1626 0, 4),
1629 0, 4),
1632 0, 4),
1635 0, 4),
1638 0, 4),
1641 "mout_peric0_usi_i2c", CLK_CON_DIV_DIV_CLK_PERIC0_USI_I2C, 0, 4),
1649 21, 0, 0),
1653 21, 0, 0),
1657 21, 0, 0),
1661 21, 0, 0),
1665 21, 0, 0),
1669 21, 0, 0),
1673 21, 0, 0),
1677 21, 0, 0),
1681 21, 0, 0),
1685 21, 0, 0),
1689 21, 0, 0),
1693 21, 0, 0),
1699 21, 0, 0),
1703 21, 0, 0),
1707 21, 0, 0),
1711 21, 0, 0),
1715 21, 0, 0),
1719 21, 0, 0),
1723 21, 0, 0),
1727 21, 0, 0),
1731 21, 0, 0),
1735 21, 0, 0),
1739 21, 0, 0),
1743 21, 0, 0),
1761 /* Register Offset definitions for CMU_PERIC1 (0x10800000) */
1762 #define PLL_CON0_MUX_CLKCMU_PERIC1_BUS_USER 0x0600
1763 #define PLL_CON0_MUX_CLKCMU_PERIC1_IP_USER 0x0610
1764 #define CLK_CON_MUX_MUX_CLK_PERIC1_USI06_USI 0x1000
1765 #define CLK_CON_MUX_MUX_CLK_PERIC1_USI07_USI 0x1004
1766 #define CLK_CON_MUX_MUX_CLK_PERIC1_USI08_USI 0x1008
1767 #define CLK_CON_MUX_MUX_CLK_PERIC1_USI09_USI 0x100c
1768 #define CLK_CON_MUX_MUX_CLK_PERIC1_USI10_USI 0x1010
1769 #define CLK_CON_MUX_MUX_CLK_PERIC1_USI11_USI 0x1014
1770 #define CLK_CON_MUX_MUX_CLK_PERIC1_USI_I2C 0x1018
1771 #define CLK_CON_DIV_DIV_CLK_PERIC1_USI06_USI 0x1800
1772 #define CLK_CON_DIV_DIV_CLK_PERIC1_USI07_USI 0x1804
1773 #define CLK_CON_DIV_DIV_CLK_PERIC1_USI08_USI 0x1808
1774 #define CLK_CON_DIV_DIV_CLK_PERIC1_USI09_USI 0x180c
1775 #define CLK_CON_DIV_DIV_CLK_PERIC1_USI10_USI 0x1810
1776 #define CLK_CON_DIV_DIV_CLK_PERIC1_USI11_USI 0x1814
1777 #define CLK_CON_DIV_DIV_CLK_PERIC1_USI_I2C 0x1818
1778 #define CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_IPCLK_0 0x2014
1779 #define CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_IPCLK_1 0x2018
1780 #define CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_IPCLK_2 0x2024
1781 #define CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_IPCLK_3 0x2028
1782 #define CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_IPCLK_4 0x202c
1783 #define CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_IPCLK_5 0x2030
1784 #define CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_IPCLK_6 0x2034
1785 #define CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_IPCLK_7 0x2038
1786 #define CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_IPCLK_8 0x203c
1787 #define CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_IPCLK_9 0x2040
1788 #define CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_IPCLK_10 0x201c
1789 #define CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_IPCLK_11 0x2020
1790 #define CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_PCLK_0 0x2044
1791 #define CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_PCLK_1 0x2048
1792 #define CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_PCLK_2 0x2054
1793 #define CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_PCLK_3 0x2058
1794 #define CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_PCLK_4 0x205c
1795 #define CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_PCLK_5 0x2060
1796 #define CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_PCLK_6 0x2064
1797 #define CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_PCLK_7 0x2068
1798 #define CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_PCLK_8 0x206c
1799 #define CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_PCLK_9 0x2070
1800 #define CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_PCLK_10 0x204c
1801 #define CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_PCLK_11 0x2050
1858 mout_peric1_usi_p, CLK_CON_MUX_MUX_CLK_PERIC1_USI06_USI, 0, 1),
1860 mout_peric1_usi_p, CLK_CON_MUX_MUX_CLK_PERIC1_USI07_USI, 0, 1),
1862 mout_peric1_usi_p, CLK_CON_MUX_MUX_CLK_PERIC1_USI08_USI, 0, 1),
1864 mout_peric1_usi_p, CLK_CON_MUX_MUX_CLK_PERIC1_USI09_USI, 0, 1),
1866 mout_peric1_usi_p, CLK_CON_MUX_MUX_CLK_PERIC1_USI10_USI, 0, 1),
1868 mout_peric1_usi_p, CLK_CON_MUX_MUX_CLK_PERIC1_USI11_USI, 0, 1),
1871 mout_peric1_usi_p, CLK_CON_MUX_MUX_CLK_PERIC1_USI_I2C, 0, 1),
1878 0, 4),
1881 0, 4),
1884 0, 4),
1887 0, 4),
1890 0, 4),
1893 0, 4),
1896 "mout_peric1_usi_i2c", CLK_CON_DIV_DIV_CLK_PERIC1_USI_I2C, 0, 4),
1904 21, 0, 0),
1908 21, 0, 0),
1912 21, 0, 0),
1916 21, 0, 0),
1920 21, 0, 0),
1924 21, 0, 0),
1928 21, 0, 0),
1932 21, 0, 0),
1936 21, 0, 0),
1940 21, 0, 0),
1944 21, 0, 0),
1948 21, 0, 0),
1954 21, 0, 0),
1958 21, 0, 0),
1962 21, 0, 0),
1966 21, 0, 0),
1970 21, 0, 0),
1974 21, 0, 0),
1978 21, 0, 0),
1982 21, 0, 0),
1986 21, 0, 0),
1990 21, 0, 0),
1994 21, 0, 0),
1998 21, 0, 0),
2016 /* Register Offset definitions for CMU_PERIS (0x10020000) */
2017 #define PLL_CON0_MUX_CLKCMU_PERIS_BUS_USER 0x0600
2018 #define CLK_CON_GAT_GOUT_BLK_PERIS_UID_SYSREG_PERIS_IPCLKPORT_PCLK 0x2058
2019 #define CLK_CON_GAT_GOUT_BLK_PERIS_UID_WDT_CLUSTER0_IPCLKPORT_PCLK 0x205c
2020 #define CLK_CON_GAT_GOUT_BLK_PERIS_UID_WDT_CLUSTER1_IPCLKPORT_PCLK 0x2060
2041 21, CLK_IGNORE_UNUSED, 0),
2044 21, 0, 0),
2047 21, 0, 0),
2069 return 0; in exynosautov9_cmu_probe()