Lines Matching +full:0 +full:x3b00
64 { 0x0, 1 },
65 { 0x1, 2 },
66 { 0x3, 4 },
67 { 0x7, 8 },
72 .offset = 0xc000,
75 .enable_reg = 0x1e0,
76 .enable_mask = BIT(0),
89 .offset = 0xc000,
104 .offset = 0xc050,
107 .enable_reg = 0x1e0,
121 .offset = 0xc050,
136 .offset = 0x0,
149 .offset = 0x0,
164 .offset = 0x50,
177 .offset = 0x50,
192 .offset = 0xa0,
205 .offset = 0xa0,
220 .offset = 0xf0,
233 .offset = 0xf0,
248 .offset = 0x140,
261 .offset = 0x140,
276 .offset = 0x190,
289 .offset = 0x190,
304 { P_XO, 0 },
316 { P_XO, 0 },
330 { P_XO, 0 },
344 { P_XO, 0 },
358 { P_XO, 0 },
372 { P_XO, 0 },
388 { P_XO, 0 },
406 { P_XO, 0 },
424 { P_XO, 0 },
444 { P_XO, 0 },
464 { P_XO, 0 },
484 { P_XO, 0 },
506 .cmd_rcgr = 0x2120,
519 .cmd_rcgr = 0x2140,
532 F(37500000, P_GPLL0, 16, 0, 0),
533 F(50000000, P_GPLL0, 12, 0, 0),
534 F(100000000, P_GPLL0, 6, 0, 0),
539 .cmd_rcgr = 0x3300,
552 F(100000000, P_GPLL0, 6, 0, 0),
553 F(200000000, P_GPLL0, 3, 0, 0),
554 F(384000000, P_MMPLL4_OUT_EVEN, 2, 0, 0),
555 F(404000000, P_MMPLL0_OUT_EVEN, 2, 0, 0),
556 F(480000000, P_MMPLL7_OUT_EVEN, 2, 0, 0),
557 F(576000000, P_MMPLL10_OUT_EVEN, 1, 0, 0),
558 F(600000000, P_GPLL0, 1, 0, 0),
563 .cmd_rcgr = 0x3640,
576 F(164571429, P_MMPLL10_OUT_EVEN, 3.5, 0, 0),
577 F(256000000, P_MMPLL4_OUT_EVEN, 3, 0, 0),
578 F(274290000, P_MMPLL7_OUT_EVEN, 3.5, 0, 0),
579 F(300000000, P_GPLL0, 2, 0, 0),
580 F(384000000, P_MMPLL4_OUT_EVEN, 2, 0, 0),
581 F(576000000, P_MMPLL10_OUT_EVEN, 1, 0, 0),
586 .cmd_rcgr = 0x3090,
599 .cmd_rcgr = 0x3100,
612 .cmd_rcgr = 0x3160,
625 .cmd_rcgr = 0x31c0,
638 F(164571429, P_MMPLL10_OUT_EVEN, 3.5, 0, 0),
639 F(256000000, P_MMPLL4_OUT_EVEN, 3, 0, 0),
640 F(274290000, P_MMPLL7_OUT_EVEN, 3.5, 0, 0),
641 F(300000000, P_GPLL0, 2, 0, 0),
642 F(384000000, P_MMPLL4_OUT_EVEN, 2, 0, 0),
647 .cmd_rcgr = 0x3800,
660 F(200000000, P_GPLL0, 3, 0, 0),
661 F(269333333, P_MMPLL0_OUT_EVEN, 3, 0, 0),
666 .cmd_rcgr = 0x3000,
679 .cmd_rcgr = 0x3030,
692 .cmd_rcgr = 0x3060,
705 F(19200000, P_XO, 1, 0, 0),
710 .cmd_rcgr = 0x2260,
730 .cmd_rcgr = 0x2220,
743 F(162000, P_DPLINK, 2, 0, 0),
744 F(270000, P_DPLINK, 2, 0, 0),
745 F(540000, P_DPLINK, 2, 0, 0),
750 .cmd_rcgr = 0x2200,
763 F(154000000, P_DPVCO, 1, 0, 0),
764 F(337500000, P_DPVCO, 2, 0, 0),
765 F(675000000, P_DPVCO, 2, 0, 0),
770 .cmd_rcgr = 0x2240,
783 F(19200000, P_XO, 1, 0, 0),
788 .cmd_rcgr = 0x2160,
801 .cmd_rcgr = 0x2180,
819 .cmd_rcgr = 0x2060,
833 F(100000000, P_GPLL0, 6, 0, 0),
834 F(200000000, P_GPLL0, 3, 0, 0),
835 F(404000000, P_MMPLL0_OUT_EVEN, 2, 0, 0),
836 F(480000000, P_MMPLL7_OUT_EVEN, 2, 0, 0),
837 F(576000000, P_MMPLL10_OUT_EVEN, 1, 0, 0),
842 .cmd_rcgr = 0x3b00,
855 F(19200000, P_XO, 1, 0, 0),
860 .cmd_rcgr = 0x2100,
873 F(75000000, P_GPLL0, 8, 0, 0),
874 F(150000000, P_GPLL0, 4, 0, 0),
875 F(320000000, P_MMPLL7_OUT_EVEN, 3, 0, 0),
876 F(480000000, P_MMPLL7_OUT_EVEN, 2, 0, 0),
881 .cmd_rcgr = 0x3500,
894 F(19200000, P_XO, 1, 0, 0),
895 F(75000000, P_GPLL0_DIV, 4, 0, 0),
896 F(171428571, P_GPLL0, 3.5, 0, 0),
897 F(323200000, P_MMPLL0_OUT_EVEN, 2.5, 0, 0),
898 F(406000000, P_MMPLL1_OUT_EVEN, 2, 0, 0),
903 .cmd_rcgr = 0xf020,
916 F(4800000, P_XO, 4, 0, 0),
919 F(9600000, P_XO, 2, 0, 0),
921 F(19200000, P_XO, 1, 0, 0),
930 .cmd_rcgr = 0x3360,
943 .cmd_rcgr = 0x3390,
956 .cmd_rcgr = 0x33c0,
969 .cmd_rcgr = 0x33f0,
982 F(85714286, P_GPLL0, 7, 0, 0),
983 F(100000000, P_GPLL0, 6, 0, 0),
984 F(150000000, P_GPLL0, 4, 0, 0),
985 F(171428571, P_GPLL0, 3.5, 0, 0),
986 F(200000000, P_GPLL0, 3, 0, 0),
987 F(275000000, P_MMPLL5_OUT_EVEN, 3, 0, 0),
988 F(300000000, P_GPLL0, 2, 0, 0),
989 F(330000000, P_MMPLL5_OUT_EVEN, 2.5, 0, 0),
990 F(412500000, P_MMPLL5_OUT_EVEN, 2, 0, 0),
995 .cmd_rcgr = 0x2040,
1008 F(19200000, P_XO, 1, 0, 0),
1013 .cmd_rcgr = 0x2080,
1026 F(19200000, P_XO, 1, 0, 0),
1027 F(40000000, P_GPLL0, 15, 0, 0),
1028 F(80800000, P_MMPLL0_OUT_EVEN, 10, 0, 0),
1033 .cmd_rcgr = 0x5000,
1046 F(75000000, P_GPLL0, 8, 0, 0),
1047 F(171428571, P_GPLL0, 3.5, 0, 0),
1048 F(240000000, P_GPLL0, 2.5, 0, 0),
1049 F(323200000, P_MMPLL0_OUT_EVEN, 2.5, 0, 0),
1050 F(406000000, P_MMPLL0_OUT_EVEN, 2, 0, 0),
1056 .cmd_rcgr = 0xd000,
1069 .cmd_rcgr = 0x2000,
1083 .cmd_rcgr = 0x2020,
1097 F(171428571, P_GPLL0, 3.5, 0, 0),
1098 F(275000000, P_MMPLL5_OUT_EVEN, 3, 0, 0),
1099 F(330000000, P_MMPLL5_OUT_EVEN, 2.5, 0, 0),
1100 F(412500000, P_MMPLL5_OUT_EVEN, 2, 0, 0),
1105 .cmd_rcgr = 0x21a0,
1118 F(200000000, P_GPLL0, 3, 0, 0),
1119 F(269330000, P_MMPLL0_OUT_EVEN, 3, 0, 0),
1120 F(355200000, P_MMPLL6_OUT_EVEN, 2.5, 0, 0),
1121 F(444000000, P_MMPLL6_OUT_EVEN, 2, 0, 0),
1122 F(533000000, P_MMPLL3_OUT_EVEN, 2, 0, 0),
1127 .cmd_rcgr = 0x1000,
1140 .cmd_rcgr = 0x1060,
1153 .cmd_rcgr = 0x1080,
1166 F(200000000, P_GPLL0, 3, 0, 0),
1167 F(300000000, P_GPLL0, 2, 0, 0),
1168 F(320000000, P_MMPLL7_OUT_EVEN, 3, 0, 0),
1169 F(384000000, P_MMPLL4_OUT_EVEN, 2, 0, 0),
1170 F(404000000, P_MMPLL0_OUT_EVEN, 2, 0, 0),
1171 F(480000000, P_MMPLL7_OUT_EVEN, 2, 0, 0),
1172 F(576000000, P_MMPLL10_OUT_EVEN, 1, 0, 0),
1173 F(600000000, P_GPLL0, 1, 0, 0),
1178 .cmd_rcgr = 0x3600,
1191 .cmd_rcgr = 0x3620,
1204 .halt_reg = 0x328,
1205 .hwcg_reg = 0x328,
1208 .enable_reg = 0x328,
1209 .enable_mask = BIT(0),
1221 .halt_reg = 0x1028,
1223 .enable_reg = 0x1028,
1224 .enable_mask = BIT(0),
1236 .halt_reg = 0x1030,
1237 .hwcg_reg = 0x1030,
1240 .enable_reg = 0x1030,
1241 .enable_mask = BIT(0),
1253 .halt_reg = 0x1034,
1255 .enable_reg = 0x1034,
1256 .enable_mask = BIT(0),
1267 .halt_reg = 0x1038,
1269 .enable_reg = 0x1038,
1270 .enable_mask = BIT(0),
1282 .halt_reg = 0x1048,
1284 .enable_reg = 0x1048,
1285 .enable_mask = BIT(0),
1297 .halt_reg = 0x104c,
1299 .enable_reg = 0x104c,
1300 .enable_mask = BIT(0),
1312 .halt_reg = 0x2308,
1313 .hwcg_reg = 0x2308,
1316 .enable_reg = 0x2308,
1317 .enable_mask = BIT(0),
1329 .halt_reg = 0x230c,
1331 .enable_reg = 0x230c,
1332 .enable_mask = BIT(0),
1344 .halt_reg = 0x2310,
1346 .enable_reg = 0x2310,
1347 .enable_mask = BIT(0),
1358 .halt_reg = 0x2314,
1360 .enable_reg = 0x2314,
1361 .enable_mask = BIT(0),
1373 .halt_reg = 0x2318,
1375 .enable_reg = 0x2318,
1376 .enable_mask = BIT(0),
1388 .halt_reg = 0x231c,
1390 .enable_reg = 0x231c,
1391 .enable_mask = BIT(0),
1403 .halt_reg = 0x2320,
1405 .enable_reg = 0x2320,
1406 .enable_mask = BIT(0),
1418 .halt_reg = 0x2324,
1420 .enable_reg = 0x2324,
1421 .enable_mask = BIT(0),
1433 .halt_reg = 0x2328,
1435 .enable_reg = 0x2328,
1436 .enable_mask = BIT(0),
1448 .halt_reg = 0x2338,
1450 .enable_reg = 0x2338,
1451 .enable_mask = BIT(0),
1463 .halt_reg = 0x233c,
1465 .enable_reg = 0x233c,
1466 .enable_mask = BIT(0),
1478 .halt_reg = 0x2340,
1480 .enable_reg = 0x2340,
1481 .enable_mask = BIT(0),
1493 .halt_reg = 0x2344,
1495 .enable_reg = 0x2344,
1496 .enable_mask = BIT(0),
1508 .halt_reg = 0x2348,
1510 .enable_reg = 0x2348,
1511 .enable_mask = BIT(0),
1523 .halt_reg = 0x2350,
1525 .enable_reg = 0x2350,
1526 .enable_mask = BIT(0),
1538 .halt_reg = 0x2354,
1540 .enable_reg = 0x2354,
1541 .enable_mask = BIT(0),
1553 .halt_reg = 0x2358,
1555 .enable_reg = 0x2358,
1556 .enable_mask = BIT(0),
1568 .halt_reg = 0x235c,
1570 .enable_reg = 0x235c,
1571 .enable_mask = BIT(0),
1583 .halt_reg = 0x2360,
1585 .enable_reg = 0x2360,
1586 .enable_mask = BIT(0),
1598 .halt_reg = 0x2364,
1600 .enable_reg = 0x2364,
1601 .enable_mask = BIT(0),
1613 .halt_reg = 0x2374,
1615 .enable_reg = 0x2374,
1616 .enable_mask = BIT(0),
1628 .halt_reg = 0x2378,
1630 .enable_reg = 0x2378,
1631 .enable_mask = BIT(0),
1643 .halt_reg = 0x3024,
1645 .enable_reg = 0x3024,
1646 .enable_mask = BIT(0),
1658 .halt_reg = 0x3054,
1660 .enable_reg = 0x3054,
1661 .enable_mask = BIT(0),
1673 .halt_reg = 0x3084,
1675 .enable_reg = 0x3084,
1676 .enable_mask = BIT(0),
1688 .halt_reg = 0x30b4,
1690 .enable_reg = 0x30b4,
1691 .enable_mask = BIT(0),
1703 .halt_reg = 0x30bc,
1705 .enable_reg = 0x30bc,
1706 .enable_mask = BIT(0),
1718 .halt_reg = 0x30d4,
1720 .enable_reg = 0x30d4,
1721 .enable_mask = BIT(0),
1733 .halt_reg = 0x30e4,
1735 .enable_reg = 0x30e4,
1736 .enable_mask = BIT(0),
1748 .halt_reg = 0x3124,
1750 .enable_reg = 0x3124,
1751 .enable_mask = BIT(0),
1763 .halt_reg = 0x3128,
1765 .enable_reg = 0x3128,
1766 .enable_mask = BIT(0),
1778 .halt_reg = 0x3144,
1780 .enable_reg = 0x3144,
1781 .enable_mask = BIT(0),
1793 .halt_reg = 0x3154,
1795 .enable_reg = 0x3154,
1796 .enable_mask = BIT(0),
1808 .halt_reg = 0x3184,
1810 .enable_reg = 0x3184,
1811 .enable_mask = BIT(0),
1823 .halt_reg = 0x3188,
1825 .enable_reg = 0x3188,
1826 .enable_mask = BIT(0),
1838 .halt_reg = 0x31a4,
1840 .enable_reg = 0x31a4,
1841 .enable_mask = BIT(0),
1853 .halt_reg = 0x31b4,
1855 .enable_reg = 0x31b4,
1856 .enable_mask = BIT(0),
1868 .halt_reg = 0x31e4,
1870 .enable_reg = 0x31e4,
1871 .enable_mask = BIT(0),
1883 .halt_reg = 0x31e8,
1885 .enable_reg = 0x31e8,
1886 .enable_mask = BIT(0),
1898 .halt_reg = 0x3204,
1900 .enable_reg = 0x3204,
1901 .enable_mask = BIT(0),
1913 .halt_reg = 0x3214,
1915 .enable_reg = 0x3214,
1916 .enable_mask = BIT(0),
1928 .halt_reg = 0x3224,
1930 .enable_reg = 0x3224,
1931 .enable_mask = BIT(0),
1943 .halt_reg = 0x3344,
1945 .enable_reg = 0x3344,
1946 .enable_mask = BIT(0),
1958 .halt_reg = 0x3348,
1960 .enable_reg = 0x3348,
1961 .enable_mask = BIT(0),
1973 .halt_reg = 0x3384,
1975 .enable_reg = 0x3384,
1976 .enable_mask = BIT(0),
1988 .halt_reg = 0x33b4,
1990 .enable_reg = 0x33b4,
1991 .enable_mask = BIT(0),
2003 .halt_reg = 0x33e4,
2005 .enable_reg = 0x33e4,
2006 .enable_mask = BIT(0),
2018 .halt_reg = 0x3414,
2020 .enable_reg = 0x3414,
2021 .enable_mask = BIT(0),
2033 .halt_reg = 0x3484,
2035 .enable_reg = 0x3484,
2036 .enable_mask = BIT(0),
2048 .halt_reg = 0x348c,
2050 .enable_reg = 0x348c,
2051 .enable_mask = BIT(0),
2063 .halt_reg = 0x3494,
2065 .enable_reg = 0x3494,
2066 .enable_mask = BIT(0),
2078 .halt_reg = 0x35a8,
2080 .enable_reg = 0x35a8,
2081 .enable_mask = BIT(0),
2093 .halt_reg = 0x35b4,
2095 .enable_reg = 0x35b4,
2096 .enable_mask = BIT(0),
2108 .halt_reg = 0x35b8,
2110 .enable_reg = 0x35b8,
2111 .enable_mask = BIT(0),
2122 .halt_reg = 0x3668,
2124 .enable_reg = 0x3668,
2125 .enable_mask = BIT(0),
2137 .halt_reg = 0x3678,
2139 .enable_reg = 0x3678,
2140 .enable_mask = BIT(0),
2152 .halt_reg = 0x36a8,
2154 .enable_reg = 0x36a8,
2155 .enable_mask = BIT(0),
2167 .halt_reg = 0x36ac,
2169 .enable_reg = 0x36ac,
2170 .enable_mask = BIT(0),
2182 .halt_reg = 0x36b0,
2184 .enable_reg = 0x36b0,
2185 .enable_mask = BIT(0),
2197 .halt_reg = 0x36b4,
2199 .enable_reg = 0x36b4,
2200 .enable_mask = BIT(0),
2212 .halt_reg = 0x36b8,
2214 .enable_reg = 0x36b8,
2215 .enable_mask = BIT(0),
2227 .halt_reg = 0x36bc,
2229 .enable_reg = 0x36bc,
2230 .enable_mask = BIT(0),
2241 .halt_reg = 0x36c4,
2243 .enable_reg = 0x36c4,
2244 .enable_mask = BIT(0),
2255 .halt_reg = 0x36c8,
2257 .enable_reg = 0x36c8,
2258 .enable_mask = BIT(0),
2270 .halt_reg = 0x3704,
2272 .enable_reg = 0x3704,
2273 .enable_mask = BIT(0),
2285 .halt_reg = 0x3714,
2287 .enable_reg = 0x3714,
2288 .enable_mask = BIT(0),
2300 .halt_reg = 0x3720,
2302 .enable_reg = 0x3720,
2303 .enable_mask = BIT(0),
2315 .halt_reg = 0x3724,
2317 .enable_reg = 0x3724,
2318 .enable_mask = BIT(0),
2330 .halt_reg = 0x3730,
2332 .enable_reg = 0x3730,
2333 .enable_mask = BIT(0),
2345 .halt_reg = 0x3734,
2347 .enable_reg = 0x3734,
2348 .enable_mask = BIT(0),
2360 .halt_reg = 0x3738,
2362 .enable_reg = 0x3738,
2363 .enable_mask = BIT(0),
2375 .halt_reg = 0x373c,
2377 .enable_reg = 0x373c,
2378 .enable_mask = BIT(0),
2390 .halt_reg = 0x3740,
2392 .enable_reg = 0x3740,
2393 .enable_mask = BIT(0),
2405 .halt_reg = 0x3744,
2407 .enable_reg = 0x3744,
2408 .enable_mask = BIT(0),
2420 .halt_reg = 0x3748,
2422 .enable_reg = 0x3748,
2423 .enable_mask = BIT(0),
2435 .halt_reg = 0x3b68,
2437 .enable_reg = 0x3b68,
2438 .enable_mask = BIT(0),
2450 .halt_reg = 0x3b6c,
2452 .enable_reg = 0x3b6c,
2453 .enable_mask = BIT(0),
2465 .halt_reg = 0x3b74,
2467 .enable_reg = 0x3b74,
2468 .enable_mask = BIT(0),
2480 .halt_reg = 0x5024,
2482 .enable_reg = 0x5024,
2483 .enable_mask = BIT(0),
2495 .halt_reg = 0xe004,
2496 .hwcg_reg = 0xe004,
2499 .enable_reg = 0xe004,
2500 .enable_mask = BIT(0),
2512 .halt_reg = 0xe008,
2513 .hwcg_reg = 0xe008,
2516 .enable_reg = 0xe008,
2517 .enable_mask = BIT(0),
2528 .halt_reg = 0xf004,
2530 .enable_reg = 0xf004,
2531 .enable_mask = BIT(0),
2543 .halt_reg = 0xf064,
2545 .enable_reg = 0xf064,
2546 .enable_mask = BIT(0),
2558 .halt_reg = 0xf068,
2560 .enable_reg = 0xf068,
2561 .enable_mask = BIT(0),
2577 .gdscr = 0x1024,
2585 .gdscr = 0x1040,
2594 .gdscr = 0x1044,
2603 .gdscr = 0x2304,
2604 .cxcs = (unsigned int []){ 0x2310, 0x2350, 0x231c, 0x2320 },
2613 .gdscr = 0x34a0,
2614 .cxcs = (unsigned int []){ 0x35b8, 0x36c4, 0x3704, 0x3714, 0x3494,
2615 0x35a8, 0x3868 },
2624 .gdscr = 0x3664,
2633 .gdscr = 0x3674,
2642 .gdscr = 0x36d4,
2651 .gdscr = 0xe020,
2652 .gds_hw_ctrl = 0xe024,
2822 [SPDM_BCR] = { 0x200 },
2823 [SPDM_RM_BCR] = { 0x300 },
2824 [MISC_BCR] = { 0x320 },
2825 [VIDEO_TOP_BCR] = { 0x1020 },
2826 [THROTTLE_VIDEO_BCR] = { 0x1180 },
2827 [MDSS_BCR] = { 0x2300 },
2828 [THROTTLE_MDSS_BCR] = { 0x2460 },
2829 [CAMSS_PHY0_BCR] = { 0x3020 },
2830 [CAMSS_PHY1_BCR] = { 0x3050 },
2831 [CAMSS_PHY2_BCR] = { 0x3080 },
2832 [CAMSS_CSI0_BCR] = { 0x30b0 },
2833 [CAMSS_CSI0RDI_BCR] = { 0x30d0 },
2834 [CAMSS_CSI0PIX_BCR] = { 0x30e0 },
2835 [CAMSS_CSI1_BCR] = { 0x3120 },
2836 [CAMSS_CSI1RDI_BCR] = { 0x3140 },
2837 [CAMSS_CSI1PIX_BCR] = { 0x3150 },
2838 [CAMSS_CSI2_BCR] = { 0x3180 },
2839 [CAMSS_CSI2RDI_BCR] = { 0x31a0 },
2840 [CAMSS_CSI2PIX_BCR] = { 0x31b0 },
2841 [CAMSS_CSI3_BCR] = { 0x31e0 },
2842 [CAMSS_CSI3RDI_BCR] = { 0x3200 },
2843 [CAMSS_CSI3PIX_BCR] = { 0x3210 },
2844 [CAMSS_ISPIF_BCR] = { 0x3220 },
2845 [CAMSS_CCI_BCR] = { 0x3340 },
2846 [CAMSS_TOP_BCR] = { 0x3480 },
2847 [CAMSS_AHB_BCR] = { 0x3488 },
2848 [CAMSS_MICRO_BCR] = { 0x3490 },
2849 [CAMSS_JPEG_BCR] = { 0x35a0 },
2850 [CAMSS_VFE0_BCR] = { 0x3660 },
2851 [CAMSS_VFE1_BCR] = { 0x3670 },
2852 [CAMSS_VFE_VBIF_BCR] = { 0x36a0 },
2853 [CAMSS_CPP_TOP_BCR] = { 0x36c0 },
2854 [CAMSS_CPP_BCR] = { 0x36d0 },
2855 [CAMSS_CSI_VFE0_BCR] = { 0x3700 },
2856 [CAMSS_CSI_VFE1_BCR] = { 0x3710 },
2857 [CAMSS_FD_BCR] = { 0x3b60 },
2858 [THROTTLE_CAMSS_BCR] = { 0x3c30 },
2859 [MNOCAHB_BCR] = { 0x5020 },
2860 [MNOCAXI_BCR] = { 0xd020 },
2861 [BMIC_SMMU_BCR] = { 0xe000 },
2862 [MNOC_MAXI_BCR] = { 0xf000 },
2863 [VMEM_BCR] = { 0xf060 },
2864 [BTO_BCR] = { 0x10004 },
2871 .max_register = 0x10004,