Lines Matching refs:GATE_TOP1

528 #define GATE_TOP1(_id, _name, _parent, _shift) {	\  macro
584 	GATE_TOP1(CLK_TOP_THEM, "them", "ahb_infra_sel", 1),
585 	GATE_TOP1(CLK_TOP_APDMA, "apdma", "ahb_infra_sel", 2),
586 	GATE_TOP1(CLK_TOP_I2C0, "i2c0", "ifr_i2c0_sel", 3),
587 	GATE_TOP1(CLK_TOP_I2C1, "i2c1", "ifr_i2c1_sel", 4),
588 	GATE_TOP1(CLK_TOP_AUXADC1, "auxadc1", "ahb_infra_sel", 5),
589 	GATE_TOP1(CLK_TOP_NFI, "nfi", "nfi1x_pad_sel", 6),
590 	GATE_TOP1(CLK_TOP_NFIECC, "nfiecc", "rg_nfiecc", 7),
591 	GATE_TOP1(CLK_TOP_DEBUGSYS, "debugsys", "rg_dbg_atclk", 8),
592 	GATE_TOP1(CLK_TOP_PWM, "pwm", "ahb_infra_sel", 9),
593 	GATE_TOP1(CLK_TOP_UART0, "uart0", "uart0_sel", 10),
594 	GATE_TOP1(CLK_TOP_UART1, "uart1", "uart1_sel", 11),
595 	GATE_TOP1(CLK_TOP_BTIF, "btif", "ahb_infra_sel", 12),
596 	GATE_TOP1(CLK_TOP_USB, "usb", "usb_78m", 13),
597 	GATE_TOP1(CLK_TOP_FLASHIF_26M, "flashif_26m", "clk26m_ck", 14),
598 	GATE_TOP1(CLK_TOP_AUXADC2, "auxadc2", "ahb_infra_sel", 15),
599 	GATE_TOP1(CLK_TOP_I2C2, "i2c2", "ifr_i2c2_sel", 16),
600 	GATE_TOP1(CLK_TOP_MSDC0, "msdc0", "msdc0_sel", 17),
601 	GATE_TOP1(CLK_TOP_MSDC1, "msdc1", "msdc1_sel", 18),
602 	GATE_TOP1(CLK_TOP_NFI2X, "nfi2x", "nfi2x_pad_sel", 19),
603 	GATE_TOP1(CLK_TOP_PMICWRAP_AP, "pwrap_ap", "clk26m_ck", 20),
604 	GATE_TOP1(CLK_TOP_SEJ, "sej", "ahb_infra_sel", 21),
605 	GATE_TOP1(CLK_TOP_MEMSLP_DLYER, "memslp_dlyer", "clk26m_ck", 22),
606 	GATE_TOP1(CLK_TOP_SPI, "spi", "spi_sel", 23),
607 	GATE_TOP1(CLK_TOP_APXGPT, "apxgpt", "clk26m_ck", 24),
608 	GATE_TOP1(CLK_TOP_AUDIO, "audio", "clk26m_ck", 25),
609 	GATE_TOP1(CLK_TOP_PMICWRAP_MD, "pwrap_md", "clk26m_ck", 27),
610 	GATE_TOP1(CLK_TOP_PMICWRAP_CONN, "pwrap_conn", "clk26m_ck", 28),
611 	GATE_TOP1(CLK_TOP_PMICWRAP_26M, "pwrap_26m", "clk26m_ck", 29),
612 	GATE_TOP1(CLK_TOP_AUX_ADC, "aux_adc", "clk26m_ck", 30),
613 	GATE_TOP1(CLK_TOP_AUX_TP, "aux_tp", "clk26m_ck", 31),