Lines Matching +full:mt8173 +full:- +full:infracfg

1 // SPDX-License-Identifier: GPL-2.0-only
11 #include "clk-cpumux.h"
12 #include "clk-gate.h"
13 #include "clk-mtk.h"
14 #include "clk-pll.h"
16 #include <dt-bindings/clock/mt8173-clk.h>
848 	clk_prepare_enable(mt8173_pll_clk_data->hws[CLK_APMIXED_ARMCA15PLL]->clk);  in mtk_clk_enable_critical()
849 	clk_prepare_enable(mt8173_pll_clk_data->hws[CLK_APMIXED_ARMCA7PLL]->clk);  in mtk_clk_enable_critical()
850 	clk_prepare_enable(mt8173_top_clk_data->hws[CLK_TOP_MEM_SEL]->clk);  in mtk_clk_enable_critical()
851 	clk_prepare_enable(mt8173_top_clk_data->hws[CLK_TOP_DDRPHYCFG_SEL]->clk);  in mtk_clk_enable_critical()
852 	clk_prepare_enable(mt8173_top_clk_data->hws[CLK_TOP_CCI400_SEL]->clk);  in mtk_clk_enable_critical()
853 	clk_prepare_enable(mt8173_top_clk_data->hws[CLK_TOP_RTC_SEL]->clk);  in mtk_clk_enable_critical()
882 CLK_OF_DECLARE(mtk_topckgen, "mediatek,mt8173-topckgen", mtk_topckgen_init);
905 CLK_OF_DECLARE(mtk_infrasys, "mediatek,mt8173-infracfg", mtk_infrasys_init);
933 CLK_OF_DECLARE(mtk_pericfg, "mediatek,mt8173-pericfg", mtk_pericfg_init);
1034 		hw = mtk_clk_register_ref2usb_tx(cku->name, cku->parent, base + cku->reg_ofs);  in mtk_apmixedsys_init()
1036 			pr_err("Failed to register clk %s: %ld\n", cku->name, PTR_ERR(hw));  in mtk_apmixedsys_init()
1040 		clk_data->hws[cku->id] = hw;  in mtk_apmixedsys_init()
1046 	clk_data->hws[CLK_APMIXED_HDMI_REF] = hw;  in mtk_apmixedsys_init()
1055 CLK_OF_DECLARE(mtk_apmixedsys, "mediatek,mt8173-apmixedsys",
1074 CLK_OF_DECLARE(mtk_imgsys, "mediatek,mt8173-imgsys", mtk_imgsys_init);
1091 CLK_OF_DECLARE(mtk_vdecsys, "mediatek,mt8173-vdecsys", mtk_vdecsys_init);
1108 CLK_OF_DECLARE(mtk_vencsys, "mediatek,mt8173-vencsys", mtk_vencsys_init);
1125 CLK_OF_DECLARE(mtk_vencltsys, "mediatek,mt8173-vencltsys", mtk_vencltsys_init);