Lines Matching +full:v1 +full:- +full:v6
1 /* SPDX-License-Identifier: GPL-2.0 */
3 * Hardware-accelerated CRC-32 variants for Linux on z Systems
6 * computing of bitreflected CRC-32 checksums for IEEE 802.3 Ethernet
9 * This CRC-32 implementation algorithm is bitreflected and processes
10 * the least-significant bit first (Little-Endian).
17 #include <asm/nospec-insn.h>
18 #include <asm/vx-insn.h>
20 /* Vector register range containing CRC-32 constants */
32 * The CRC-32 constant block contains reduction constants to fold and
35 * For the CRC-32 variants, the constants are precomputed according to
39 * R2 = [(x4*128-32 mod P'(x) << 32)]' << 1
41 * R4 = [(x128-32 mod P'(x) << 32)]' << 1
51 * CRC-32 (IEEE 802.3 Ethernet, ...) polynomials:
56 * CRC-32C (Castagnoli) polynomials:
63 .octa 0x0F0E0D0C0B0A09080706050403020100 # BE->LE mask
71 .octa 0x0F0E0D0C0B0A09080706050403020100 # BE->LE mask
85 * The CRC-32 functions use these calling conventions:
96 * %r5: CRC-32 constant pool base pointer.
98 * V1..V4: Data for CRC computation.
100 * V9: Constant for BE->LE conversion and shift operations
102 * V10..V14: CRC-32 constants.
116 /* Load CRC-32 constants */
129 /* Load a 64-byte data chunk and XOR with CRC */
130 VLM %v1,%v4,0,%r3 /* 64-bytes into V1..V4 */
131 VPERM %v1,%v1,%v1,CONST_PERM_LE2BE
136 VX %v1,%v0,%v1 /* V1 ^= CRC */
138 aghi %r4,-64 /* LEN = LEN - 64 */
144 /* Load the next 64-byte data chunk into V5 to V8 */
147 VPERM %v6,%v6,%v6,CONST_PERM_LE2BE
152 * Perform a GF(2) multiplication of the doublewords in V1 with
155 * stored in V1. Repeat this step for the register contents
158 VGFMAG %v1,CONST_R2R1,%v1,%v5
159 VGFMAG %v2,CONST_R2R1,%v2,%v6
164 aghi %r4,-64 /* LEN = LEN - 64 */
171 * Fold V1 to V4 into a single 128-bit value in V1. Multiply V1 with R3
172 * and R4 and accumulating the next 128-bit chunk until a single 128-bit
175 VGFMAG %v1,CONST_R4R3,%v1,%v2
176 VGFMAG %v1,CONST_R4R3,%v1,%v3
177 VGFMAG %v1,CONST_R4R3,%v1,%v4
186 VGFMAG %v1,CONST_R4R3,%v1,%v2 /* Fold next data chunk */
189 aghi %r4,-16
197 * be loaded in bits 1-4 in byte element 7 of a vector register.
212 * Compute GF(2) product of V1 and V0. The rightmost doubleword
213 * of V1 is multiplied with R4. The leftmost doubleword of V1 is
217 VGFMG %v1,%v0,%v1
220 * Now do the final 32-bit fold by multiplying the rightmost word
221 * in V1 with R5 and XOR the result with the remaining bits in V1.
223 * To achieve this by a single VGFMAG, right shift V1 by a word
226 * doubleword into the rightmost doubleword element of V1; the other
230 * the leftmost product of V1.
233 VSRLB %v2,%v1,%v9 /* Store remaining bits in V2 */
234 VUPLLF %v1,%v1 /* Split rightmost doubleword */
235 VGFMAG %v1,CONST_R5,%v1,%v2 /* V1 = (V1 * R5) XOR V2 */
238 * Apply a Barret reduction to compute the final 32-bit CRC value.
240 * The input values to the Barret reduction are the degree-63 polynomial
241 * in V1 (R(x)), degree-32 generator polynomial, and the reduction
257 VUPLLF %v2,%v1
262 * V2 and XOR the intermediate result, T2(x), with the value in V1.
266 VGFMAG %v2,CONST_CRC_POLY,%v2,%v1