Lines Matching full:v1
98 * V1..V4: Data for CRC computation.
130 VLM %v1,%v4,0,%r3 /* 64-bytes into V1..V4 */
131 VPERM %v1,%v1,%v1,CONST_PERM_LE2BE
136 VX %v1,%v0,%v1 /* V1 ^= CRC */
152 * Perform a GF(2) multiplication of the doublewords in V1 with
155 * stored in V1. Repeat this step for the register contents
158 VGFMAG %v1,CONST_R2R1,%v1,%v5
171 * Fold V1 to V4 into a single 128-bit value in V1. Multiply V1 with R3
175 VGFMAG %v1,CONST_R4R3,%v1,%v2
176 VGFMAG %v1,CONST_R4R3,%v1,%v3
177 VGFMAG %v1,CONST_R4R3,%v1,%v4
186 VGFMAG %v1,CONST_R4R3,%v1,%v2 /* Fold next data chunk */
212 * Compute GF(2) product of V1 and V0. The rightmost doubleword
213 * of V1 is multiplied with R4. The leftmost doubleword of V1 is
217 VGFMG %v1,%v0,%v1
221 * in V1 with R5 and XOR the result with the remaining bits in V1.
223 * To achieve this by a single VGFMAG, right shift V1 by a word
226 * doubleword into the rightmost doubleword element of V1; the other
230 * the leftmost product of V1.
233 VSRLB %v2,%v1,%v9 /* Store remaining bits in V2 */
234 VUPLLF %v1,%v1 /* Split rightmost doubleword */
235 VGFMAG %v1,CONST_R5,%v1,%v2 /* V1 = (V1 * R5) XOR V2 */
241 * in V1 (R(x)), degree-32 generator polynomial, and the reduction
257 VUPLLF %v2,%v1
262 * V2 and XOR the intermediate result, T2(x), with the value in V1.
266 VGFMAG %v2,CONST_CRC_POLY,%v2,%v1