Lines Matching +full:gcc +full:- +full:msm8994
1 // SPDX-License-Identifier: GPL-2.0-only
2 /* Copyright (c) 2013-2016, The Linux Foundation. All rights reserved.
5 #include <dt-bindings/interrupt-controller/arm-gic.h>
6 #include <dt-bindings/clock/qcom,gcc-msm8994.h>
7 #include <dt-bindings/clock/qcom,mmcc-msm8994.h>
8 #include <dt-bindings/clock/qcom,rpmcc.h>
9 #include <dt-bindings/gpio/gpio.h>
10 #include <dt-bindings/power/qcom-rpmpd.h>
13 interrupt-parent = <&intc>;
15 #address-cells = <2>;
16 #size-cells = <2>;
26 xo_board: xo-board {
27 compatible = "fixed-clock";
28 #clock-cells = <0>;
29 clock-frequency = <19200000>;
30 clock-output-names = "xo_board";
33 sleep_clk: sleep-clk {
34 compatible = "fixed-clock";
35 #clock-cells = <0>;
36 clock-frequency = <32768>;
37 clock-output-names = "sleep_clk";
42 #address-cells = <2>;
43 #size-cells = <0>;
47 compatible = "arm,cortex-a53";
49 enable-method = "psci";
50 next-level-cache = <&L2_0>;
51 L2_0: l2-cache {
53 cache-level = <2>;
59 compatible = "arm,cortex-a53";
61 enable-method = "psci";
62 next-level-cache = <&L2_0>;
67 compatible = "arm,cortex-a53";
69 enable-method = "psci";
70 next-level-cache = <&L2_0>;
75 compatible = "arm,cortex-a53";
77 enable-method = "psci";
78 next-level-cache = <&L2_0>;
83 compatible = "arm,cortex-a57";
85 enable-method = "psci";
86 next-level-cache = <&L2_1>;
87 L2_1: l2-cache {
89 cache-level = <2>;
95 compatible = "arm,cortex-a57";
97 enable-method = "psci";
98 next-level-cache = <&L2_1>;
103 compatible = "arm,cortex-a57";
105 enable-method = "psci";
106 next-level-cache = <&L2_1>;
111 compatible = "arm,cortex-a57";
113 enable-method = "psci";
114 next-level-cache = <&L2_1>;
117 cpu-map {
158 compatible = "qcom,scm-msm8994", "qcom,scm";
169 compatible = "arm,cortex-a53-pmu";
174 compatible = "arm,psci-0.2";
178 reserved-memory {
179 #address-cells = <2>;
180 #size-cells = <2>;
185 no-map;
190 no-map;
195 no-map;
200 no-map;
205 no-map;
209 compatible = "qcom,rmtfs-mem";
211 no-map;
213 qcom,client-id = <1>;
218 no-map;
223 no-map;
228 no-map;
237 qcom,smd-edge = <15>;
238 qcom,remote-pid = <6>;
240 rpm_requests: rpm-requests {
241 compatible = "qcom,rpm-msm8994";
242 qcom,smd-channels = "rpm_requests";
245 compatible = "qcom,rpmcc-msm8994", "qcom,rpmcc";
246 #clock-cells = <1>;
249 rpmpd: power-controller {
250 compatible = "qcom,msm8994-rpmpd";
251 #power-domain-cells = <1>;
252 operating-points-v2 = <&rpmpd_opp_table>;
254 rpmpd_opp_table: opp-table {
255 compatible = "operating-points-v2";
258 opp-level = <1>;
261 opp-level = <2>;
264 opp-level = <3>;
267 opp-level = <4>;
270 opp-level = <5>;
273 opp-level = <6>;
283 memory-region = <&smem_mem>;
284 qcom,rpm-msg-ram = <&rpm_msg_ram>;
288 smp2p-lpass {
296 qcom,local-pid = <0>;
297 qcom,remote-pid = <2>;
299 adsp_smp2p_out: master-kernel {
300 qcom,entry-name = "master-kernel";
301 #qcom,smem-state-cells = <1>;
304 adsp_smp2p_in: slave-kernel {
305 qcom,entry-name = "slave-kernel";
307 interrupt-controller;
308 #interrupt-cells = <2>;
312 smp2p-modem {
316 interrupt-parent = <&intc>;
321 qcom,local-pid = <0>;
322 qcom,remote-pid = <1>;
324 modem_smp2p_out: master-kernel {
325 qcom,entry-name = "master-kernel";
326 #qcom,smem-state-cells = <1>;
329 modem_smp2p_in: slave-kernel {
330 qcom,entry-name = "slave-kernel";
332 interrupt-controller;
333 #interrupt-cells = <2>;
339 #address-cells = <1>;
340 #size-cells = <1>;
342 compatible = "simple-bus";
344 intc: interrupt-controller@f9000000 {
345 compatible = "qcom,msm-qgic2";
346 interrupt-controller;
347 #interrupt-cells = <3>;
353 compatible = "qcom,msm8994-apcs-kpss-global", "syscon";
355 #mbox-cells = <1>;
359 compatible = "qcom,apss-wdt-msm8994", "qcom,kpss-wdt";
364 timeout-sec = <10>;
368 #address-cells = <1>;
369 #size-cells = <1>;
371 compatible = "arm,armv7-timer-mem";
375 frame-number = <0>;
383 frame-number = <1>;
390 frame-number = <2>;
397 frame-number = <3>;
404 frame-number = <4>;
411 frame-number = <5>;
418 frame-number = <6>;
426 compatible = "qcom,msm8994-dwc3", "qcom,dwc3";
428 #address-cells = <1>;
429 #size-cells = <1>;
432 clocks = <&gcc GCC_USB30_MASTER_CLK>,
433 <&gcc GCC_SYS_NOC_USB3_AXI_CLK>,
434 <&gcc GCC_USB30_SLEEP_CLK>,
435 <&gcc GCC_USB30_MOCK_UTMI_CLK>;
436 clock-names = "core",
441 assigned-clocks = <&gcc GCC_USB30_MOCK_UTMI_CLK>,
442 <&gcc GCC_USB30_MASTER_CLK>;
443 assigned-clock-rates = <19200000>, <120000000>;
445 power-domains = <&gcc USB30_GDSC>;
446 qcom,select-utmi-as-pipe-clk;
454 maximum-speed = "high-speed";
460 compatible = "qcom,msm8994-sdhci", "qcom,sdhci-msm-v4";
462 reg-names = "hc", "core";
466 interrupt-names = "hc_irq", "pwr_irq";
468 clocks = <&gcc GCC_SDCC1_AHB_CLK>,
469 <&gcc GCC_SDCC1_APPS_CLK>,
471 clock-names = "iface", "core", "xo";
473 pinctrl-names = "default", "sleep";
474 pinctrl-0 = <&sdc1_clk_on &sdc1_cmd_on &sdc1_data_on &sdc1_rclk_on>;
475 pinctrl-1 = <&sdc1_clk_off &sdc1_cmd_off &sdc1_data_off &sdc1_rclk_off>;
477 bus-width = <8>;
478 non-removable;
483 compatible = "qcom,msm8994-sdhci", "qcom,sdhci-msm-v4";
485 reg-names = "hc", "core";
489 interrupt-names = "hc_irq", "pwr_irq";
491 clocks = <&gcc GCC_SDCC2_AHB_CLK>,
492 <&gcc GCC_SDCC2_APPS_CLK>,
494 clock-names = "iface", "core", "xo";
496 pinctrl-names = "default", "sleep";
497 pinctrl-0 = <&sdc2_clk_on &sdc2_cmd_on &sdc2_data_on>;
498 pinctrl-1 = <&sdc2_clk_off &sdc2_cmd_off &sdc2_data_off>;
500 cd-gpios = <&tlmm 100 GPIO_ACTIVE_HIGH>;
501 bus-width = <4>;
505 blsp1_dma: dma-controller@f9904000 {
506 compatible = "qcom,bam-v1.7.0";
509 clocks = <&gcc GCC_BLSP1_AHB_CLK>;
510 clock-names = "bam_clk";
511 #dma-cells = <1>;
513 qcom,controlled-remotely;
514 num-channels = <24>;
515 qcom,num-ees = <4>;
519 compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
522 clock-names = "core", "iface";
523 clocks = <&gcc GCC_BLSP1_UART2_APPS_CLK>,
524 <&gcc GCC_BLSP1_AHB_CLK>;
525 pinctrl-names = "default", "sleep";
526 pinctrl-0 = <&blsp1_uart2_default>;
527 pinctrl-1 = <&blsp1_uart2_sleep>;
532 compatible = "qcom,i2c-qup-v2.2.1";
535 clocks = <&gcc GCC_BLSP1_QUP1_I2C_APPS_CLK>,
536 <&gcc GCC_BLSP1_AHB_CLK>;
537 clock-names = "core", "iface";
538 clock-frequency = <400000>;
540 dma-names = "tx", "rx";
541 pinctrl-names = "default", "sleep";
542 pinctrl-0 = <&i2c1_default>;
543 pinctrl-1 = <&i2c1_sleep>;
544 #address-cells = <1>;
545 #size-cells = <0>;
550 compatible = "qcom,spi-qup-v2.2.1";
553 clocks = <&gcc GCC_BLSP1_QUP1_SPI_APPS_CLK>,
554 <&gcc GCC_BLSP1_AHB_CLK>;
555 clock-names = "core", "iface";
556 spi-max-frequency = <19200000>;
558 dma-names = "tx", "rx";
559 pinctrl-names = "default", "sleep";
560 pinctrl-0 = <&blsp1_spi1_default>;
561 pinctrl-1 = <&blsp1_spi1_sleep>;
562 #address-cells = <1>;
563 #size-cells = <0>;
568 compatible = "qcom,i2c-qup-v2.2.1";
571 clocks = <&gcc GCC_BLSP1_QUP2_I2C_APPS_CLK>,
572 <&gcc GCC_BLSP1_AHB_CLK>;
573 clock-names = "core", "iface";
574 clock-frequency = <400000>;
576 dma-names = "tx", "rx";
577 pinctrl-names = "default", "sleep";
578 pinctrl-0 = <&i2c2_default>;
579 pinctrl-1 = <&i2c2_sleep>;
580 #address-cells = <1>;
581 #size-cells = <0>;
588 compatible = "qcom,i2c-qup-v2.2.1";
591 clocks = <&gcc GCC_BLSP1_QUP4_I2C_APPS_CLK>,
592 <&gcc GCC_BLSP1_AHB_CLK>;
593 clock-names = "core", "iface";
594 clock-frequency = <400000>;
596 dma-names = "tx", "rx";
597 pinctrl-names = "default", "sleep";
598 pinctrl-0 = <&i2c4_default>;
599 pinctrl-1 = <&i2c4_sleep>;
600 #address-cells = <1>;
601 #size-cells = <0>;
606 compatible = "qcom,i2c-qup-v2.2.1";
609 clocks = <&gcc GCC_BLSP1_QUP5_I2C_APPS_CLK>,
610 <&gcc GCC_BLSP1_AHB_CLK>;
611 clock-names = "core", "iface";
612 clock-frequency = <400000>;
614 dma-names = "tx", "rx";
615 pinctrl-names = "default", "sleep";
616 pinctrl-0 = <&i2c5_default>;
617 pinctrl-1 = <&i2c5_sleep>;
618 #address-cells = <1>;
619 #size-cells = <0>;
624 compatible = "qcom,i2c-qup-v2.2.1";
627 clocks = <&gcc GCC_BLSP1_QUP6_I2C_APPS_CLK>,
628 <&gcc GCC_BLSP1_AHB_CLK>;
629 clock-names = "core", "iface";
630 clock-frequency = <400000>;
632 dma-names = "tx", "rx";
633 pinctrl-names = "default", "sleep";
634 pinctrl-0 = <&i2c6_default>;
635 pinctrl-1 = <&i2c6_sleep>;
636 #address-cells = <1>;
637 #size-cells = <0>;
641 blsp2_dma: dma-controller@f9944000 {
642 compatible = "qcom,bam-v1.7.0";
645 clocks = <&gcc GCC_BLSP2_AHB_CLK>;
646 clock-names = "bam_clk";
647 #dma-cells = <1>;
649 qcom,controlled-remotely;
650 num-channels = <24>;
651 qcom,num-ees = <4>;
655 compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
658 clock-names = "core", "iface";
659 clocks = <&gcc GCC_BLSP2_UART2_APPS_CLK>,
660 <&gcc GCC_BLSP2_AHB_CLK>;
662 dma-names = "tx", "rx";
663 pinctrl-names = "default", "sleep";
664 pinctrl-0 = <&blsp2_uart2_default>;
665 pinctrl-1 = <&blsp2_uart2_sleep>;
670 compatible = "qcom,i2c-qup-v2.2.1";
673 clocks = <&gcc GCC_BLSP2_QUP1_I2C_APPS_CLK>,
674 <&gcc GCC_BLSP2_AHB_CLK>;
675 clock-names = "core", "iface";
676 clock-frequency = <400000>;
678 dma-names = "tx", "rx";
679 pinctrl-names = "default", "sleep";
680 pinctrl-0 = <&i2c7_default>;
681 pinctrl-1 = <&i2c7_sleep>;
682 #address-cells = <1>;
683 #size-cells = <0>;
688 compatible = "qcom,spi-qup-v2.2.1";
691 clocks = <&gcc GCC_BLSP2_QUP4_SPI_APPS_CLK>,
692 <&gcc GCC_BLSP2_AHB_CLK>;
693 clock-names = "core", "iface";
694 spi-max-frequency = <19200000>;
696 dma-names = "tx", "rx";
697 pinctrl-names = "default", "sleep";
698 pinctrl-0 = <&blsp2_spi10_default>;
699 pinctrl-1 = <&blsp2_spi10_sleep>;
700 #address-cells = <1>;
701 #size-cells = <0>;
706 compatible = "qcom,i2c-qup-v2.2.1";
709 clocks = <&gcc GCC_BLSP2_QUP5_I2C_APPS_CLK>,
710 <&gcc GCC_BLSP2_AHB_CLK>;
711 clock-names = "core", "iface";
712 clock-frequency = <355000>;
714 dma-names = "tx", "rx";
715 pinctrl-names = "default", "sleep";
716 pinctrl-0 = <&i2c11_default>;
717 pinctrl-1 = <&i2c11_sleep>;
718 #address-cells = <1>;
719 #size-cells = <0>;
723 gcc: clock-controller@fc400000 { label
724 compatible = "qcom,gcc-msm8994";
725 #clock-cells = <1>;
726 #reset-cells = <1>;
727 #power-domain-cells = <1>;
730 clock-names = "xo", "sleep";
735 compatible = "qcom,rpm-msg-ram";
745 compatible = "qcom,spmi-pmic-arb";
749 reg-names = "core", "intr", "cnfg";
750 interrupt-names = "periph_irq";
754 #address-cells = <2>;
755 #size-cells = <0>;
756 interrupt-controller;
757 #interrupt-cells = <4>;
761 compatible = "qcom,msm8994-tcsr-mutex", "qcom,tcsr-mutex";
763 #hwlock-cells = <1>;
767 compatible = "qcom,msm8994-pinctrl";
770 gpio-controller;
771 gpio-ranges = <&tlmm 0 0 146>;
772 #gpio-cells = <2>;
773 interrupt-controller;
774 #interrupt-cells = <2>;
776 blsp1_uart2_default: blsp1-uart2-default {
779 drive-strength = <16>;
780 bias-disable;
783 blsp1_uart2_sleep: blsp1-uart2-sleep {
786 drive-strength = <2>;
787 bias-pull-down;
790 blsp2_uart2_default: blsp2-uart2-default {
794 drive-strength = <16>;
795 bias-disable;
798 blsp2_uart2_sleep: blsp2-uart2-sleep {
802 drive-strength = <2>;
803 bias-disable;
806 i2c1_default: i2c1-default {
809 drive-strength = <2>;
810 bias-disable;
813 i2c1_sleep: i2c1-sleep {
816 drive-strength = <2>;
817 bias-disable;
820 i2c2_default: i2c2-default {
823 drive-strength = <2>;
824 bias-disable;
827 i2c2_sleep: i2c2-sleep {
830 drive-strength = <2>;
831 bias-disable;
834 i2c4_default: i2c4-default {
837 drive-strength = <2>;
838 bias-disable;
841 i2c4_sleep: i2c4-sleep {
844 drive-strength = <2>;
845 bias-pull-down;
846 input-enable;
849 i2c5_default: i2c5-default {
852 drive-strength = <2>;
853 bias-disable;
856 i2c5_sleep: i2c5-sleep {
859 drive-strength = <2>;
860 bias-disable;
863 i2c6_default: i2c6-default {
866 drive-strength = <2>;
867 bias-disable;
870 i2c6_sleep: i2c6-sleep {
873 drive-strength = <2>;
874 bias-disable;
877 i2c7_default: i2c7-default {
880 drive-strength = <2>;
881 bias-disable;
884 i2c7_sleep: i2c7-sleep {
887 drive-strength = <2>;
888 bias-disable;
891 blsp2_spi10_default: blsp2-spi10-default {
895 drive-strength = <10>;
896 bias-pull-down;
901 drive-strength = <2>;
902 bias-disable;
906 blsp2_spi10_sleep: blsp2-spi10-sleep {
908 drive-strength = <2>;
909 bias-disable;
912 i2c11_default: i2c11-default {
915 drive-strength = <2>;
916 bias-disable;
919 i2c11_sleep: i2c11-sleep {
922 drive-strength = <2>;
923 bias-disable;
926 blsp1_spi1_default: blsp1-spi1-default {
930 drive-strength = <10>;
931 bias-pull-down;
936 drive-strength = <2>;
937 bias-disable;
941 blsp1_spi1_sleep: blsp1-spi1-sleep {
943 drive-strength = <2>;
944 bias-disable;
947 sdc1_clk_on: clk-on {
949 bias-disable;
950 drive-strength = <16>;
953 sdc1_clk_off: clk-off {
955 bias-disable;
956 drive-strength = <2>;
959 sdc1_cmd_on: cmd-on {
961 bias-pull-up;
962 drive-strength = <8>;
965 sdc1_cmd_off: cmd-off {
967 bias-pull-up;
968 drive-strength = <2>;
971 sdc1_data_on: data-on {
973 bias-pull-up;
974 drive-strength = <8>;
977 sdc1_data_off: data-off {
979 bias-pull-up;
980 drive-strength = <2>;
983 sdc1_rclk_on: rclk-on {
985 bias-pull-down;
988 sdc1_rclk_off: rclk-off {
990 bias-pull-down;
993 sdc2_clk_on: sdc2-clk-on {
995 bias-disable;
996 drive-strength = <10>;
999 sdc2_clk_off: sdc2-clk-off {
1001 bias-disable;
1002 drive-strength = <2>;
1005 sdc2_cmd_on: sdc2-cmd-on {
1007 bias-pull-up;
1008 drive-strength = <10>;
1011 sdc2_cmd_off: sdc2-cmd-off {
1013 bias-pull-up;
1014 drive-strength = <2>;
1017 sdc2_data_on: sdc2-data-on {
1019 bias-pull-up;
1020 drive-strength = <10>;
1023 sdc2_data_off: sdc2-data-off {
1025 bias-pull-up;
1026 drive-strength = <2>;
1030 mmcc: clock-controller@fd8c0000 {
1031 compatible = "qcom,mmcc-msm8994";
1033 #clock-cells = <1>;
1034 #reset-cells = <1>;
1035 #power-domain-cells = <1>;
1037 clock-names = "xo",
1047 <&gcc GPLL0_OUT_MMSSCC>,
1056 assigned-clocks = <&mmcc MMPLL0_PLL>,
1061 assigned-clock-rates = <800000000>,
1069 compatible = "qcom,msm8974-ocmem";
1072 reg-names = "ctrl", "mem";
1076 clock-names = "core", "iface";
1078 #address-cells = <1>;
1079 #size-cells = <1>;
1081 gmu_sram: gmu-sram@0 {
1088 compatible = "arm,armv8-timer";
1095 vph_pwr: vph-pwr-regulator {
1096 compatible = "regulator-fixed";
1097 regulator-name = "vph_pwr";
1099 regulator-min-microvolt = <3600000>;
1100 regulator-max-microvolt = <3600000>;
1102 regulator-always-on;