Lines Matching refs:sysctrl
10 #include <dt-bindings/clock/r9a06g032-sysctrl.h>
25 clocks = <&sysctrl R9A06G032_CLK_A7MP>;
32 clocks = <&sysctrl R9A06G032_CLK_A7MP>;
76 clocks = <&sysctrl R9A06G032_HCLK_RTC>;
78 power-domains = <&sysctrl>;
86 clocks = <&sysctrl R9A06G032_CLK_WATCHDOG>;
94 clocks = <&sysctrl R9A06G032_CLK_WATCHDOG>;
98 sysctrl: system-controller@4000c000 { label
99 compatible = "renesas,r9a06g032-sysctrl";
123 clocks = <&sysctrl R9A06G032_HCLK_USBH>,
124 <&sysctrl R9A06G032_HCLK_USBPM>,
125 <&sysctrl R9A06G032_CLK_PCI_USB>;
127 power-domains = <&sysctrl>;
167 clocks = <&sysctrl R9A06G032_CLK_UART0>, <&sysctrl R9A06G032_HCLK_UART0>;
178 clocks = <&sysctrl R9A06G032_CLK_UART1>, <&sysctrl R9A06G032_HCLK_UART1>;
189 clocks = <&sysctrl R9A06G032_CLK_UART2>, <&sysctrl R9A06G032_HCLK_UART2>;
200 clocks = <&sysctrl R9A06G032_CLK_UART3>, <&sysctrl R9A06G032_HCLK_UART3>;
213 clocks = <&sysctrl R9A06G032_CLK_UART4>, <&sysctrl R9A06G032_HCLK_UART4>;
226 clocks = <&sysctrl R9A06G032_CLK_UART5>, <&sysctrl R9A06G032_HCLK_UART5>;
239 clocks = <&sysctrl R9A06G032_CLK_UART6>, <&sysctrl R9A06G032_HCLK_UART6>;
252 clocks = <&sysctrl R9A06G032_CLK_UART7>, <&sysctrl R9A06G032_HCLK_UART7>;
262 clocks = <&sysctrl R9A06G032_HCLK_PINCONFIG>;
271 clocks = <&sysctrl R9A06G032_HCLK_NAND>, <&sysctrl R9A06G032_CLK_NAND>;
273 power-domains = <&sysctrl>;
284 clocks = <&sysctrl R9A06G032_HCLK_DMA0>;
298 clocks = <&sysctrl R9A06G032_HCLK_DMA1>;
315 clocks = <&sysctrl R9A06G032_HCLK_GMAC1>;
317 power-domains = <&sysctrl>;
330 clocks = <&sysctrl R9A06G032_CLK_MII_REF>,
331 <&sysctrl R9A06G032_CLK_RGMII_REF>,
332 <&sysctrl R9A06G032_CLK_RMII_REF>,
333 <&sysctrl R9A06G032_HCLK_SWITCH_RG>;
335 power-domains = <&sysctrl>;
367 clocks = <&sysctrl R9A06G032_HCLK_SWITCH>,
368 <&sysctrl R9A06G032_CLK_SWITCH>;
370 power-domains = <&sysctrl>;
432 clocks = <&sysctrl R9A06G032_HCLK_CAN0>;
433 power-domains = <&sysctrl>;
442 clocks = <&sysctrl R9A06G032_HCLK_CAN1>;
443 power-domains = <&sysctrl>;