Lines Matching +full:0 +full:x52104000

19 		#size-cells = <0>;
21 		cpu@0 {
24 			reg = <0>;
34 			cpu-release-addr = <0 0x4000c204>;
39 		#clock-cells = <0>;
41 		clock-frequency = <0>;
45 		#clock-cells = <0>;
51 		#clock-cells = <0>;
53 		clock-frequency = <0>;
57 		#clock-cells = <0>;
59 		clock-frequency = <0>;
71 			reg = <0x40006000 0x1000>;
84 			reg = <0x40008000 0x1000>;
92 			reg = <0x40009000 0x1000>;
100 			reg = <0x4000c000 0x1000>;
103 			#power-domain-cells = <0>;
113 				reg = <0xa0 4>;
128 			reg = <0x40030000 0xc00>,
129 			      <0x40020000 0x1100>;
133 			bus-range = <0 0>;
137 			ranges = <0x02000000 0 0x40020000 0x40020000 0 0x00010000>;
142 			dma-ranges = <0x42000000 0 0x80000000 0x80000000 0 0x40000000>;
143 			interrupt-map-mask = <0xf800 0 0 0x7>;
144 			interrupt-map = <0x0000 0 0 1 &gic GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH
145 					 0x0800 0 0 1 &gic GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH
146 					 0x1000 0 0 2 &gic GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>;
148 			usb@1,0 {
149 				reg = <0x800 0 0 0 0>;
154 			usb@2,0 {
155 				reg = <0x1000 0 0 0 0>;
163 			reg = <0x40060000 0x400>;
174 			reg = <0x40061000 0x400>;
185 			reg = <0x40062000 0x400>;
196 			reg = <0x50000000 0x400>;
202 			dmas =  <&dmamux 0 0 0 0 0 1>, <&dmamux 1 0 0 0 1 1>;
209 			reg = <0x50001000 0x400>;
215 			dmas =  <&dmamux 2 0 0 0 2 1>, <&dmamux 3 0 0 0 3 1>;
222 			reg = <0x50002000 0x400>;
228 			dmas =  <&dmamux 4 0 0 0 4 1>, <&dmamux 5 0 0 0 5 1>;
235 			reg = <0x50003000 0x400>;
241 			dmas =  <&dmamux 6 0 0 0 6 1>, <&dmamux 7 0 0 0 7 1>;
248 			reg = <0x50004000 0x400>;
254 			dmas =  <&dmamux 4 0 0 0 20 1>, <&dmamux 5 0 0 0 21 1>;
261 			reg = <0x40067000 0x1000>, <0x51000000 0x480>;
269 			reg = <0x40102000 0x2000>;
275 			#size-cells = <0>;
281 			reg = <0x40104000 0x1000>;
289 			block_size = <0xfff>;
295 			reg = <0x40105000 0x1000>;
303 			block_size = <0xfff>;
309 			reg = <0x44002000 0x2000>;
328 			#size-cells = <0>;
329 			reg = <0x44030000 0x10000>;
366 			reg = <0x44050000 0x10000>;
375 				#size-cells = <0>;
377 				switch_port0: port@0 {
378 					reg = <0>;
419 			reg = <0x44101000 0x1000>, /* Distributer */
420 			      <0x44102000 0x2000>, /* CPU interface */
421 			      <0x44104000 0x2000>, /* Virt interface control */
422 			      <0x44106000 0x2000>; /* Virt CPU interface */
429 			reg = <0x52104000 0x800>;
439 			reg = <0x52105000 0x800>;
461 		#phy-cells = <0>;