Lines Matching +full:ipa +full:- +full:ap +full:- +full:to +full:- +full:modem
1 // SPDX-License-Identifier: BSD-3-Clause
9 #include <dt-bindings/clock/qcom,gcc-sdx55.h>
10 #include <dt-bindings/clock/qcom,rpmh.h>
11 #include <dt-bindings/gpio/gpio.h>
12 #include <dt-bindings/interconnect/qcom,sdx55.h>
13 #include <dt-bindings/interrupt-controller/arm-gic.h>
14 #include <dt-bindings/power/qcom-rpmpd.h>
15 #include <dt-bindings/soc/qcom,rpmh-rsc.h>
18 #address-cells = <1>;
19 #size-cells = <1>;
20 qcom,msm-id = <357 0x10000>, <368 0x10000>, <418 0x10000>;
21 interrupt-parent = <&intc>;
29 xo_board: xo-board {
30 compatible = "fixed-clock";
31 #clock-cells = <0>;
32 clock-frequency = <38400000>;
33 clock-output-names = "xo_board";
36 sleep_clk: sleep-clk {
37 compatible = "fixed-clock";
38 #clock-cells = <0>;
39 clock-frequency = <32000>;
42 nand_clk_dummy: nand-clk-dummy {
43 compatible = "fixed-clock";
44 #clock-cells = <0>;
45 clock-frequency = <32000>;
50 #address-cells = <1>;
51 #size-cells = <0>;
55 compatible = "arm,cortex-a7";
57 enable-method = "psci";
59 power-domains = <&rpmhpd SDX55_CX>;
60 power-domain-names = "rpmhpd";
61 operating-points-v2 = <&cpu_opp_table>;
65 cpu_opp_table: cpu-opp-table {
66 compatible = "operating-points-v2";
67 opp-shared;
69 opp-345600000 {
70 opp-hz = /bits/ 64 <345600000>;
71 required-opps = <&rpmhpd_opp_low_svs>;
74 opp-576000000 {
75 opp-hz = /bits/ 64 <576000000>;
76 required-opps = <&rpmhpd_opp_svs>;
79 opp-1094400000 {
80 opp-hz = /bits/ 64 <1094400000>;
81 required-opps = <&rpmhpd_opp_nom>;
84 opp-1555200000 {
85 opp-hz = /bits/ 64 <1555200000>;
86 required-opps = <&rpmhpd_opp_turbo>;
92 compatible = "qcom,scm-sdx55", "qcom,scm";
97 compatible = "arm,psci-1.0";
101 reserved-memory {
102 #address-cells = <1>;
103 #size-cells = <1>;
107 no-map;
112 no-map;
117 no-map;
122 no-map;
127 no-map;
132 compatible = "qcom,cmd-db";
134 no-map;
138 no-map;
143 no-map;
148 no-map;
155 memory-region = <&smem_mem>;
159 smp2p-mpss {
164 qcom,local-pid = <0>;
165 qcom,remote-pid = <1>;
167 modem_smp2p_out: master-kernel {
168 qcom,entry-name = "master-kernel";
169 #qcom,smem-state-cells = <1>;
172 modem_smp2p_in: slave-kernel {
173 qcom,entry-name = "slave-kernel";
174 interrupt-controller;
175 #interrupt-cells = <2>;
178 ipa_smp2p_out: ipa-ap-to-modem {
179 qcom,entry-name = "ipa";
180 #qcom,smem-state-cells = <1>;
183 ipa_smp2p_in: ipa-modem-to-ap {
184 qcom,entry-name = "ipa";
185 interrupt-controller;
186 #interrupt-cells = <2>;
191 #address-cells = <1>;
192 #size-cells = <1>;
194 compatible = "simple-bus";
196 gcc: clock-controller@100000 {
197 compatible = "qcom,gcc-sdx55";
199 #clock-cells = <1>;
200 #reset-cells = <1>;
201 #power-domain-cells = <1>;
202 clock-names = "bi_tcxo", "sleep_clk";
207 compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
212 clock-names = "core", "iface";
217 compatible = "qcom,usb-snps-hs-7nm-phy";
220 #phy-cells = <0>;
223 clock-names = "ref";
229 compatible = "qcom,sdx55-qmp-usb3-uni-phy";
232 #address-cells = <1>;
233 #size-cells = <1>;
239 clock-names = "aux", "cfg_ahb", "ref";
243 reset-names = "phy", "common";
249 #phy-cells = <0>;
250 #clock-cells = <0>;
252 clock-names = "pipe0";
253 clock-output-names = "usb3_uni_phy_pipe_clk_src";
258 compatible = "qcom,sdx55-mc-virt";
260 #interconnect-cells = <1>;
261 qcom,bcm-voters = <&apps_bcm_voter>;
265 compatible = "qcom,sdx55-mem-noc";
267 #interconnect-cells = <1>;
268 qcom,bcm-voters = <&apps_bcm_voter>;
272 compatible = "qcom,sdx55-system-noc";
274 #interconnect-cells = <1>;
275 qcom,bcm-voters = <&apps_bcm_voter>;
278 qpic_bam: dma-controller@1b04000 {
279 compatible = "qcom,bam-v1.7.0";
283 clock-names = "bam_clk";
284 #dma-cells = <1>;
286 qcom,controlled-remotely;
290 qpic_nand: nand-controller@1b30000 {
291 compatible = "qcom,sdx55-nand";
293 #address-cells = <1>;
294 #size-cells = <0>;
297 clock-names = "core", "aon";
302 dma-names = "tx", "rx", "cmd";
307 compatible = "qcom,sdx55-qmp-pcie-phy";
309 #address-cells = <1>;
310 #size-cells = <1>;
316 clock-names = "aux", "cfg_ahb", "ref", "refgen";
319 reset-names = "phy";
321 assigned-clocks = <&gcc GCC_PCIE_RCHNG_PHY_CLK>;
322 assigned-clock-rates = <100000000>;
334 clock-names = "pipe0";
336 #phy-cells = <0>;
337 clock-output-names = "pcie_pipe_clk";
341 ipa: ipa@1e40000 { label
342 compatible = "qcom,sdx55-ipa";
349 reg-names = "ipa-reg",
350 "ipa-shared",
353 interrupts-extended = <&intc GIC_SPI 241 IRQ_TYPE_EDGE_RISING>,
357 interrupt-names = "ipa",
359 "ipa-clock-query",
360 "ipa-setup-ready";
363 clock-names = "core";
368 interconnect-names = "memory",
372 qcom,smem-states = <&ipa_smp2p_out 0>,
374 qcom,smem-state-names = "ipa-clock-enabled-valid",
375 "ipa-clock-enabled";
381 compatible = "qcom,tcsr-mutex";
383 #hwlock-cells = <1>;
392 compatible = "qcom,sdx55-sdhci", "qcom,sdhci-msm-v5";
396 interrupt-names = "hc_irq", "pwr_irq";
399 clock-names = "iface", "core";
403 pcie_ep: pcie-ep@40000000 {
404 compatible = "qcom,sdx55-pcie-ep";
411 reg-names = "parf", "dbi", "elbi", "atu", "addr_space",
414 qcom,perst-regs = <&tcsr 0xb258 0xb270>;
423 clock-names = "aux", "cfg", "bus_master", "bus_slave",
428 interrupt-names = "global", "doorbell";
429 reset-gpios = <&tlmm 57 GPIO_ACTIVE_LOW>;
430 wake-gpios = <&tlmm 53 GPIO_ACTIVE_LOW>;
432 reset-names = "core";
433 power-domains = <&gcc PCIE_GDSC>;
435 phy-names = "pciephy";
436 max-link-speed = <3>;
437 num-lanes = <2>;
443 compatible = "qcom,sdx55-mpss-pas";
446 interrupts-extended = <&intc GIC_SPI 250 IRQ_TYPE_EDGE_RISING>,
452 interrupt-names = "wdog", "fatal", "ready", "handover",
453 "stop-ack", "shutdown-ack";
456 clock-names = "xo";
458 power-domains = <&rpmhpd SDX55_CX>,
460 power-domain-names = "cx", "mss";
462 qcom,smem-states = <&modem_smp2p_out 0>;
463 qcom,smem-state-names = "stop";
467 glink-edge {
470 qcom,remote-pid = <1>;
476 compatible = "qcom,sdx55-dwc3", "qcom,dwc3";
479 #address-cells = <1>;
480 #size-cells = <1>;
488 clock-names = "cfg_noc",
494 assigned-clocks = <&gcc GCC_USB30_MOCK_UTMI_CLK>,
496 assigned-clock-rates = <19200000>, <200000000>;
502 interrupt-names = "hs_phy_irq", "ss_phy_irq",
505 power-domains = <&gcc USB30_GDSC>;
517 phy-names = "usb2-phy", "usb3-phy";
521 pdc: interrupt-controller@b210000 {
522 compatible = "qcom,sdx55-pdc", "qcom,pdc";
524 qcom,pdc-ranges = <0 179 52>;
525 #interrupt-cells = <3>;
526 interrupt-parent = <&intc>;
527 interrupt-controller;
536 compatible = "qcom,spmi-pmic-arb";
542 reg-names = "core", "chnls", "obsrvr", "intr", "cnfg";
543 interrupt-names = "periph_irq";
547 #address-cells = <2>;
548 #size-cells = <0>;
549 interrupt-controller;
550 #interrupt-cells = <4>;
551 cell-index = <0>;
555 compatible = "qcom,sdx55-pinctrl";
558 gpio-controller;
559 #gpio-cells = <2>;
560 interrupt-controller;
561 #interrupt-cells = <2>;
565 compatible = "qcom,sdx55-imem", "syscon", "simple-mfd";
568 #address-cells = <1>;
569 #size-cells = <1>;
573 pil-reloc@94c {
574 compatible = "qcom,pil-reloc-info";
580 compatible = "qcom,sdx55-smmu-500", "arm,mmu-500";
582 #iommu-cells = <2>;
583 #global-interrupts = <1>;
603 intc: interrupt-controller@17800000 {
604 compatible = "qcom,msm-qgic2";
605 interrupt-controller;
606 interrupt-parent = <&intc>;
607 #interrupt-cells = <3>;
613 compatible = "qcom,sdx55-a7pll";
616 clock-names = "bi_tcxo";
617 #clock-cells = <0>;
621 compatible = "qcom,sdx55-apcs-gcc", "syscon";
623 #mbox-cells = <1>;
625 clock-names = "ref", "pll", "aux";
626 #clock-cells = <0>;
630 compatible = "qcom,apss-wdt-sdx55", "qcom,kpss-wdt";
636 #address-cells = <1>;
637 #size-cells = <1>;
639 compatible = "arm,armv7-timer-mem";
641 clock-frequency = <19200000>;
644 frame-number = <0>;
652 frame-number = <1>;
659 frame-number = <2>;
666 frame-number = <3>;
673 frame-number = <4>;
680 frame-number = <5>;
687 frame-number = <6>;
694 frame-number = <7>;
702 compatible = "qcom,rpmh-rsc";
704 reg-names = "drv-0", "drv-1";
707 qcom,tcs-offset = <0xd00>;
708 qcom,drv-id = <1>;
709 qcom,tcs-config = <ACTIVE_TCS 2>, <SLEEP_TCS 2>,
712 rpmhcc: clock-controller {
713 compatible = "qcom,sdx55-rpmh-clk";
714 #clock-cells = <1>;
715 clock-names = "xo";
719 rpmhpd: power-controller {
720 compatible = "qcom,sdx55-rpmhpd";
721 #power-domain-cells = <1>;
722 operating-points-v2 = <&rpmhpd_opp_table>;
724 rpmhpd_opp_table: opp-table {
725 compatible = "operating-points-v2";
728 opp-level = <RPMH_REGULATOR_LEVEL_RETENTION>;
732 opp-level = <RPMH_REGULATOR_LEVEL_MIN_SVS>;
736 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>;
740 opp-level = <RPMH_REGULATOR_LEVEL_SVS>;
744 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>;
748 opp-level = <RPMH_REGULATOR_LEVEL_NOM>;
752 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>;
756 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L2>;
760 opp-level = <RPMH_REGULATOR_LEVEL_TURBO>;
764 opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L1>;
769 apps_bcm_voter: bcm-voter {
770 compatible = "qcom,bcm-voter";
776 compatible = "arm,armv7-timer";
781 clock-frequency = <19200000>;