Lines Matching full:gcc
9 #include <dt-bindings/clock/qcom,gcc-sdx55.h>
196 gcc: clock-controller@100000 { label
197 compatible = "qcom,gcc-sdx55";
210 clocks = <&gcc 30>,
211 <&gcc 9>;
225 resets = <&gcc GCC_QUSB2PHY_BCR>;
236 clocks = <&gcc GCC_USB3_PHY_AUX_CLK>,
237 <&gcc GCC_USB_PHY_CFG_AHB2PHY_CLK>,
238 <&gcc GCC_USB3_PRIM_CLKREF_CLK>;
241 resets = <&gcc GCC_USB3PHY_PHY_BCR>,
242 <&gcc GCC_USB3_PHY_BCR>;
251 clocks = <&gcc GCC_USB3_PHY_PIPE_CLK>;
312 clocks = <&gcc GCC_PCIE_AUX_PHY_CLK_SRC>,
313 <&gcc GCC_PCIE_CFG_AHB_CLK>,
314 <&gcc GCC_PCIE_0_CLKREF_CLK>,
315 <&gcc GCC_PCIE_RCHNG_PHY_CLK>;
318 resets = <&gcc GCC_PCIE_PHY_BCR>;
321 assigned-clocks = <&gcc GCC_PCIE_RCHNG_PHY_CLK>;
333 clocks = <&gcc GCC_PCIE_PIPE_CLK>;
397 clocks = <&gcc GCC_SDCC1_AHB_CLK>,
398 <&gcc GCC_SDCC1_APPS_CLK>;
416 clocks = <&gcc GCC_PCIE_AUX_CLK>,
417 <&gcc GCC_PCIE_CFG_AHB_CLK>,
418 <&gcc GCC_PCIE_MSTR_AXI_CLK>,
419 <&gcc GCC_PCIE_SLV_AXI_CLK>,
420 <&gcc GCC_PCIE_SLV_Q2A_AXI_CLK>,
421 <&gcc GCC_PCIE_SLEEP_CLK>,
422 <&gcc GCC_PCIE_0_CLKREF_CLK>;
431 resets = <&gcc GCC_PCIE_BCR>;
433 power-domains = <&gcc PCIE_GDSC>;
483 clocks = <&gcc GCC_USB30_SLV_AHB_CLK>,
484 <&gcc GCC_USB30_MASTER_CLK>,
485 <&gcc GCC_USB30_MSTR_AXI_CLK>,
486 <&gcc GCC_USB30_SLEEP_CLK>,
487 <&gcc GCC_USB30_MOCK_UTMI_CLK>;
494 assigned-clocks = <&gcc GCC_USB30_MOCK_UTMI_CLK>,
495 <&gcc GCC_USB30_MASTER_CLK>;
505 power-domains = <&gcc USB30_GDSC>;
507 resets = <&gcc GCC_USB30_BCR>;
621 compatible = "qcom,sdx55-apcs-gcc", "syscon";
624 clocks = <&rpmhcc RPMH_CXO_CLK>, <&a7pll>, <&gcc GPLL0>;