Lines Matching +full:0 +full:x15000000
20 qcom,msm-id = <357 0x10000>, <368 0x10000>, <418 0x10000>;
25 reg = <0 0>;
31 #clock-cells = <0>;
38 #clock-cells = <0>;
44 #clock-cells = <0>;
51 #size-cells = <0>;
53 cpu0: cpu@0 {
56 reg = <0x0>;
108 reg = <0x8fc00000 0x80000>;
113 reg = <0x8fc80000 0x40000>;
118 reg = <0x8fcfd000 0x1000>;
123 reg = <0x8fd00000 0x100000>;
128 reg = <0x8fe00000 0x20000>;
133 reg = <0x8fe20000 0x20000>;
139 reg = <0x8fe40000 0xc0000>;
144 reg = <0x8ff00000 0x100000>;
149 reg = <0x90000000 0x500000>;
164 qcom,local-pid = <0>;
198 reg = <0x100000 0x1f0000>;
208 reg = <0x00831000 0x200>;
218 reg = <0x00ff4000 0x114>;
220 #phy-cells = <0>;
230 reg = <0x00ff6000 0x1c0>;
246 reg = <0x00ff6200 0x170>,
247 <0x00ff6400 0x200>,
248 <0x00ff6800 0x800>;
249 #phy-cells = <0>;
250 #clock-cells = <0>;
259 reg = <0x01100000 0x400000>;
266 reg = <0x09680000 0x40000>;
273 reg = <0x0162c000 0x31200>;
280 reg = <0x01b04000 0x1c000>;
285 qcom,ee = <0>;
292 reg = <0x01b30000 0x10000>;
294 #size-cells = <0>;
299 dmas = <&qpic_bam 0>,
308 reg = <0x01c07000 0x1c4>;
327 reg = <0x01c06000 0x104>, /* tx0 */
328 <0x01c06200 0x328>, /* rx0 */
329 <0x01c07200 0x1e8>, /* pcs */
330 <0x01c06800 0x104>, /* tx1 */
331 <0x01c06a00 0x328>, /* rx1 */
332 <0x01c07600 0x800>; /* pcs_misc */
336 #phy-cells = <0>;
344 iommus = <&apps_smmu 0x5e0 0x0>,
345 <&apps_smmu 0x5e2 0x0>;
346 reg = <0x1e40000 0x7000>,
347 <0x1e50000 0x4b20>,
348 <0x1e04000 0x2c000>;
355 <&ipa_smp2p_in 0 IRQ_TYPE_EDGE_RISING>,
372 qcom,smem-states = <&ipa_smp2p_out 0>,
382 reg = <0x01f40000 0x40000>;
388 reg = <0x01fc0000 0x1000>;
393 reg = <0x08804000 0x1000>;
405 reg = <0x01c00000 0x3000>,
406 <0x40000000 0xf1d>,
407 <0x40000f20 0xc8>,
408 <0x40001000 0x1000>,
409 <0x40200000 0x100000>,
410 <0x01c03000 0x3000>;
414 qcom,perst-regs = <&tcsr 0xb258 0xb270>;
444 reg = <0x04080000 0x4040>;
447 <&modem_smp2p_in 0 IRQ_TYPE_EDGE_RISING>,
462 qcom,smem-states = <&modem_smp2p_out 0>;
477 reg = <0x0a6f8800 0x400>;
511 reg = <0x0a600000 0xcd00>;
513 iommus = <&apps_smmu 0x1a0 0x0>;
523 reg = <0x0b210000 0x30000>;
524 qcom,pdc-ranges = <0 179 52>;
532 reg = <0x0c264000 0x1000>;
537 reg = <0x0c440000 0x0000d00>,
538 <0x0c600000 0x2000000>,
539 <0x0e600000 0x0100000>,
540 <0x0e700000 0x00a0000>,
541 <0x0c40a000 0x0000700>;
545 qcom,ee = <0>;
546 qcom,channel = <0>;
548 #size-cells = <0>;
551 cell-index = <0>;
556 reg = <0xf100000 0x300000>;
566 reg = <0x1468f000 0x1000>;
571 ranges = <0x0 0x1468f000 0x1000>;
575 reg = <0x94c 0x200>;
581 reg = <0x15000000 0x20000>;
608 reg = <0x17800000 0x1000>,
609 <0x17802000 0x1000>;
614 reg = <0x17808000 0x1000>;
617 #clock-cells = <0>;
622 reg = <0x17810000 0x2000>;
626 #clock-cells = <0>;
631 reg = <0x17817000 0x1000>;
640 reg = <0x17820000 0x1000>;
644 frame-number = <0>;
645 interrupts = <GIC_SPI 7 0x4>,
646 <GIC_SPI 6 0x4>;
647 reg = <0x17821000 0x1000>,
648 <0x17822000 0x1000>;
653 interrupts = <GIC_SPI 8 0x4>;
654 reg = <0x17823000 0x1000>;
660 interrupts = <GIC_SPI 9 0x4>;
661 reg = <0x17824000 0x1000>;
667 interrupts = <GIC_SPI 10 0x4>;
668 reg = <0x17825000 0x1000>;
674 interrupts = <GIC_SPI 11 0x4>;
675 reg = <0x17826000 0x1000>;
681 interrupts = <GIC_SPI 12 0x4>;
682 reg = <0x17827000 0x1000>;
688 interrupts = <GIC_SPI 13 0x4>;
689 reg = <0x17828000 0x1000>;
695 interrupts = <GIC_SPI 14 0x4>;
696 reg = <0x17829000 0x1000>;
703 reg = <0x17830000 0x10000>, <0x17840000 0x10000>;
704 reg-names = "drv-0", "drv-1";
707 qcom,tcs-offset = <0xd00>;