Lines Matching +full:msm +full:- +full:uartdm +full:- +full:v1
1 // SPDX-License-Identifier: GPL-2.0
2 /dts-v1/;
4 #include <dt-bindings/interrupt-controller/arm-gic.h>
5 #include <dt-bindings/mfd/qcom-rpm.h>
6 #include <dt-bindings/clock/qcom,rpmcc.h>
7 #include <dt-bindings/clock/qcom,gcc-ipq806x.h>
8 #include <dt-bindings/clock/qcom,lcc-ipq806x.h>
9 #include <dt-bindings/gpio/gpio.h>
10 #include <dt-bindings/reset/qcom,gcc-ipq806x.h>
11 #include <dt-bindings/soc/qcom,gsbi.h>
12 #include <dt-bindings/interrupt-controller/arm-gic.h>
15 #address-cells = <1>;
16 #size-cells = <1>;
19 interrupt-parent = <&intc>;
22 #address-cells = <1>;
23 #size-cells = <0>;
27 enable-method = "qcom,kpss-acc-v1";
30 next-level-cache = <&L2>;
37 enable-method = "qcom,kpss-acc-v1";
40 next-level-cache = <&L2>;
45 L2: l2-cache {
47 cache-level = <2>;
51 thermal-zones {
52 sensor0-thermal {
53 polling-delay-passive = <0>;
54 polling-delay = <0>;
55 thermal-sensors = <&tsens 0>;
58 cpu-critical {
64 cpu-hot {
72 sensor1-thermal {
73 polling-delay-passive = <0>;
74 polling-delay = <0>;
75 thermal-sensors = <&tsens 1>;
78 cpu-critical {
84 cpu-hot {
92 sensor2-thermal {
93 polling-delay-passive = <0>;
94 polling-delay = <0>;
95 thermal-sensors = <&tsens 2>;
98 cpu-critical {
104 cpu-hot {
112 sensor3-thermal {
113 polling-delay-passive = <0>;
114 polling-delay = <0>;
115 thermal-sensors = <&tsens 3>;
118 cpu-critical {
124 cpu-hot {
132 sensor4-thermal {
133 polling-delay-passive = <0>;
134 polling-delay = <0>;
135 thermal-sensors = <&tsens 4>;
138 cpu-critical {
144 cpu-hot {
152 sensor5-thermal {
153 polling-delay-passive = <0>;
154 polling-delay = <0>;
155 thermal-sensors = <&tsens 5>;
158 cpu-critical {
164 cpu-hot {
172 sensor6-thermal {
173 polling-delay-passive = <0>;
174 polling-delay = <0>;
175 thermal-sensors = <&tsens 6>;
178 cpu-critical {
184 cpu-hot {
192 sensor7-thermal {
193 polling-delay-passive = <0>;
194 polling-delay = <0>;
195 thermal-sensors = <&tsens 7>;
198 cpu-critical {
204 cpu-hot {
212 sensor8-thermal {
213 polling-delay-passive = <0>;
214 polling-delay = <0>;
215 thermal-sensors = <&tsens 8>;
218 cpu-critical {
224 cpu-hot {
232 sensor9-thermal {
233 polling-delay-passive = <0>;
234 polling-delay = <0>;
235 thermal-sensors = <&tsens 9>;
238 cpu-critical {
244 cpu-hot {
252 sensor10-thermal {
253 polling-delay-passive = <0>;
254 polling-delay = <0>;
255 thermal-sensors = <&tsens 10>;
258 cpu-critical {
264 cpu-hot {
278 cpu-pmu {
279 compatible = "qcom,krait-pmu";
284 reserved-memory {
285 #address-cells = <1>;
286 #size-cells = <1>;
291 no-map;
297 no-map;
305 compatible = "fixed-clock";
306 #clock-cells = <0>;
307 clock-frequency = <25000000>;
311 compatible = "fixed-clock";
312 #clock-cells = <0>;
313 clock-frequency = <25000000>;
317 compatible = "fixed-clock";
318 clock-frequency = <32768>;
319 #clock-cells = <0>;
325 compatible = "qcom,scm-ipq806x", "qcom,scm";
330 #address-cells = <1>;
331 #size-cells = <1>;
333 compatible = "simple-bus";
335 stmmac_axi_setup: stmmac-axi-config {
341 vsdcc_fixed: vsdcc-regulator {
342 compatible = "regulator-fixed";
343 regulator-name = "SDCC Power";
344 regulator-min-microvolt = <3300000>;
345 regulator-max-microvolt = <3300000>;
346 regulator-always-on;
350 compatible = "qcom,rpm-ipq8064";
357 interrupt-names = "ack", "err", "wakeup";
360 clock-names = "ram";
362 rpmcc: clock-controller {
363 compatible = "qcom,rpmcc-ipq806x", "qcom,rpmcc";
364 #clock-cells = <1>;
371 qcom,controller-type = "pmic-arbiter";
375 compatible = "qcom,ipq8064-qfprom", "qcom,qfprom";
377 #address-cells = <1>;
378 #size-cells = <1>;
391 compatible = "qcom,ipq8064-pinctrl";
394 gpio-controller;
395 gpio-ranges = <&qcom_pinmux 0 0 69>;
396 #gpio-cells = <2>;
397 interrupt-controller;
398 #interrupt-cells = <2>;
405 drive-strength = <12>;
406 bias-disable;
414 drive-strength = <12>;
415 bias-disable;
423 drive-strength = <12>;
424 bias-disable;
428 i2c4_pins: i2c4-default {
431 drive-strength = <12>;
432 bias-disable;
439 drive-strength = <10>;
440 bias-none;
449 drive-strength = <2>;
450 bias-pull-down;
451 output-low;
458 drive-strength = <2>;
459 bias-pull-up;
471 drive-strength = <10>;
472 bias-disable;
478 drive-strength = <10>;
479 bias-pull-up;
487 drive-strength = <10>;
488 bias-bus-hold;
492 mdio0_pins: mdio0-pins {
496 drive-strength = <8>;
497 bias-disable;
501 rgmii2_pins: rgmii2-pins {
508 drive-strength = <8>;
509 bias-disable;
514 gcc: clock-controller@900000 {
515 compatible = "qcom,gcc-ipq8064", "syscon";
517 clock-names = "pxo", "cxo";
519 #clock-cells = <1>;
520 #reset-cells = <1>;
521 #power-domain-cells = <1>;
523 tsens: thermal-sensor@900000 {
524 compatible = "qcom,ipq8064-tsens";
526 nvmem-cells = <&tsens_calib>, <&tsens_calib_backup>;
527 nvmem-cell-names = "calib", "calib_backup";
529 interrupt-names = "uplow";
532 #thermal-sensor-cells = <1>;
537 compatible = "qcom,sfpb-mutex";
540 #hwlock-cells = <1>;
543 intc: interrupt-controller@2000000 {
544 compatible = "qcom,msm-qgic2";
545 interrupt-controller;
546 #interrupt-cells = <3>;
552 compatible = "qcom,kpss-timer",
553 "qcom,kpss-wdt-ipq8064", "qcom,msm-timer";
565 clock-frequency = <25000000>,
568 clock-names = "sleep";
569 cpu-offset = <0x80000>;
572 l2cc: clock-controller@2011000 {
573 compatible = "qcom,kpss-gcc", "syscon";
576 clock-names = "pll8_vote", "pxo";
577 clock-output-names = "acpu_l2_aux";
580 acc0: clock-controller@2088000 {
581 compatible = "qcom,kpss-acc-v1";
591 acc1: clock-controller@2098000 {
592 compatible = "qcom,kpss-acc-v1";
608 compatible = "qcom,ipq8064-dwc3", "qcom,dwc3";
609 #address-cells = <1>;
610 #size-cells = <1>;
613 clock-names = "core";
618 reset-names = "master";
627 phy-names = "usb2-phy", "usb3-phy";
634 compatible = "qcom,ipq806x-usb-phy-hs";
637 clock-names = "ref";
638 #phy-cells = <0>;
644 compatible = "qcom,ipq806x-usb-phy-ss";
647 clock-names = "ref";
648 #phy-cells = <0>;
654 compatible = "qcom,ipq8064-dwc3", "qcom,dwc3";
655 #address-cells = <1>;
656 #size-cells = <1>;
659 clock-names = "core";
664 reset-names = "master";
673 phy-names = "usb2-phy", "usb3-phy";
680 compatible = "qcom,ipq806x-usb-phy-hs";
683 clock-names = "ref";
684 #phy-cells = <0>;
690 compatible = "qcom,ipq806x-usb-phy-ss";
693 clock-names = "ref";
694 #phy-cells = <0>;
699 sdcc3bam: dma-controller@12182000 {
700 compatible = "qcom,bam-v1.3.0";
704 clock-names = "bam_clk";
705 #dma-cells = <1>;
709 sdcc1bam: dma-controller@12402000 {
710 compatible = "qcom,bam-v1.3.0";
714 clock-names = "bam_clk";
715 #dma-cells = <1>;
720 compatible = "simple-bus";
721 #address-cells = <1>;
722 #size-cells = <1>;
727 arm,primecell-periphid = <0x00051180>;
731 interrupt-names = "cmd_irq";
733 clock-names = "mclk", "apb_pclk";
734 bus-width = <8>;
735 cap-sd-highspeed;
736 cap-mmc-highspeed;
737 max-frequency = <192000000>;
738 sd-uhs-sdr104;
739 sd-uhs-ddr50;
740 vqmmc-supply = <&vsdcc_fixed>;
742 dma-names = "tx", "rx";
748 arm,primecell-periphid = <0x00051180>;
751 interrupt-names = "cmd_irq";
753 clock-names = "mclk", "apb_pclk";
754 bus-width = <8>;
755 max-frequency = <96000000>;
756 non-removable;
757 cap-sd-highspeed;
758 cap-mmc-highspeed;
759 mmc-ddr-1_8v;
760 vmmc-supply = <&vsdcc_fixed>;
762 dma-names = "tx", "rx";
767 compatible = "qcom,gsbi-v1.0.0";
769 cell-index = <1>;
771 clock-names = "iface";
772 #address-cells = <1>;
773 #size-cells = <1>;
776 syscon-tcsr = <&tcsr>;
781 compatible = "qcom,msm-uartdm-v1.3", "qcom,msm-uartdm";
786 clock-names = "core", "iface";
792 compatible = "qcom,i2c-qup-v1.1.1";
796 clock-names = "core", "iface";
797 #address-cells = <1>;
798 #size-cells = <0>;
805 compatible = "qcom,gsbi-v1.0.0";
806 cell-index = <2>;
809 clock-names = "iface";
810 #address-cells = <1>;
811 #size-cells = <1>;
815 syscon-tcsr = <&tcsr>;
818 compatible = "qcom,msm-uartdm-v1.3", "qcom,msm-uartdm";
823 clock-names = "core", "iface";
828 compatible = "qcom,i2c-qup-v1.1.1";
833 clock-names = "core", "iface";
836 #address-cells = <1>;
837 #size-cells = <0>;
842 compatible = "qcom,gsbi-v1.0.0";
843 cell-index = <4>;
846 clock-names = "iface";
847 #address-cells = <1>;
848 #size-cells = <1>;
852 syscon-tcsr = <&tcsr>;
855 compatible = "qcom,msm-uartdm-v1.3", "qcom,msm-uartdm";
860 clock-names = "core", "iface";
865 compatible = "qcom,i2c-qup-v1.1.1";
870 clock-names = "core", "iface";
873 #address-cells = <1>;
874 #size-cells = <0>;
879 compatible = "qcom,gsbi-v1.0.0";
881 cell-index = <6>;
883 clock-names = "iface";
884 #address-cells = <1>;
885 #size-cells = <1>;
888 syscon-tcsr = <&tcsr>;
893 compatible = "qcom,i2c-qup-v1.1.1";
898 clock-names = "core", "iface";
900 #address-cells = <1>;
901 #size-cells = <0>;
907 compatible = "qcom,spi-qup-v1.1.1";
912 clock-names = "core", "iface";
914 #address-cells = <1>;
915 #size-cells = <0>;
923 compatible = "qcom,gsbi-v1.0.0";
924 cell-index = <7>;
927 clock-names = "iface";
928 #address-cells = <1>;
929 #size-cells = <1>;
931 syscon-tcsr = <&tcsr>;
934 compatible = "qcom,msm-uartdm-v1.3", "qcom,msm-uartdm";
939 clock-names = "core", "iface";
944 compatible = "qcom,i2c-qup-v1.1.1";
949 clock-names = "core", "iface";
951 #address-cells = <1>;
952 #size-cells = <0>;
958 adm_dma: dma-controller@18300000 {
962 #dma-cells = <1>;
965 clock-names = "core", "iface";
972 reset-names = "clk", "pbus", "c0", "c1", "c2";
979 compatible = "qcom,gsbi-v1.0.0";
980 cell-index = <5>;
983 clock-names = "iface";
984 #address-cells = <1>;
986 #size-cells = <1>;
990 syscon-tcsr = <&tcsr>;
993 compatible = "qcom,msm-uartdm-v1.3", "qcom,msm-uartdm";
998 clock-names = "core", "iface";
1003 compatible = "qcom,i2c-qup-v1.1.1";
1008 clock-names = "core", "iface";
1011 #address-cells = <1>;
1012 #size-cells = <0>;
1016 compatible = "qcom,spi-qup-v1.1.1";
1021 clock-names = "core", "iface";
1024 #address-cells = <1>;
1025 #size-cells = <0>;
1030 compatible = "qcom,tcsr-ipq8064", "syscon";
1038 clock-names = "core";
1041 nand: nand-controller@1ac00000 {
1042 compatible = "qcom,ipq806x-nand";
1045 pinctrl-0 = <&nand_pins>;
1046 pinctrl-names = "default";
1050 clock-names = "core", "aon";
1053 dma-names = "rxtx";
1054 qcom,cmd-crci = <15>;
1055 qcom,data-crci = <3>;
1057 #address-cells = <1>;
1058 #size-cells = <0>;
1063 sata_phy: sata-phy@1b400000 {
1064 compatible = "qcom,ipq806x-sata-phy";
1068 clock-names = "cfg";
1070 #phy-cells = <0>;
1075 compatible = "qcom,pcie-ipq8064";
1080 reg-names = "dbi", "elbi", "parf", "config";
1082 linux,pci-domain = <0>;
1083 bus-range = <0x00 0xff>;
1084 num-lanes = <1>;
1085 #address-cells = <3>;
1086 #size-cells = <2>;
1089 0x82000000 0 0x08000000 0x08000000 0 0x07e00000>; /* non-prefetchable memory */
1092 interrupt-names = "msi";
1093 #interrupt-cells = <1>;
1094 interrupt-map-mask = <0 0 0 0x7>;
1095 interrupt-map = <0 0 0 1 &intc 0 36 IRQ_TYPE_LEVEL_HIGH>, /* int_a */
1105 clock-names = "core", "iface", "phy", "aux", "ref";
1107 assigned-clocks = <&gcc PCIE_ALT_REF_CLK>;
1108 assigned-clock-rates = <100000000>;
1116 reset-names = "axi", "ahb", "por", "pci", "phy", "ext";
1118 pinctrl-0 = <&pcie0_pins>;
1119 pinctrl-names = "default";
1122 perst-gpios = <&qcom_pinmux 3 GPIO_ACTIVE_LOW>;
1126 compatible = "qcom,pcie-ipq8064";
1131 reg-names = "dbi", "elbi", "parf", "config";
1133 linux,pci-domain = <1>;
1134 bus-range = <0x00 0xff>;
1135 num-lanes = <1>;
1136 #address-cells = <3>;
1137 #size-cells = <2>;
1140 0x82000000 0 0x2e000000 0x2e000000 0 0x03e00000>; /* non-prefetchable memory */
1143 interrupt-names = "msi";
1144 #interrupt-cells = <1>;
1145 interrupt-map-mask = <0 0 0 0x7>;
1146 interrupt-map = <0 0 0 1 &intc 0 58 IRQ_TYPE_LEVEL_HIGH>, /* int_a */
1156 clock-names = "core", "iface", "phy", "aux", "ref";
1158 assigned-clocks = <&gcc PCIE_1_ALT_REF_CLK>;
1159 assigned-clock-rates = <100000000>;
1167 reset-names = "axi", "ahb", "por", "pci", "phy", "ext";
1169 pinctrl-0 = <&pcie1_pins>;
1170 pinctrl-names = "default";
1173 perst-gpios = <&qcom_pinmux 48 GPIO_ACTIVE_LOW>;
1177 compatible = "qcom,pcie-ipq8064";
1182 reg-names = "dbi", "elbi", "parf", "config";
1184 linux,pci-domain = <2>;
1185 bus-range = <0x00 0xff>;
1186 num-lanes = <1>;
1187 #address-cells = <3>;
1188 #size-cells = <2>;
1191 0x82000000 0 0x32000000 0x32000000 0 0x03e00000>; /* non-prefetchable memory */
1194 interrupt-names = "msi";
1195 #interrupt-cells = <1>;
1196 interrupt-map-mask = <0 0 0 0x7>;
1197 interrupt-map = <0 0 0 1 &intc 0 72 IRQ_TYPE_LEVEL_HIGH>, /* int_a */
1207 clock-names = "core", "iface", "phy", "aux", "ref";
1209 assigned-clocks = <&gcc PCIE_2_ALT_REF_CLK>;
1210 assigned-clock-rates = <100000000>;
1218 reset-names = "axi", "ahb", "por", "pci", "phy", "ext";
1220 pinctrl-0 = <&pcie2_pins>;
1221 pinctrl-names = "default";
1224 perst-gpios = <&qcom_pinmux 63 GPIO_ACTIVE_LOW>;
1232 lcc: clock-controller@28000000 {
1233 compatible = "qcom,lcc-ipq8064";
1235 #clock-cells = <1>;
1236 #reset-cells = <1>;
1240 compatible = "qcom,lpass-cpu";
1245 clock-names = "ahbix-clk",
1246 "mi2s-osr-clk",
1247 "mi2s-bit-clk";
1249 interrupt-names = "lpass-irq-lpaif";
1251 reg-names = "lpass-lpaif";
1255 compatible = "qcom,ipq806x-ahci", "generic-ahci";
1265 clock-names = "slave_face", "iface", "core",
1268 assigned-clocks = <&gcc SATA_RXOOB_CLK>, <&gcc SATA_PMALIVE_CLK>;
1269 assigned-clock-rates = <100000000>, <100000000>;
1272 phy-names = "sata-phy";
1278 compatible = "qcom,ipq806x-gmac", "snps,dwmac";
1281 interrupt-names = "macirq";
1283 snps,axi-config = <&stmmac_axi_setup>;
1287 qcom,nss-common = <&nss_common>;
1288 qcom,qsgmii-csr = <&qsgmii_csr>;
1291 clock-names = "stmmaceth";
1295 reset-names = "stmmaceth", "ahb";
1302 compatible = "qcom,ipq806x-gmac", "snps,dwmac";
1305 interrupt-names = "macirq";
1307 snps,axi-config = <&stmmac_axi_setup>;
1311 qcom,nss-common = <&nss_common>;
1312 qcom,qsgmii-csr = <&qsgmii_csr>;
1315 clock-names = "stmmaceth";
1319 reset-names = "stmmaceth", "ahb";
1326 compatible = "qcom,ipq806x-gmac", "snps,dwmac";
1329 interrupt-names = "macirq";
1331 snps,axi-config = <&stmmac_axi_setup>;
1335 qcom,nss-common = <&nss_common>;
1336 qcom,qsgmii-csr = <&qsgmii_csr>;
1339 clock-names = "stmmaceth";
1343 reset-names = "stmmaceth", "ahb";
1350 compatible = "qcom,ipq806x-gmac", "snps,dwmac";
1353 interrupt-names = "macirq";
1355 snps,axi-config = <&stmmac_axi_setup>;
1359 qcom,nss-common = <&nss_common>;
1360 qcom,qsgmii-csr = <&qsgmii_csr>;
1363 clock-names = "stmmaceth";
1367 reset-names = "stmmaceth", "ahb";