Lines Matching full:gcc
7 #include <dt-bindings/clock/qcom,gcc-ipq806x.h>
10 #include <dt-bindings/reset/qcom,gcc-ipq806x.h>
359 clocks = <&gcc RPM_MSG_RAM_H_CLK>;
514 gcc: clock-controller@900000 { label
515 compatible = "qcom,gcc-ipq8064", "syscon";
573 compatible = "qcom,kpss-gcc", "syscon";
575 clocks = <&gcc PLL8_VOTE>, <&pxo_board>;
612 clocks = <&gcc USB30_0_MASTER_CLK>;
617 resets = <&gcc USB30_0_MASTER_RESET>;
636 clocks = <&gcc USB30_0_UTMI_CLK>;
646 clocks = <&gcc USB30_0_MASTER_CLK>;
658 clocks = <&gcc USB30_1_MASTER_CLK>;
663 resets = <&gcc USB30_1_MASTER_RESET>;
682 clocks = <&gcc USB30_1_UTMI_CLK>;
692 clocks = <&gcc USB30_1_MASTER_CLK>;
703 clocks = <&gcc SDC3_H_CLK>;
713 clocks = <&gcc SDC1_H_CLK>;
732 clocks = <&gcc SDC3_CLK>, <&gcc SDC3_H_CLK>;
752 clocks = <&gcc SDC1_CLK>, <&gcc SDC1_H_CLK>;
770 clocks = <&gcc GSBI1_H_CLK>;
785 clocks = <&gcc GSBI1_UART_CLK>, <&gcc GSBI1_H_CLK>;
795 clocks = <&gcc GSBI1_QUP_CLK>, <&gcc GSBI1_H_CLK>;
808 clocks = <&gcc GSBI2_H_CLK>;
822 clocks = <&gcc GSBI2_UART_CLK>, <&gcc GSBI2_H_CLK>;
832 clocks = <&gcc GSBI2_QUP_CLK>, <&gcc GSBI2_H_CLK>;
845 clocks = <&gcc GSBI4_H_CLK>;
859 clocks = <&gcc GSBI4_UART_CLK>, <&gcc GSBI4_H_CLK>;
869 clocks = <&gcc GSBI4_QUP_CLK>, <&gcc GSBI4_H_CLK>;
882 clocks = <&gcc GSBI6_H_CLK>;
897 clocks = <&gcc GSBI6_QUP_CLK>, <&gcc GSBI6_H_CLK>;
911 clocks = <&gcc GSBI6_QUP_CLK>, <&gcc GSBI6_H_CLK>;
926 clocks = <&gcc GSBI7_H_CLK>;
938 clocks = <&gcc GSBI7_UART_CLK>, <&gcc GSBI7_H_CLK>;
948 clocks = <&gcc GSBI7_QUP_CLK>, <&gcc GSBI7_H_CLK>;
964 clocks = <&gcc ADM0_CLK>, <&gcc ADM0_PBUS_CLK>;
967 resets = <&gcc ADM0_RESET>,
968 <&gcc ADM0_PBUS_RESET>,
969 <&gcc ADM0_C0_RESET>,
970 <&gcc ADM0_C1_RESET>,
971 <&gcc ADM0_C2_RESET>;
982 clocks = <&gcc GSBI5_H_CLK>;
997 clocks = <&gcc GSBI5_UART_CLK>, <&gcc GSBI5_H_CLK>;
1007 clocks = <&gcc GSBI5_QUP_CLK>, <&gcc GSBI5_H_CLK>;
1020 clocks = <&gcc GSBI5_QUP_CLK>, <&gcc GSBI5_H_CLK>;
1037 clocks = <&gcc PRNG_CLK>;
1048 clocks = <&gcc EBI2_CLK>,
1049 <&gcc EBI2_AON_CLK>;
1067 clocks = <&gcc SATA_PHY_CFG_CLK>;
1100 clocks = <&gcc PCIE_A_CLK>,
1101 <&gcc PCIE_H_CLK>,
1102 <&gcc PCIE_PHY_CLK>,
1103 <&gcc PCIE_AUX_CLK>,
1104 <&gcc PCIE_ALT_REF_CLK>;
1107 assigned-clocks = <&gcc PCIE_ALT_REF_CLK>;
1110 resets = <&gcc PCIE_ACLK_RESET>,
1111 <&gcc PCIE_HCLK_RESET>,
1112 <&gcc PCIE_POR_RESET>,
1113 <&gcc PCIE_PCI_RESET>,
1114 <&gcc PCIE_PHY_RESET>,
1115 <&gcc PCIE_EXT_RESET>;
1151 clocks = <&gcc PCIE_1_A_CLK>,
1152 <&gcc PCIE_1_H_CLK>,
1153 <&gcc PCIE_1_PHY_CLK>,
1154 <&gcc PCIE_1_AUX_CLK>,
1155 <&gcc PCIE_1_ALT_REF_CLK>;
1158 assigned-clocks = <&gcc PCIE_1_ALT_REF_CLK>;
1161 resets = <&gcc PCIE_1_ACLK_RESET>,
1162 <&gcc PCIE_1_HCLK_RESET>,
1163 <&gcc PCIE_1_POR_RESET>,
1164 <&gcc PCIE_1_PCI_RESET>,
1165 <&gcc PCIE_1_PHY_RESET>,
1166 <&gcc PCIE_1_EXT_RESET>;
1202 clocks = <&gcc PCIE_2_A_CLK>,
1203 <&gcc PCIE_2_H_CLK>,
1204 <&gcc PCIE_2_PHY_CLK>,
1205 <&gcc PCIE_2_AUX_CLK>,
1206 <&gcc PCIE_2_ALT_REF_CLK>;
1209 assigned-clocks = <&gcc PCIE_2_ALT_REF_CLK>;
1212 resets = <&gcc PCIE_2_ACLK_RESET>,
1213 <&gcc PCIE_2_HCLK_RESET>,
1214 <&gcc PCIE_2_POR_RESET>,
1215 <&gcc PCIE_2_PCI_RESET>,
1216 <&gcc PCIE_2_PHY_RESET>,
1217 <&gcc PCIE_2_EXT_RESET>;
1260 clocks = <&gcc SFAB_SATA_S_H_CLK>,
1261 <&gcc SATA_H_CLK>,
1262 <&gcc SATA_A_CLK>,
1263 <&gcc SATA_RXOOB_CLK>,
1264 <&gcc SATA_PMALIVE_CLK>;
1268 assigned-clocks = <&gcc SATA_RXOOB_CLK>, <&gcc SATA_PMALIVE_CLK>;
1290 clocks = <&gcc GMAC_CORE1_CLK>;
1293 resets = <&gcc GMAC_CORE1_RESET>,
1294 <&gcc GMAC_AHB_RESET>;
1314 clocks = <&gcc GMAC_CORE2_CLK>;
1317 resets = <&gcc GMAC_CORE2_RESET>,
1318 <&gcc GMAC_AHB_RESET>;
1338 clocks = <&gcc GMAC_CORE3_CLK>;
1341 resets = <&gcc GMAC_CORE3_RESET>,
1342 <&gcc GMAC_AHB_RESET>;
1362 clocks = <&gcc GMAC_CORE4_CLK>;
1365 resets = <&gcc GMAC_CORE4_RESET>,
1366 <&gcc GMAC_AHB_RESET>;