Lines Matching +full:0 +full:x2e000000
23 #size-cells = <0>;
25 cpu0: cpu@0 {
29 reg = <0>;
53 polling-delay-passive = <0>;
54 polling-delay = <0>;
55 thermal-sensors = <&tsens 0>;
73 polling-delay-passive = <0>;
74 polling-delay = <0>;
93 polling-delay-passive = <0>;
94 polling-delay = <0>;
113 polling-delay-passive = <0>;
114 polling-delay = <0>;
133 polling-delay-passive = <0>;
134 polling-delay = <0>;
153 polling-delay-passive = <0>;
154 polling-delay = <0>;
173 polling-delay-passive = <0>;
174 polling-delay = <0>;
193 polling-delay-passive = <0>;
194 polling-delay = <0>;
213 polling-delay-passive = <0>;
214 polling-delay = <0>;
233 polling-delay-passive = <0>;
234 polling-delay = <0>;
253 polling-delay-passive = <0>;
254 polling-delay = <0>;
275 reg = <0x0 0x0>;
290 reg = <0x40000000 0x1000000>;
296 reg = <0x41000000 0x200000>;
306 #clock-cells = <0>;
312 #clock-cells = <0>;
319 #clock-cells = <0>;
338 snps,blen = <16 0 0 0 0 0 0>;
351 reg = <0x00108000 0x1000>;
352 qcom,ipc = <&l2cc 0x8 2>;
370 reg = <0x00500000 0x1000>;
376 reg = <0x00700000 0x1000>;
380 reg = <0xc0 0x4>;
383 reg = <0x400 0xb>;
386 reg = <0x410 0xb>;
392 reg = <0x00800000 0x4000>;
395 gpio-ranges = <&qcom_pinmux 0 0 69>;
518 reg = <0x00900000 0x4000>;
538 reg = <0x01200600 0x100>;
547 reg = <0x02000000 0x1000>,
548 <0x02002000 0x1000>;
564 reg = <0x0200a000 0x100>;
569 cpu-offset = <0x80000>;
574 reg = <0x02011000 0x1000>;
582 reg = <0x02088000 0x1000>, <0x02008000 0x1000>;
587 reg = <0x02089000 0x1000>, <0x02009000 0x1000>;
593 reg = <0x02098000 0x1000>, <0x02008000 0x1000>;
598 reg = <0x02099000 0x1000>, <0x02009000 0x1000>;
604 reg = <0x03000000 0x0000FFFF>;
611 reg = <0x100f8800 0x8000>;
624 reg = <0x10000000 0xcd00>;
635 reg = <0x100f8800 0x30>;
638 #phy-cells = <0>;
645 reg = <0x100f8830 0x30>;
648 #phy-cells = <0>;
657 reg = <0x110f8800 0x8000>;
670 reg = <0x11000000 0xcd00>;
681 reg = <0x110f8800 0x30>;
684 #phy-cells = <0>;
691 reg = <0x110f8830 0x30>;
694 #phy-cells = <0>;
701 reg = <0x12182000 0x8000>;
706 qcom,ee = <0>;
711 reg = <0x12402000 0x8000>;
716 qcom,ee = <0>;
727 arm,primecell-periphid = <0x00051180>;
729 reg = <0x12180000 0x2000>;
748 arm,primecell-periphid = <0x00051180>;
749 reg = <0x12400000 0x2000>;
768 reg = <0x12440000 0x100>;
782 reg = <0x12450000 0x100>,
783 <0x12400000 0x03>;
793 reg = <0x12460000 0x1000>;
798 #size-cells = <0>;
807 reg = <0x12480000 0x100>;
819 reg = <0x12490000 0x1000>,
820 <0x12480000 0x1000>;
829 reg = <0x124a0000 0x1000>;
837 #size-cells = <0>;
844 reg = <0x16300000 0x100>;
856 reg = <0x16340000 0x1000>,
857 <0x16300000 0x1000>;
866 reg = <0x16380000 0x1000>;
874 #size-cells = <0>;
880 reg = <0x16500000 0x100>;
894 reg = <0x16580000 0x1000>;
901 #size-cells = <0>;
908 reg = <0x16580000 0x1000>;
915 #size-cells = <0>;
925 reg = <0x16600000 0x100>;
935 reg = <0x16640000 0x1000>,
936 <0x16600000 0x1000>;
945 reg = <0x16680000 0x1000>;
952 #size-cells = <0>;
960 reg = <0x18300000 0x100000>;
973 qcom,ee = <0>;
981 reg = <0x1a200000 0x100>;
994 reg = <0x1a240000 0x1000>,
995 <0x1a200000 0x1000>;
1004 reg = <0x1a280000 0x1000>;
1012 #size-cells = <0>;
1017 reg = <0x1a280000 0x1000>;
1025 #size-cells = <0>;
1031 reg = <0x1a400000 0x100>;
1036 reg = <0x1a500000 0x200>;
1043 reg = <0x1ac00000 0x800>;
1045 pinctrl-0 = <&nand_pins>;
1058 #size-cells = <0>;
1065 reg = <0x1b400000 0x200>;
1070 #phy-cells = <0>;
1076 reg = <0x1b500000 0x1000
1077 0x1b502000 0x80
1078 0x1b600000 0x100
1079 0x0ff00000 0x100000>;
1082 linux,pci-domain = <0>;
1083 bus-range = <0x00 0xff>;
1088 ranges = <0x81000000 0 0x0fe00000 0x0fe00000 0 0x00010000 /* downstream I/O */
1089 0x82000000 0 0x08000000 0x08000000 0 0x07e00000>; /* non-prefetchable memory */
1094 interrupt-map-mask = <0 0 0 0x7>;
1095 interrupt-map = <0 0 0 1 &intc 0 36 IRQ_TYPE_LEVEL_HIGH>, /* int_a */
1096 <0 0 0 2 &intc 0 37 IRQ_TYPE_LEVEL_HIGH>, /* int_b */
1097 <0 0 0 3 &intc 0 38 IRQ_TYPE_LEVEL_HIGH>, /* int_c */
1098 <0 0 0 4 &intc 0 39 IRQ_TYPE_LEVEL_HIGH>; /* int_d */
1118 pinctrl-0 = <&pcie0_pins>;
1127 reg = <0x1b700000 0x1000
1128 0x1b702000 0x80
1129 0x1b800000 0x100
1130 0x31f00000 0x100000>;
1134 bus-range = <0x00 0xff>;
1139 ranges = <0x81000000 0 0x31e00000 0x31e00000 0 0x00010000 /* downstream I/O */
1140 0x82000000 0 0x2e000000 0x2e000000 0 0x03e00000>; /* non-prefetchable memory */
1145 interrupt-map-mask = <0 0 0 0x7>;
1146 interrupt-map = <0 0 0 1 &intc 0 58 IRQ_TYPE_LEVEL_HIGH>, /* int_a */
1147 <0 0 0 2 &intc 0 59 IRQ_TYPE_LEVEL_HIGH>, /* int_b */
1148 <0 0 0 3 &intc 0 60 IRQ_TYPE_LEVEL_HIGH>, /* int_c */
1149 <0 0 0 4 &intc 0 61 IRQ_TYPE_LEVEL_HIGH>; /* int_d */
1169 pinctrl-0 = <&pcie1_pins>;
1178 reg = <0x1b900000 0x1000
1179 0x1b902000 0x80
1180 0x1ba00000 0x100
1181 0x35f00000 0x100000>;
1185 bus-range = <0x00 0xff>;
1190 ranges = <0x81000000 0 0x35e00000 0x35e00000 0 0x00010000 /* downstream I/O */
1191 0x82000000 0 0x32000000 0x32000000 0 0x03e00000>; /* non-prefetchable memory */
1196 interrupt-map-mask = <0 0 0 0x7>;
1197 interrupt-map = <0 0 0 1 &intc 0 72 IRQ_TYPE_LEVEL_HIGH>, /* int_a */
1198 <0 0 0 2 &intc 0 73 IRQ_TYPE_LEVEL_HIGH>, /* int_b */
1199 <0 0 0 3 &intc 0 74 IRQ_TYPE_LEVEL_HIGH>, /* int_c */
1200 <0 0 0 4 &intc 0 75 IRQ_TYPE_LEVEL_HIGH>; /* int_d */
1220 pinctrl-0 = <&pcie2_pins>;
1229 reg = <0x1bb00000 0x000001FF>;
1234 reg = <0x28000000 0x1000>;
1250 reg = <0x28100000 0x10000>;
1256 reg = <0x29000000 0x180>;
1279 reg = <0x37000000 0x200000>;
1303 reg = <0x37200000 0x200000>;
1327 reg = <0x37400000 0x200000>;
1351 reg = <0x37600000 0x200000>;