31 #define SQ_SIZE(q)	((q)->q_depth << (q)->sqes)
32 #define CQ_SIZE(q)	((q)->q_depth * sizeof(struct nvme_completion))
102 	int q_depth;  member
174 	u16 q_depth;  member
471 		if (next_tail == nvmeq->q_depth)  in nvme_write_sq_db()
495 	if (++nvmeq->sq_tail == nvmeq->q_depth)  in nvme_submit_cmd()
958 	if (unlikely(cqe->command_id >= nvmeq->q_depth)) {  in nvme_handle_cqe()
987 		if (++start == nvmeq->q_depth)  in nvme_complete_cqes()
994 	if (nvmeq->cq_head == nvmeq->q_depth - 1) {  in nvme_update_cq_head()
1139 	c.create_cq.qsize = cpu_to_le16(nvmeq->q_depth - 1);  in adapter_alloc_cq()
1169 	c.create_sq.qsize = cpu_to_le16(nvmeq->q_depth - 1);  in adapter_alloc_sq()
1419 	int q_depth = dev->q_depth;  in nvme_cmb_qdepth()  local
1420 	unsigned q_size_aligned = roundup(q_depth * entry_size,  in nvme_cmb_qdepth()
1426 		q_depth = div_u64(mem_per_q, entry_size);  in nvme_cmb_qdepth()
1433 		if (q_depth < 64)  in nvme_cmb_qdepth()
1437 	return q_depth;  in nvme_cmb_qdepth()
1474 	nvmeq->q_depth = depth;  in nvme_alloc_queue()
1696 	aqa = nvmeq->q_depth - 1;  in nvme_pci_configure_admin_queue()
1725 		if (nvme_alloc_queue(dev, i, dev->q_depth)) {  in nvme_create_io_queues()
2131 			dev->q_depth = result;  in nvme_setup_io_queues()
2280 				min_t(int, dev->q_depth, BLK_MQ_MAX_DEPTH) - 1;  in nvme_dev_add()
2339 	dev->q_depth = min_t(int, NVME_CAP_MQES(dev->ctrl.cap) + 1,  in nvme_pci_enable()
2341 	dev->ctrl.sqsize = dev->q_depth - 1; /* 0's based queue depth */  in nvme_pci_enable()
2360 		dev->q_depth = 2;  in nvme_pci_enable()
2363 			dev->q_depth);  in nvme_pci_enable()
2367 		dev->q_depth = 64;  in nvme_pci_enable()
2369                         "set queue depth=%u\n", dev->q_depth);  in nvme_pci_enable()
2377 	    (dev->q_depth < (NVME_AQ_DEPTH + 2))) {  in nvme_pci_enable()
2378 		dev->q_depth = NVME_AQ_DEPTH + 2;  in nvme_pci_enable()
2380 			 dev->q_depth);  in nvme_pci_enable()