Lines Matching +full:reset +full:- +full:delay +full:- +full:us
1 // SPDX-License-Identifier: GPL-2.0
4 #include <dt-bindings/interrupt-controller/arm-gic.h>
5 #include <dt-bindings/clock/qcom,gcc-msm8998.h>
6 #include <dt-bindings/clock/qcom,rpmcc.h>
7 #include <dt-bindings/power/qcom-rpmpd.h>
8 #include <dt-bindings/gpio/gpio.h>
11 interrupt-parent = <&intc>;
13 qcom,msm-id = <292 0x0>;
15 #address-cells = <2>;
16 #size-cells = <2>;
26 reserved-memory {
27 #address-cells = <2>;
28 #size-cells = <2>;
33 no-map;
36 smem_mem: smem-mem@86000000 {
38 no-map;
43 no-map;
47 compatible = "qcom,rmtfs-mem";
50 alloc-ranges = <0x0 0xa0000000 0x0 0x2000000>;
51 no-map;
53 qcom,client-id = <1>;
59 xo: xo-board {
60 compatible = "fixed-clock";
61 #clock-cells = <0>;
62 clock-frequency = <19200000>;
63 clock-output-names = "xo_board";
67 compatible = "fixed-clock";
68 #clock-cells = <0>;
69 clock-frequency = <32764>;
74 #address-cells = <2>;
75 #size-cells = <0>;
81 enable-method = "psci";
82 cpu-idle-states = <&LITTLE_CPU_SLEEP_0 &LITTLE_CPU_SLEEP_1>;
83 next-level-cache = <&L2_0>;
84 L2_0: l2-cache {
85 compatible = "arm,arch-cache";
86 cache-level = <2>;
88 L1_I_0: l1-icache {
89 compatible = "arm,arch-cache";
91 L1_D_0: l1-dcache {
92 compatible = "arm,arch-cache";
100 enable-method = "psci";
101 cpu-idle-states = <&LITTLE_CPU_SLEEP_0 &LITTLE_CPU_SLEEP_1>;
102 next-level-cache = <&L2_0>;
103 L1_I_1: l1-icache {
104 compatible = "arm,arch-cache";
106 L1_D_1: l1-dcache {
107 compatible = "arm,arch-cache";
115 enable-method = "psci";
116 cpu-idle-states = <&LITTLE_CPU_SLEEP_0 &LITTLE_CPU_SLEEP_1>;
117 next-level-cache = <&L2_0>;
118 L1_I_2: l1-icache {
119 compatible = "arm,arch-cache";
121 L1_D_2: l1-dcache {
122 compatible = "arm,arch-cache";
130 enable-method = "psci";
131 cpu-idle-states = <&LITTLE_CPU_SLEEP_0 &LITTLE_CPU_SLEEP_1>;
132 next-level-cache = <&L2_0>;
133 L1_I_3: l1-icache {
134 compatible = "arm,arch-cache";
136 L1_D_3: l1-dcache {
137 compatible = "arm,arch-cache";
145 enable-method = "psci";
146 cpu-idle-states = <&BIG_CPU_SLEEP_0 &BIG_CPU_SLEEP_1>;
147 next-level-cache = <&L2_1>;
148 L2_1: l2-cache {
149 compatible = "arm,arch-cache";
150 cache-level = <2>;
152 L1_I_100: l1-icache {
153 compatible = "arm,arch-cache";
155 L1_D_100: l1-dcache {
156 compatible = "arm,arch-cache";
164 enable-method = "psci";
165 cpu-idle-states = <&BIG_CPU_SLEEP_0 &BIG_CPU_SLEEP_1>;
166 next-level-cache = <&L2_1>;
167 L1_I_101: l1-icache {
168 compatible = "arm,arch-cache";
170 L1_D_101: l1-dcache {
171 compatible = "arm,arch-cache";
179 enable-method = "psci";
180 cpu-idle-states = <&BIG_CPU_SLEEP_0 &BIG_CPU_SLEEP_1>;
181 next-level-cache = <&L2_1>;
182 L1_I_102: l1-icache {
183 compatible = "arm,arch-cache";
185 L1_D_102: l1-dcache {
186 compatible = "arm,arch-cache";
194 enable-method = "psci";
195 cpu-idle-states = <&BIG_CPU_SLEEP_0 &BIG_CPU_SLEEP_1>;
196 next-level-cache = <&L2_1>;
197 L1_I_103: l1-icache {
198 compatible = "arm,arch-cache";
200 L1_D_103: l1-dcache {
201 compatible = "arm,arch-cache";
205 cpu-map {
243 idle-states {
244 entry-method = "psci";
246 LITTLE_CPU_SLEEP_0: cpu-sleep-0-0 {
247 compatible = "arm,idle-state";
248 idle-state-name = "little-retention";
249 arm,psci-suspend-param = <0x00000002>;
250 entry-latency-us = <81>;
251 exit-latency-us = <86>;
252 min-residency-us = <200>;
255 LITTLE_CPU_SLEEP_1: cpu-sleep-0-1 {
256 compatible = "arm,idle-state";
257 idle-state-name = "little-power-collapse";
258 arm,psci-suspend-param = <0x40000003>;
259 entry-latency-us = <273>;
260 exit-latency-us = <612>;
261 min-residency-us = <1000>;
262 local-timer-stop;
265 BIG_CPU_SLEEP_0: cpu-sleep-1-0 {
266 compatible = "arm,idle-state";
267 idle-state-name = "big-retention";
268 arm,psci-suspend-param = <0x00000002>;
269 entry-latency-us = <79>;
270 exit-latency-us = <82>;
271 min-residency-us = <200>;
274 BIG_CPU_SLEEP_1: cpu-sleep-1-1 {
275 compatible = "arm,idle-state";
276 idle-state-name = "big-power-collapse";
277 arm,psci-suspend-param = <0x40000003>;
278 entry-latency-us = <336>;
279 exit-latency-us = <525>;
280 min-residency-us = <1000>;
281 local-timer-stop;
288 compatible = "qcom,scm-msm8998", "qcom,scm";
293 compatible = "qcom,tcsr-mutex";
295 #hwlock-cells = <1>;
299 compatible = "arm,psci-1.0";
303 rpm-glink {
304 compatible = "qcom,glink-rpm";
307 qcom,rpm-msg-ram = <&rpm_msg_ram>;
310 rpm_requests: rpm-requests {
311 compatible = "qcom,rpm-msm8998";
312 qcom,glink-channels = "rpm_requests";
314 rpmcc: clock-controller {
315 compatible = "qcom,rpmcc-msm8998", "qcom,rpmcc";
316 #clock-cells = <1>;
319 rpmpd: power-controller {
320 compatible = "qcom,msm8998-rpmpd";
321 #power-domain-cells = <1>;
322 operating-points-v2 = <&rpmpd_opp_table>;
324 rpmpd_opp_table: opp-table {
325 compatible = "operating-points-v2";
328 opp-level = <16>;
332 opp-level = <32>;
336 opp-level = <48>;
340 opp-level = <64>;
344 opp-level = <128>;
348 opp-level = <192>;
352 opp-level = <256>;
356 opp-level = <320>;
360 opp-level = <384>;
364 opp-level = <512>;
373 memory-region = <&smem_mem>;
377 smp2p-lpass {
385 qcom,local-pid = <0>;
386 qcom,remote-pid = <2>;
388 adsp_smp2p_out: master-kernel {
389 qcom,entry-name = "master-kernel";
390 #qcom,smem-state-cells = <1>;
393 adsp_smp2p_in: slave-kernel {
394 qcom,entry-name = "slave-kernel";
396 interrupt-controller;
397 #interrupt-cells = <2>;
401 smp2p-mpss {
406 qcom,local-pid = <0>;
407 qcom,remote-pid = <1>;
409 modem_smp2p_out: master-kernel {
410 qcom,entry-name = "master-kernel";
411 #qcom,smem-state-cells = <1>;
414 modem_smp2p_in: slave-kernel {
415 qcom,entry-name = "slave-kernel";
416 interrupt-controller;
417 #interrupt-cells = <2>;
421 smp2p-slpi {
426 qcom,local-pid = <0>;
427 qcom,remote-pid = <3>;
429 slpi_smp2p_out: master-kernel {
430 qcom,entry-name = "master-kernel";
431 #qcom,smem-state-cells = <1>;
434 slpi_smp2p_in: slave-kernel {
435 qcom,entry-name = "slave-kernel";
436 interrupt-controller;
437 #interrupt-cells = <2>;
441 thermal-zones {
442 cpu0-thermal {
443 polling-delay-passive = <250>;
444 polling-delay = <1000>;
446 thermal-sensors = <&tsens0 1>;
449 cpu0_alert0: trip-point@0 {
463 cpu1-thermal {
464 polling-delay-passive = <250>;
465 polling-delay = <1000>;
467 thermal-sensors = <&tsens0 2>;
470 cpu1_alert0: trip-point@0 {
484 cpu2-thermal {
485 polling-delay-passive = <250>;
486 polling-delay = <1000>;
488 thermal-sensors = <&tsens0 3>;
491 cpu2_alert0: trip-point@0 {
505 cpu3-thermal {
506 polling-delay-passive = <250>;
507 polling-delay = <1000>;
509 thermal-sensors = <&tsens0 4>;
512 cpu3_alert0: trip-point@0 {
526 cpu4-thermal {
527 polling-delay-passive = <250>;
528 polling-delay = <1000>;
530 thermal-sensors = <&tsens0 7>;
533 cpu4_alert0: trip-point@0 {
547 cpu5-thermal {
548 polling-delay-passive = <250>;
549 polling-delay = <1000>;
551 thermal-sensors = <&tsens0 8>;
554 cpu5_alert0: trip-point@0 {
568 cpu6-thermal {
569 polling-delay-passive = <250>;
570 polling-delay = <1000>;
572 thermal-sensors = <&tsens0 9>;
575 cpu6_alert0: trip-point@0 {
589 cpu7-thermal {
590 polling-delay-passive = <250>;
591 polling-delay = <1000>;
593 thermal-sensors = <&tsens0 10>;
596 cpu7_alert0: trip-point@0 {
610 gpu-thermal-bottom {
611 polling-delay-passive = <250>;
612 polling-delay = <1000>;
614 thermal-sensors = <&tsens0 12>;
617 gpu1_alert0: trip-point@0 {
625 gpu-thermal-top {
626 polling-delay-passive = <250>;
627 polling-delay = <1000>;
629 thermal-sensors = <&tsens0 13>;
632 gpu2_alert0: trip-point@0 {
640 clust0-mhm-thermal {
641 polling-delay-passive = <250>;
642 polling-delay = <1000>;
644 thermal-sensors = <&tsens0 5>;
647 cluster0_mhm_alert0: trip-point@0 {
655 clust1-mhm-thermal {
656 polling-delay-passive = <250>;
657 polling-delay = <1000>;
659 thermal-sensors = <&tsens0 6>;
662 cluster1_mhm_alert0: trip-point@0 {
670 cluster1-l2-thermal {
671 polling-delay-passive = <250>;
672 polling-delay = <1000>;
674 thermal-sensors = <&tsens0 11>;
677 cluster1_l2_alert0: trip-point@0 {
685 modem-thermal {
686 polling-delay-passive = <250>;
687 polling-delay = <1000>;
689 thermal-sensors = <&tsens1 1>;
692 modem_alert0: trip-point@0 {
700 mem-thermal {
701 polling-delay-passive = <250>;
702 polling-delay = <1000>;
704 thermal-sensors = <&tsens1 2>;
707 mem_alert0: trip-point@0 {
715 wlan-thermal {
716 polling-delay-passive = <250>;
717 polling-delay = <1000>;
719 thermal-sensors = <&tsens1 3>;
722 wlan_alert0: trip-point@0 {
730 q6-dsp-thermal {
731 polling-delay-passive = <250>;
732 polling-delay = <1000>;
734 thermal-sensors = <&tsens1 4>;
737 q6_dsp_alert0: trip-point@0 {
745 camera-thermal {
746 polling-delay-passive = <250>;
747 polling-delay = <1000>;
749 thermal-sensors = <&tsens1 5>;
752 camera_alert0: trip-point@0 {
760 multimedia-thermal {
761 polling-delay-passive = <250>;
762 polling-delay = <1000>;
764 thermal-sensors = <&tsens1 6>;
767 multimedia_alert0: trip-point@0 {
777 compatible = "arm,armv8-timer";
785 #address-cells = <1>;
786 #size-cells = <1>;
788 compatible = "simple-bus";
790 gcc: clock-controller@100000 {
791 compatible = "qcom,gcc-msm8998";
792 #clock-cells = <1>;
793 #reset-cells = <1>;
794 #power-domain-cells = <1>;
799 compatible = "qcom,rpm-msg-ram";
806 #address-cells = <1>;
807 #size-cells = <1>;
809 qusb2_hstx_trim: hstx-trim@423a {
816 compatible = "qcom,msm8998-tsens", "qcom,tsens-v2";
821 #thermal-sensor-cells = <1>;
825 compatible = "qcom,msm8998-tsens", "qcom,tsens-v2";
830 #thermal-sensor-cells = <1>;
834 compatible = "qcom,msm8998-smmu-v2", "qcom,smmu-v2";
836 #iommu-cells = <1>;
838 #global-interrupts = <0>;
849 compatible = "qcom,pcie-msm8996";
854 reg-names = "parf", "dbi", "elbi", "config";
856 linux,pci-domain = <0>;
857 bus-range = <0x00 0xff>;
858 #address-cells = <3>;
859 #size-cells = <2>;
860 num-lanes = <1>;
862 phy-names = "pciephy";
867 #interrupt-cells = <1>;
869 interrupt-names = "msi";
870 interrupt-map-mask = <0 0 0 0x7>;
871 interrupt-map = <0 0 0 1 &intc 0 135 IRQ_TYPE_LEVEL_HIGH>,
881 clock-names = "pipe", "bus_master", "bus_slave", "cfg", "aux";
883 power-domains = <&gcc PCIE_0_GDSC>;
884 iommu-map = <0x100 &anoc1_smmu 0x1480 1>;
885 perst-gpios = <&tlmm 35 GPIO_ACTIVE_LOW>;
889 compatible = "qcom,msm8998-qmp-pcie-phy";
891 #address-cells = <1>;
892 #size-cells = <1>;
898 clock-names = "aux", "cfg_ahb", "ref";
901 reset-names = "phy", "common";
903 vdda-phy-supply = <&vreg_l1a_0p875>;
904 vdda-pll-supply = <&vreg_l2a_1p2>;
908 #phy-cells = <0>;
911 clock-names = "pipe0";
912 clock-output-names = "pcie_0_pipe_clk_src";
913 #clock-cells = <0>;
918 compatible = "qcom,msm8998-ufshc", "qcom,ufshc", "jedec,ufs-2.0";
922 phy-names = "ufsphy";
923 lanes-per-direction = <2>;
924 power-domains = <&gcc UFS_GDSC>;
925 #reset-cells = <1>;
927 clock-names =
945 freq-table-hz =
956 reset-names = "rst";
960 compatible = "qcom,msm8998-qmp-ufs-phy";
962 #address-cells = <1>;
963 #size-cells = <1>;
966 clock-names =
973 reset-names = "ufsphy";
982 #phy-cells = <0>;
992 compatible = "qcom,msm8998-pinctrl";
995 gpio-controller;
996 #gpio-cells = <0x2>;
997 interrupt-controller;
998 #interrupt-cells = <0x2>;
1002 compatible = "arm,coresight-stm", "arm,primecell";
1005 reg-names = "stm-base", "stm-data-base";
1008 clock-names = "apb_pclk", "atclk";
1010 out-ports {
1013 remote-endpoint = <&funnel0_in7>;
1020 compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
1024 clock-names = "apb_pclk", "atclk";
1026 out-ports {
1029 remote-endpoint =
1035 in-ports {
1036 #address-cells = <1>;
1037 #size-cells = <0>;
1042 remote-endpoint = <&stm_out>;
1049 compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
1053 clock-names = "apb_pclk", "atclk";
1055 out-ports {
1058 remote-endpoint =
1064 in-ports {
1065 #address-cells = <1>;
1066 #size-cells = <0>;
1071 remote-endpoint =
1079 compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
1083 clock-names = "apb_pclk", "atclk";
1085 out-ports {
1088 remote-endpoint =
1094 in-ports {
1095 #address-cells = <1>;
1096 #size-cells = <0>;
1101 remote-endpoint =
1109 remote-endpoint =
1117 compatible = "arm,coresight-dynamic-replicator", "arm,primecell";
1121 clock-names = "apb_pclk", "atclk";
1123 out-ports {
1126 remote-endpoint = <&etr_in>;
1131 in-ports {
1134 remote-endpoint = <&etf_out>;
1141 compatible = "arm,coresight-tmc", "arm,primecell";
1145 clock-names = "apb_pclk", "atclk";
1147 out-ports {
1150 remote-endpoint =
1156 in-ports {
1159 remote-endpoint =
1167 compatible = "arm,coresight-tmc", "arm,primecell";
1171 clock-names = "apb_pclk", "atclk";
1172 arm,scatter-gather;
1174 in-ports {
1177 remote-endpoint =
1185 compatible = "arm,coresight-etm4x", "arm,primecell";
1189 clock-names = "apb_pclk", "atclk";
1193 out-ports {
1196 remote-endpoint =
1204 compatible = "arm,coresight-etm4x", "arm,primecell";
1208 clock-names = "apb_pclk", "atclk";
1212 out-ports {
1215 remote-endpoint =
1223 compatible = "arm,coresight-etm4x", "arm,primecell";
1227 clock-names = "apb_pclk", "atclk";
1231 out-ports {
1234 remote-endpoint =
1242 compatible = "arm,coresight-etm4x", "arm,primecell";
1246 clock-names = "apb_pclk", "atclk";
1250 out-ports {
1253 remote-endpoint =
1261 compatible = "arm,coresight-etm4x", "arm,primecell";
1265 clock-names = "apb_pclk", "atclk";
1267 out-ports {
1270 remote-endpoint =
1276 in-ports {
1277 #address-cells = <1>;
1278 #size-cells = <0>;
1283 remote-endpoint =
1291 remote-endpoint =
1299 remote-endpoint =
1307 remote-endpoint =
1315 remote-endpoint =
1323 remote-endpoint =
1331 remote-endpoint =
1339 remote-endpoint =
1347 compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
1351 clock-names = "apb_pclk", "atclk";
1353 out-ports {
1356 remote-endpoint =
1362 in-ports {
1365 remote-endpoint =
1373 compatible = "arm,coresight-etm4x", "arm,primecell";
1377 clock-names = "apb_pclk", "atclk";
1383 remote-endpoint = <&apss_funnel_in4>;
1389 compatible = "arm,coresight-etm4x", "arm,primecell";
1393 clock-names = "apb_pclk", "atclk";
1399 remote-endpoint = <&apss_funnel_in5>;
1405 compatible = "arm,coresight-etm4x", "arm,primecell";
1409 clock-names = "apb_pclk", "atclk";
1415 remote-endpoint = <&apss_funnel_in6>;
1421 compatible = "arm,coresight-etm4x", "arm,primecell";
1425 clock-names = "apb_pclk", "atclk";
1431 remote-endpoint = <&apss_funnel_in7>;
1437 compatible = "qcom,spmi-pmic-arb";
1443 reg-names = "core", "chnls", "obsrvr", "intr", "cnfg";
1444 interrupt-names = "periph_irq";
1448 #address-cells = <2>;
1449 #size-cells = <0>;
1450 interrupt-controller;
1451 #interrupt-cells = <4>;
1452 cell-index = <0>;
1456 compatible = "qcom,msm8998-dwc3", "qcom,dwc3";
1459 #address-cells = <1>;
1460 #size-cells = <1>;
1468 clock-names = "cfg_noc", "core", "iface", "mock_utmi",
1471 assigned-clocks = <&gcc GCC_USB30_MOCK_UTMI_CLK>,
1473 assigned-clock-rates = <19200000>, <120000000>;
1477 interrupt-names = "hs_phy_irq", "ss_phy_irq";
1479 power-domains = <&gcc USB_30_GDSC>;
1490 phy-names = "usb2-phy", "usb3-phy";
1491 snps,has-lpm-erratum;
1492 snps,hird-threshold = /bits/ 8 <0x10>;
1497 compatible = "qcom,msm8998-qmp-usb3-phy";
1500 #clock-cells = <1>;
1501 #address-cells = <1>;
1502 #size-cells = <1>;
1508 clock-names = "aux", "cfg_ahb", "ref";
1512 reset-names = "phy", "common";
1520 #phy-cells = <0>;
1522 clock-names = "pipe0";
1523 clock-output-names = "usb3_phy_pipe_clk_src";
1528 compatible = "qcom,msm8998-qusb2-phy";
1531 #phy-cells = <0>;
1535 clock-names = "cfg_ahb", "ref";
1539 nvmem-cells = <&qusb2_hstx_trim>;
1543 compatible = "qcom,sdhci-msm-v4";
1545 reg-names = "hc_mem", "core_mem";
1549 interrupt-names = "hc_irq", "pwr_irq";
1551 clock-names = "iface", "core", "xo";
1555 bus-width = <4>;
1560 compatible = "qcom,i2c-qup-v2.2.1";
1566 clock-names = "core", "iface";
1567 clock-frequency = <400000>;
1570 #address-cells = <1>;
1571 #size-cells = <0>;
1575 compatible = "qcom,i2c-qup-v2.2.1";
1581 clock-names = "core", "iface";
1582 clock-frequency = <400000>;
1585 #address-cells = <1>;
1586 #size-cells = <0>;
1590 compatible = "qcom,i2c-qup-v2.2.1";
1596 clock-names = "core", "iface";
1597 clock-frequency = <400000>;
1600 #address-cells = <1>;
1601 #size-cells = <0>;
1605 compatible = "qcom,i2c-qup-v2.2.1";
1611 clock-names = "core", "iface";
1612 clock-frequency = <400000>;
1615 #address-cells = <1>;
1616 #size-cells = <0>;
1620 compatible = "qcom,i2c-qup-v2.2.1";
1626 clock-names = "core", "iface";
1627 clock-frequency = <400000>;
1630 #address-cells = <1>;
1631 #size-cells = <0>;
1635 compatible = "qcom,i2c-qup-v2.2.1";
1641 clock-names = "core", "iface";
1642 clock-frequency = <400000>;
1645 #address-cells = <1>;
1646 #size-cells = <0>;
1650 compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
1655 clock-names = "core", "iface";
1660 compatible = "qcom,i2c-qup-v2.2.1";
1666 clock-names = "core", "iface";
1667 clock-frequency = <400000>;
1670 #address-cells = <1>;
1671 #size-cells = <0>;
1675 compatible = "qcom,i2c-qup-v2.2.1";
1681 clock-names = "core", "iface";
1682 clock-frequency = <400000>;
1685 #address-cells = <1>;
1686 #size-cells = <0>;
1690 compatible = "qcom,i2c-qup-v2.2.1";
1696 clock-names = "core", "iface";
1697 clock-frequency = <400000>;
1700 #address-cells = <1>;
1701 #size-cells = <0>;
1705 compatible = "qcom,i2c-qup-v2.2.1";
1711 clock-names = "core", "iface";
1712 clock-frequency = <400000>;
1715 #address-cells = <1>;
1716 #size-cells = <0>;
1720 compatible = "qcom,i2c-qup-v2.2.1";
1726 clock-names = "core", "iface";
1727 clock-frequency = <400000>;
1730 #address-cells = <1>;
1731 #size-cells = <0>;
1735 compatible = "qcom,i2c-qup-v2.2.1";
1741 clock-names = "core", "iface";
1742 clock-frequency = <400000>;
1745 #address-cells = <1>;
1746 #size-cells = <0>;
1750 compatible = "qcom,msm8998-apcs-hmss-global";
1753 #mbox-cells = <1>;
1757 #address-cells = <1>;
1758 #size-cells = <1>;
1760 compatible = "arm,armv7-timer-mem";
1764 frame-number = <0>;
1772 frame-number = <1>;
1779 frame-number = <2>;
1786 frame-number = <3>;
1793 frame-number = <4>;
1800 frame-number = <5>;
1807 frame-number = <6>;
1814 intc: interrupt-controller@17a00000 {
1815 compatible = "arm,gic-v3";
1818 #interrupt-cells = <3>;
1819 #address-cells = <1>;
1820 #size-cells = <1>;
1822 interrupt-controller;
1823 #redistributor-regions = <1>;
1824 redistributor-stride = <0x0 0x20000>;
1830 #include "msm8998-pins.dtsi"