Lines Matching +full:phy +full:- +full:device
5 - compatible:
6 * "qcom,mdss-dsi-ctrl"
7 - reg: Physical base address and length of the registers of controller
8 - reg-names: The names of register regions. The following regions are required:
10 - interrupts: The interrupt signal from the DSI block.
11 - power-domains: Should be <&mmcc MDSS_GDSC>.
12 - clocks: Phandles to device clocks.
13 - clock-names: the following clocks are required:
25 - assigned-clocks: Parents of "byte" and "pixel" for the given platform.
26 - assigned-clock-parents: The Byte clock and Pixel clock PLL outputs provided
27 by a DSI PHY block. See [1] for details on clock bindings.
28 - vdd-supply: phandle to vdd regulator device node
29 - vddio-supply: phandle to vdd-io regulator device node
30 - vdda-supply: phandle to vdda regulator device node
31 - phys: phandle to DSI PHY device node
32 - phy-names: the name of the corresponding PHY device
33 - syscon-sfpb: A phandle to mmss_sfpb syscon node (only for DSIv2)
34 - ports: Contains 2 DSI controller ports as child nodes. Each port contains
38 - panel@0: Node of panel connected to this DSI controller.
40 - qcom,dual-dsi-mode: Boolean value indicating if the DSI controller is
42 - qcom,master-dsi: Boolean value indicating if the DSI controller is driving
43 the master link of the 2-DSI panel.
44 - qcom,sync-dual-dsi: Boolean value indicating if the DSI controller is
45 driving a 2-DSI panel whose 2 links need receive command simultaneously.
46 - pinctrl-names: the pin control state names; should contain "default"
47 - pinctrl-0: the default pinctrl state (active)
48 - pinctrl-n: the "sleep" pinctrl state
49 - ports: contains DSI controller input and output ports as children, each
53 - remote-endpoint: For port@0, set to phandle of the connected panel/bridge's
55 device graph info.
57 - data-lanes: this describes how the physical DSI data lanes are mapped
62 [3] for more info on the data-lanes property.
66 data-lanes = <3 0 1 2>;
82 DSI PHY:
84 - compatible: Could be the following
85 * "qcom,dsi-phy-28nm-hpm"
86 * "qcom,dsi-phy-28nm-lp"
87 * "qcom,dsi-phy-20nm"
88 * "qcom,dsi-phy-28nm-8960"
89 * "qcom,dsi-phy-14nm"
90 * "qcom,dsi-phy-10nm"
91 * "qcom,dsi-phy-10nm-8998"
92 - reg: Physical base address and length of the registers of PLL, PHY. Some
93 revisions require the PHY regulator base address, whereas others require the
94 PHY lane base address. See below for each PHY revision.
95 - reg-names: The names of register regions. The following regions are required:
96 For DSI 28nm HPM/LP/8960 PHYs and 20nm PHY:
104 - clock-cells: Must be 1. The DSI PHY block acts as a clock provider, creating
106 - power-domains: Should be <&mmcc MDSS_GDSC>.
107 - clocks: Phandles to device clocks. See [1] for details on clock bindings.
108 - clock-names: the following clocks are required:
112 - vddio-supply: phandle to vdd-io regulator device node
113 For 20nm PHY:
114 - vddio-supply: phandle to vdd-io regulator device node
115 - vcca-supply: phandle to vcca regulator device node
116 For 14nm PHY:
117 - vcca-supply: phandle to vcca regulator device node
118 For 10nm PHY:
119 - vdds-supply: phandle to vdds regulator device node
122 - qcom,dsi-phy-regulator-ldo-mode: Boolean value indicating if the LDO mode PHY
124 - qcom,mdss-mdp-transfer-time-us: Specifies the dsi transfer time for command mode
139 [1] Documentation/devicetree/bindings/clock/clock-bindings.txt
141 [3] Documentation/devicetree/bindings/media/video-interfaces.txt
146 compatible = "qcom,mdss-dsi-ctrl";
147 qcom,dsi-host-index = <0>;
148 interrupt-parent = <&mdp>;
150 reg-names = "dsi_ctrl";
152 power-domains = <&mmcc MDSS_GDSC>;
153 clock-names =
170 assigned-clocks =
173 assigned-clock-parents =
177 vdda-supply = <&pma8084_l2>;
178 vdd-supply = <&pma8084_l22>;
179 vddio-supply = <&pma8084_l12>;
182 phy-names ="dsi-phy";
184 qcom,dual-dsi-mode;
185 qcom,master-dsi;
186 qcom,sync-dual-dsi;
188 qcom,mdss-mdp-transfer-time-us = <12000>;
190 pinctrl-names = "default", "sleep";
191 pinctrl-0 = <&dsi_active>;
192 pinctrl-1 = <&dsi_suspend>;
195 #address-cells = <1>;
196 #size-cells = <0>;
201 remote-endpoint = <&mdp_intf1_out>;
208 remote-endpoint = <&panel_in>;
209 data-lanes = <0 1 2 3>;
219 power-supply = <...>;
224 remote-endpoint = <&dsi0_out>;
230 dsi_phy0: dsi-phy@fd922a00 {
231 compatible = "qcom,dsi-phy-28nm-hpm";
232 qcom,dsi-phy-index = <0>;
233 reg-names =
240 clock-names = "iface";
242 #clock-cells = <1>;
243 vddio-supply = <&pma8084_l12>;
245 qcom,dsi-phy-regulator-ldo-mode;