Lines Matching +full:ddc +full:- +full:i2c +full:- +full:bus
8 - compatible: Should be "mediatek,<chip>-hdmi".
9 - reg: Physical base address and length of the controller's registers
10 - interrupts: The interrupt signal from the function block.
11 - clocks: device clocks
12 See Documentation/devicetree/bindings/clock/clock-bindings.txt for details.
13 - clock-names: must contain "pixel", "pll", "bclk", and "spdif".
14 - phys: phandle link to the HDMI PHY node.
15 See Documentation/devicetree/bindings/phy/phy-bindings.txt for details.
16 - phy-names: must contain "hdmi"
17 - mediatek,syscon-hdmi: phandle link and register offset to the system
20 - ports: A node containing input and output port nodes with endpoint
22 - port@0: The input port in the ports node should be connected to a DPI output
24 - port@1: The output port in the ports node should be connected to the input
25 port of a connector node that contains a ddc-i2c-bus property, or to the
34 - compatible: Should be "mediatek,<chip>-cec"
35 - reg: Physical base address and length of the controller's registers
36 - interrupts: The interrupt signal from the function block.
37 - clocks: device clock
39 HDMI DDC
42 The HDMI DDC i2c controller is used to interface with the HDMI DDC pins.
43 The Mediatek's I2C controller is used to interface with I2C devices.
46 - compatible: Should be "mediatek,<chip>-hdmi-ddc"
47 - reg: Physical base address and length of the controller's registers
48 - clocks: device clock
49 - clock-names: Should be "ddc-i2c".
54 The HDMI PHY serializes the HDMI encoder's three channel 10-bit parallel
58 - compatible: "mediatek,<chip>-hdmi-phy"
59 - reg: Physical base address and length of the module's registers
60 - clocks: PLL reference clock
61 - clock-names: must contain "pll_ref"
62 - clock-output-names: must be "hdmitx_dig_cts" on mt8173
63 - #phy-cells: must be <0>
64 - #clock-cells: must be <0>
67 - mediatek,ibias: TX DRV bias current for <1.65Gbps, defaults to 0xa
68 - mediatek,ibias_up: TX DRV bias current for >1.65Gbps, defaults to 0x1c
73 compatible = "mediatek,mt8173-cec";
79 hdmi_phy: hdmi-phy@10209100 {
80 compatible = "mediatek,mt8173-hdmi-phy";
83 clock-names = "pll_ref";
84 clock-output-names = "hdmitx_dig_cts";
87 #clock-cells = <0>;
88 #phy-cells = <0>;
91 hdmi_ddc0: i2c@11012000 {
92 compatible = "mediatek,mt8173-hdmi-ddc";
96 clock-names = "ddc-i2c";
100 compatible = "mediatek,mt8173-hdmi";
107 clock-names = "pixel", "pll", "bclk", "spdif";
108 pinctrl-names = "default";
109 pinctrl-0 = <&hdmi_pin>;
111 phy-names = "hdmi";
112 mediatek,syscon-hdmi = <&mmsys 0x900>;
113 assigned-clocks = <&topckgen CLK_TOP_HDMI_SEL>;
114 assigned-clock-parents = <&hdmi_phy>;
117 #address-cells = <1>;
118 #size-cells = <0>;
124 remote-endpoint = <&dpi0_out>;
132 remote-endpoint = <&hdmi_con_in>;
139 compatible = "hdmi-connector";
141 ddc-i2c-bus = <&hdmiddc0>;
145 remote-endpoint = <&hdmi0_out>;