Lines Matching +full:lgm +full:- +full:nand
1 // SPDX-License-Identifier: GPL-2.0-only
5 // Copyright Altera Corporation (C) 2012-2014. All rights reserved.
6 // Copyright Intel Corporation (C) 2019-2020. All rights reserved.
7 // Copyright (C) 2020 Texas Instruments Incorporated - http://www.ti.com
12 #include <linux/dma-mapping.h>
29 #include <linux/spi/spi-mem.h>
32 #define CQSPI_NAME "cadence-qspi"
265 u32 reg = readl(cqspi->iobase + CQSPI_REG_CONFIG); in cqspi_is_idle()
272 u32 reg = readl(cqspi->iobase + CQSPI_REG_SDRAMLEVEL); in cqspi_get_rd_sram_level()
284 irq_status = readl(cqspi->iobase + CQSPI_REG_IRQSTATUS); in cqspi_irq_handler()
287 writel(irq_status, cqspi->iobase + CQSPI_REG_IRQSTATUS); in cqspi_irq_handler()
292 complete(&cqspi->transfer_complete); in cqspi_irq_handler()
301 rdreg |= f_pdata->inst_width << CQSPI_REG_RD_INSTR_TYPE_INSTR_LSB; in cqspi_calc_rdreg()
302 rdreg |= f_pdata->addr_width << CQSPI_REG_RD_INSTR_TYPE_ADDR_LSB; in cqspi_calc_rdreg()
303 rdreg |= f_pdata->data_width << CQSPI_REG_RD_INSTR_TYPE_DATA_LSB; in cqspi_calc_rdreg()
312 if (!op->dummy.nbytes) in cqspi_calc_dummy()
315 dummy_clk = op->dummy.nbytes * (8 / op->dummy.buswidth); in cqspi_calc_dummy()
325 f_pdata->inst_width = CQSPI_INST_TYPE_SINGLE; in cqspi_set_protocol()
326 f_pdata->addr_width = CQSPI_INST_TYPE_SINGLE; in cqspi_set_protocol()
327 f_pdata->data_width = CQSPI_INST_TYPE_SINGLE; in cqspi_set_protocol()
330 * For an op to be DTR, cmd phase along with every other non-empty in cqspi_set_protocol()
334 f_pdata->dtr = op->cmd.dtr && in cqspi_set_protocol()
335 (!op->addr.nbytes || op->addr.dtr) && in cqspi_set_protocol()
336 (!op->data.nbytes || op->data.dtr); in cqspi_set_protocol()
338 switch (op->data.buswidth) { in cqspi_set_protocol()
342 f_pdata->data_width = CQSPI_INST_TYPE_SINGLE; in cqspi_set_protocol()
345 f_pdata->data_width = CQSPI_INST_TYPE_DUAL; in cqspi_set_protocol()
348 f_pdata->data_width = CQSPI_INST_TYPE_QUAD; in cqspi_set_protocol()
351 f_pdata->data_width = CQSPI_INST_TYPE_OCTAL; in cqspi_set_protocol()
354 return -EINVAL; in cqspi_set_protocol()
357 /* Right now we only support 8-8-8 DTR mode. */ in cqspi_set_protocol()
358 if (f_pdata->dtr) { in cqspi_set_protocol()
359 switch (op->cmd.buswidth) { in cqspi_set_protocol()
363 f_pdata->inst_width = CQSPI_INST_TYPE_OCTAL; in cqspi_set_protocol()
366 return -EINVAL; in cqspi_set_protocol()
369 switch (op->addr.buswidth) { in cqspi_set_protocol()
373 f_pdata->addr_width = CQSPI_INST_TYPE_OCTAL; in cqspi_set_protocol()
376 return -EINVAL; in cqspi_set_protocol()
379 switch (op->data.buswidth) { in cqspi_set_protocol()
383 f_pdata->data_width = CQSPI_INST_TYPE_OCTAL; in cqspi_set_protocol()
386 return -EINVAL; in cqspi_set_protocol()
416 dev_err(&cqspi->pdev->dev, in cqspi_wait_idle()
419 return -ETIMEDOUT; in cqspi_wait_idle()
428 void __iomem *reg_base = cqspi->iobase; in cqspi_exec_flash_cmd()
441 dev_err(&cqspi->pdev->dev, in cqspi_exec_flash_cmd()
454 struct cqspi_st *cqspi = f_pdata->cqspi; in cqspi_setup_opcode_ext()
455 void __iomem *reg_base = cqspi->iobase; in cqspi_setup_opcode_ext()
459 if (op->cmd.nbytes != 2) in cqspi_setup_opcode_ext()
460 return -EINVAL; in cqspi_setup_opcode_ext()
463 ext = op->cmd.opcode & 0xff; in cqspi_setup_opcode_ext()
477 struct cqspi_st *cqspi = f_pdata->cqspi; in cqspi_enable_dtr()
478 void __iomem *reg_base = cqspi->iobase; in cqspi_enable_dtr()
509 struct cqspi_st *cqspi = f_pdata->cqspi; in cqspi_command_read()
510 void __iomem *reg_base = cqspi->iobase; in cqspi_command_read()
511 u8 *rxbuf = op->data.buf.in; in cqspi_command_read()
513 size_t n_rx = op->data.nbytes; in cqspi_command_read()
525 f_pdata->dtr); in cqspi_command_read()
530 dev_err(&cqspi->pdev->dev, in cqspi_command_read()
533 return -EINVAL; in cqspi_command_read()
536 if (f_pdata->dtr) in cqspi_command_read()
537 opcode = op->cmd.opcode >> 8; in cqspi_command_read()
539 opcode = op->cmd.opcode; in cqspi_command_read()
546 dummy_clk = cqspi_calc_dummy(op, f_pdata->dtr); in cqspi_command_read()
548 return -EOPNOTSUPP; in cqspi_command_read()
557 reg |= (((n_rx - 1) & CQSPI_REG_CMDCTRL_RD_BYTES_MASK) in cqspi_command_read()
573 read_len = n_rx - read_len; in cqspi_command_read()
583 struct cqspi_st *cqspi = f_pdata->cqspi; in cqspi_command_write()
584 void __iomem *reg_base = cqspi->iobase; in cqspi_command_write()
586 const u8 *txbuf = op->data.buf.out; in cqspi_command_write()
587 size_t n_tx = op->data.nbytes; in cqspi_command_write()
598 f_pdata->dtr); in cqspi_command_write()
603 dev_err(&cqspi->pdev->dev, in cqspi_command_write()
606 return -EINVAL; in cqspi_command_write()
612 if (f_pdata->dtr) in cqspi_command_write()
613 opcode = op->cmd.opcode >> 8; in cqspi_command_write()
615 opcode = op->cmd.opcode; in cqspi_command_write()
619 if (op->addr.nbytes) { in cqspi_command_write()
621 reg |= ((op->addr.nbytes - 1) & in cqspi_command_write()
625 writel(op->addr.val, reg_base + CQSPI_REG_CMDADDRESS); in cqspi_command_write()
630 reg |= ((n_tx - 1) & CQSPI_REG_CMDCTRL_WR_BYTES_MASK) in cqspi_command_write()
640 write_len = n_tx - 4; in cqspi_command_write()
652 struct cqspi_st *cqspi = f_pdata->cqspi; in cqspi_read_setup()
653 void __iomem *reg_base = cqspi->iobase; in cqspi_read_setup()
660 f_pdata->dtr); in cqspi_read_setup()
664 if (f_pdata->dtr) in cqspi_read_setup()
665 opcode = op->cmd.opcode >> 8; in cqspi_read_setup()
667 opcode = op->cmd.opcode; in cqspi_read_setup()
673 dummy_clk = cqspi_calc_dummy(op, f_pdata->dtr); in cqspi_read_setup()
676 return -EOPNOTSUPP; in cqspi_read_setup()
687 reg |= (op->addr.nbytes - 1); in cqspi_read_setup()
696 struct cqspi_st *cqspi = f_pdata->cqspi; in cqspi_indirect_read_execute()
697 struct device *dev = &cqspi->pdev->dev; in cqspi_indirect_read_execute()
698 void __iomem *reg_base = cqspi->iobase; in cqspi_indirect_read_execute()
699 void __iomem *ahb_base = cqspi->ahb_base; in cqspi_indirect_read_execute()
714 reinit_completion(&cqspi->transfer_complete); in cqspi_indirect_read_execute()
719 if (!wait_for_completion_timeout(&cqspi->transfer_complete, in cqspi_indirect_read_execute()
721 ret = -ETIMEDOUT; in cqspi_indirect_read_execute()
733 bytes_to_read *= cqspi->fifo_width; in cqspi_indirect_read_execute()
746 (rxbuf_end - rxbuf), in cqspi_indirect_read_execute()
750 remaining -= bytes_to_read; in cqspi_indirect_read_execute()
755 reinit_completion(&cqspi->transfer_complete); in cqspi_indirect_read_execute()
789 struct cqspi_st *cqspi = f_pdata->cqspi; in cqspi_write_setup()
790 void __iomem *reg_base = cqspi->iobase; in cqspi_write_setup()
794 f_pdata->dtr); in cqspi_write_setup()
798 if (f_pdata->dtr) in cqspi_write_setup()
799 opcode = op->cmd.opcode >> 8; in cqspi_write_setup()
801 opcode = op->cmd.opcode; in cqspi_write_setup()
805 reg |= f_pdata->data_width << CQSPI_REG_WR_INSTR_TYPE_DATA_LSB; in cqspi_write_setup()
806 reg |= f_pdata->addr_width << CQSPI_REG_WR_INSTR_TYPE_ADDR_LSB; in cqspi_write_setup()
812 * SPI NAND flashes require the address of the status register to be in cqspi_write_setup()
814 * cypress Semper flash expect a 4-byte dummy address in the Read SR in cqspi_write_setup()
818 * command when doing auto-HW polling. So, disable write completion in cqspi_write_setup()
819 * polling on the controller's side. spinand and spi-nor will take in cqspi_write_setup()
828 reg |= (op->addr.nbytes - 1); in cqspi_write_setup()
837 struct cqspi_st *cqspi = f_pdata->cqspi; in cqspi_indirect_write_execute()
838 struct device *dev = &cqspi->pdev->dev; in cqspi_indirect_write_execute()
839 void __iomem *reg_base = cqspi->iobase; in cqspi_indirect_write_execute()
852 reinit_completion(&cqspi->transfer_complete); in cqspi_indirect_write_execute()
862 if (cqspi->wr_delay) in cqspi_indirect_write_execute()
863 ndelay(cqspi->wr_delay); in cqspi_indirect_write_execute()
873 iowrite32_rep(cqspi->ahb_base, txbuf, write_words); in cqspi_indirect_write_execute()
880 iowrite32(temp, cqspi->ahb_base); in cqspi_indirect_write_execute()
884 if (!wait_for_completion_timeout(&cqspi->transfer_complete, in cqspi_indirect_write_execute()
887 ret = -ETIMEDOUT; in cqspi_indirect_write_execute()
891 remaining -= write_bytes; in cqspi_indirect_write_execute()
894 reinit_completion(&cqspi->transfer_complete); in cqspi_indirect_write_execute()
927 struct cqspi_st *cqspi = f_pdata->cqspi; in cqspi_chipselect()
928 void __iomem *reg_base = cqspi->iobase; in cqspi_chipselect()
929 unsigned int chip_select = f_pdata->cs; in cqspi_chipselect()
933 if (cqspi->is_decoded_cs) { in cqspi_chipselect()
967 struct cqspi_st *cqspi = f_pdata->cqspi; in cqspi_delay()
968 void __iomem *iobase = cqspi->iobase; in cqspi_delay()
969 const unsigned int ref_clk_hz = cqspi->master_ref_clk_hz; in cqspi_delay()
975 tsclk = DIV_ROUND_UP(ref_clk_hz, cqspi->sclk); in cqspi_delay()
977 tshsl = calculate_ticks_for_ns(ref_clk_hz, f_pdata->tshsl_ns); in cqspi_delay()
982 tchsh = calculate_ticks_for_ns(ref_clk_hz, f_pdata->tchsh_ns); in cqspi_delay()
983 tslch = calculate_ticks_for_ns(ref_clk_hz, f_pdata->tslch_ns); in cqspi_delay()
984 tsd2d = calculate_ticks_for_ns(ref_clk_hz, f_pdata->tsd2d_ns); in cqspi_delay()
999 const unsigned int ref_clk_hz = cqspi->master_ref_clk_hz; in cqspi_config_baudrate_div()
1000 void __iomem *reg_base = cqspi->iobase; in cqspi_config_baudrate_div()
1004 div = DIV_ROUND_UP(ref_clk_hz, 2 * cqspi->sclk) - 1; in cqspi_config_baudrate_div()
1016 void __iomem *reg_base = cqspi->iobase; in cqspi_readdata_capture()
1037 void __iomem *reg_base = cqspi->iobase; in cqspi_controller_enable()
1053 struct cqspi_st *cqspi = f_pdata->cqspi; in cqspi_configure()
1054 int switch_cs = (cqspi->current_cs != f_pdata->cs); in cqspi_configure()
1055 int switch_ck = (cqspi->sclk != sclk); in cqspi_configure()
1062 cqspi->current_cs = f_pdata->cs; in cqspi_configure()
1068 cqspi->sclk = sclk; in cqspi_configure()
1071 cqspi_readdata_capture(cqspi, !cqspi->rclk_en, in cqspi_configure()
1072 f_pdata->read_delay); in cqspi_configure()
1082 struct cqspi_st *cqspi = f_pdata->cqspi; in cqspi_write()
1083 loff_t to = op->addr.val; in cqspi_write()
1084 size_t len = op->data.nbytes; in cqspi_write()
1085 const u_char *buf = op->data.buf.out; in cqspi_write()
1097 * Some flashes like the Cypress Semper flash expect a dummy 4-byte in cqspi_write()
1104 if (!f_pdata->dtr && cqspi->use_direct_mode && in cqspi_write()
1105 ((to + len) <= cqspi->ahb_size)) { in cqspi_write()
1106 memcpy_toio(cqspi->ahb_base + to, buf, len); in cqspi_write()
1117 complete(&cqspi->rx_dma_complete); in cqspi_rx_dma_callback()
1123 struct cqspi_st *cqspi = f_pdata->cqspi; in cqspi_direct_read_execute()
1124 struct device *dev = &cqspi->pdev->dev; in cqspi_direct_read_execute()
1126 dma_addr_t dma_src = (dma_addr_t)cqspi->mmap_phys_base + from; in cqspi_direct_read_execute()
1133 if (!cqspi->rx_chan || !virt_addr_valid(buf)) { in cqspi_direct_read_execute()
1134 memcpy_fromio(buf, cqspi->ahb_base + from, len); in cqspi_direct_read_execute()
1138 ddev = cqspi->rx_chan->device->dev; in cqspi_direct_read_execute()
1142 return -ENOMEM; in cqspi_direct_read_execute()
1144 tx = dmaengine_prep_dma_memcpy(cqspi->rx_chan, dma_dst, dma_src, in cqspi_direct_read_execute()
1148 ret = -EIO; in cqspi_direct_read_execute()
1152 tx->callback = cqspi_rx_dma_callback; in cqspi_direct_read_execute()
1153 tx->callback_param = cqspi; in cqspi_direct_read_execute()
1154 cookie = tx->tx_submit(tx); in cqspi_direct_read_execute()
1155 reinit_completion(&cqspi->rx_dma_complete); in cqspi_direct_read_execute()
1160 ret = -EIO; in cqspi_direct_read_execute()
1164 dma_async_issue_pending(cqspi->rx_chan); in cqspi_direct_read_execute()
1165 if (!wait_for_completion_timeout(&cqspi->rx_dma_complete, in cqspi_direct_read_execute()
1167 dmaengine_terminate_sync(cqspi->rx_chan); in cqspi_direct_read_execute()
1169 ret = -ETIMEDOUT; in cqspi_direct_read_execute()
1182 struct cqspi_st *cqspi = f_pdata->cqspi; in cqspi_read()
1183 loff_t from = op->addr.val; in cqspi_read()
1184 size_t len = op->data.nbytes; in cqspi_read()
1185 u_char *buf = op->data.buf.in; in cqspi_read()
1196 if (cqspi->use_direct_mode && ((from + len) <= cqspi->ahb_size)) in cqspi_read()
1204 struct cqspi_st *cqspi = spi_master_get_devdata(mem->spi->master); in cqspi_mem_process()
1207 f_pdata = &cqspi->f_pdata[mem->spi->chip_select]; in cqspi_mem_process()
1208 cqspi_configure(f_pdata, mem->spi->max_speed_hz); in cqspi_mem_process()
1210 if (op->data.dir == SPI_MEM_DATA_IN && op->data.buf.in) { in cqspi_mem_process()
1211 if (!op->addr.nbytes) in cqspi_mem_process()
1217 if (!op->addr.nbytes || !op->data.buf.out) in cqspi_mem_process()
1229 dev_err(&mem->spi->dev, "operation failed with %d\n", ret); in cqspi_exec_mem_op()
1240 * op->dummy.dtr is required for converting nbytes into ncycles. in cqspi_supports_mem_op()
1243 all_true = op->cmd.dtr && in cqspi_supports_mem_op()
1244 (!op->addr.nbytes || op->addr.dtr) && in cqspi_supports_mem_op()
1245 (!op->dummy.nbytes || op->dummy.dtr) && in cqspi_supports_mem_op()
1246 (!op->data.nbytes || op->data.dtr); in cqspi_supports_mem_op()
1248 all_false = !op->cmd.dtr && !op->addr.dtr && !op->dummy.dtr && in cqspi_supports_mem_op()
1249 !op->data.dtr; in cqspi_supports_mem_op()
1265 if (of_property_read_u32(np, "cdns,read-delay", &f_pdata->read_delay)) { in cqspi_of_get_flash_pdata()
1266 dev_err(&pdev->dev, "couldn't determine read-delay\n"); in cqspi_of_get_flash_pdata()
1267 return -ENXIO; in cqspi_of_get_flash_pdata()
1270 if (of_property_read_u32(np, "cdns,tshsl-ns", &f_pdata->tshsl_ns)) { in cqspi_of_get_flash_pdata()
1271 dev_err(&pdev->dev, "couldn't determine tshsl-ns\n"); in cqspi_of_get_flash_pdata()
1272 return -ENXIO; in cqspi_of_get_flash_pdata()
1275 if (of_property_read_u32(np, "cdns,tsd2d-ns", &f_pdata->tsd2d_ns)) { in cqspi_of_get_flash_pdata()
1276 dev_err(&pdev->dev, "couldn't determine tsd2d-ns\n"); in cqspi_of_get_flash_pdata()
1277 return -ENXIO; in cqspi_of_get_flash_pdata()
1280 if (of_property_read_u32(np, "cdns,tchsh-ns", &f_pdata->tchsh_ns)) { in cqspi_of_get_flash_pdata()
1281 dev_err(&pdev->dev, "couldn't determine tchsh-ns\n"); in cqspi_of_get_flash_pdata()
1282 return -ENXIO; in cqspi_of_get_flash_pdata()
1285 if (of_property_read_u32(np, "cdns,tslch-ns", &f_pdata->tslch_ns)) { in cqspi_of_get_flash_pdata()
1286 dev_err(&pdev->dev, "couldn't determine tslch-ns\n"); in cqspi_of_get_flash_pdata()
1287 return -ENXIO; in cqspi_of_get_flash_pdata()
1290 if (of_property_read_u32(np, "spi-max-frequency", &f_pdata->clk_rate)) { in cqspi_of_get_flash_pdata()
1291 dev_err(&pdev->dev, "couldn't determine spi-max-frequency\n"); in cqspi_of_get_flash_pdata()
1292 return -ENXIO; in cqspi_of_get_flash_pdata()
1300 struct device *dev = &cqspi->pdev->dev; in cqspi_of_get_pdata()
1301 struct device_node *np = dev->of_node; in cqspi_of_get_pdata()
1303 cqspi->is_decoded_cs = of_property_read_bool(np, "cdns,is-decoded-cs"); in cqspi_of_get_pdata()
1305 if (of_property_read_u32(np, "cdns,fifo-depth", &cqspi->fifo_depth)) { in cqspi_of_get_pdata()
1306 dev_err(dev, "couldn't determine fifo-depth\n"); in cqspi_of_get_pdata()
1307 return -ENXIO; in cqspi_of_get_pdata()
1310 if (of_property_read_u32(np, "cdns,fifo-width", &cqspi->fifo_width)) { in cqspi_of_get_pdata()
1311 dev_err(dev, "couldn't determine fifo-width\n"); in cqspi_of_get_pdata()
1312 return -ENXIO; in cqspi_of_get_pdata()
1315 if (of_property_read_u32(np, "cdns,trigger-address", in cqspi_of_get_pdata()
1316 &cqspi->trigger_address)) { in cqspi_of_get_pdata()
1317 dev_err(dev, "couldn't determine trigger-address\n"); in cqspi_of_get_pdata()
1318 return -ENXIO; in cqspi_of_get_pdata()
1321 if (of_property_read_u32(np, "num-cs", &cqspi->num_chipselect)) in cqspi_of_get_pdata()
1322 cqspi->num_chipselect = CQSPI_MAX_CHIPSELECT; in cqspi_of_get_pdata()
1324 cqspi->rclk_en = of_property_read_bool(np, "cdns,rclk-en"); in cqspi_of_get_pdata()
1336 writel(0, cqspi->iobase + CQSPI_REG_REMAP); in cqspi_controller_init()
1339 writel(0, cqspi->iobase + CQSPI_REG_IRQMASK); in cqspi_controller_init()
1342 writel(cqspi->fifo_depth / 2, cqspi->iobase + CQSPI_REG_SRAMPARTITION); in cqspi_controller_init()
1345 writel(cqspi->trigger_address, in cqspi_controller_init()
1346 cqspi->iobase + CQSPI_REG_INDIRECTTRIGGER); in cqspi_controller_init()
1348 /* Program read watermark -- 1/2 of the FIFO. */ in cqspi_controller_init()
1349 writel(cqspi->fifo_depth * cqspi->fifo_width / 2, in cqspi_controller_init()
1350 cqspi->iobase + CQSPI_REG_INDIRECTRDWATERMARK); in cqspi_controller_init()
1351 /* Program write watermark -- 1/8 of the FIFO. */ in cqspi_controller_init()
1352 writel(cqspi->fifo_depth * cqspi->fifo_width / 8, in cqspi_controller_init()
1353 cqspi->iobase + CQSPI_REG_INDIRECTWRWATERMARK); in cqspi_controller_init()
1356 if (!cqspi->use_direct_mode) { in cqspi_controller_init()
1357 reg = readl(cqspi->iobase + CQSPI_REG_CONFIG); in cqspi_controller_init()
1359 writel(reg, cqspi->iobase + CQSPI_REG_CONFIG); in cqspi_controller_init()
1372 cqspi->rx_chan = dma_request_chan_by_mask(&mask); in cqspi_request_mmap_dma()
1373 if (IS_ERR(cqspi->rx_chan)) { in cqspi_request_mmap_dma()
1374 int ret = PTR_ERR(cqspi->rx_chan); in cqspi_request_mmap_dma()
1375 cqspi->rx_chan = NULL; in cqspi_request_mmap_dma()
1376 return dev_err_probe(&cqspi->pdev->dev, ret, "No Rx DMA available\n"); in cqspi_request_mmap_dma()
1378 init_completion(&cqspi->rx_dma_complete); in cqspi_request_mmap_dma()
1385 struct cqspi_st *cqspi = spi_master_get_devdata(mem->spi->master); in cqspi_get_name()
1386 struct device *dev = &cqspi->pdev->dev; in cqspi_get_name()
1388 return devm_kasprintf(dev, GFP_KERNEL, "%s.%d", dev_name(dev), mem->spi->chip_select); in cqspi_get_name()
1399 struct platform_device *pdev = cqspi->pdev; in cqspi_setup_flash()
1400 struct device *dev = &pdev->dev; in cqspi_setup_flash()
1401 struct device_node *np = dev->of_node; in cqspi_setup_flash()
1407 for_each_available_child_of_node(dev->of_node, np) { in cqspi_setup_flash()
1418 return -EINVAL; in cqspi_setup_flash()
1421 f_pdata = &cqspi->f_pdata[cs]; in cqspi_setup_flash()
1422 f_pdata->cqspi = cqspi; in cqspi_setup_flash()
1423 f_pdata->cs = cs; in cqspi_setup_flash()
1439 struct device *dev = &pdev->dev; in cqspi_probe()
1447 master = spi_alloc_master(&pdev->dev, sizeof(*cqspi)); in cqspi_probe()
1449 dev_err(&pdev->dev, "spi_alloc_master failed\n"); in cqspi_probe()
1450 return -ENOMEM; in cqspi_probe()
1452 master->mode_bits = SPI_RX_QUAD | SPI_RX_DUAL; in cqspi_probe()
1453 master->mem_ops = &cqspi_mem_ops; in cqspi_probe()
1454 master->dev.of_node = pdev->dev.of_node; in cqspi_probe()
1458 cqspi->pdev = pdev; in cqspi_probe()
1465 ret = -ENODEV; in cqspi_probe()
1470 cqspi->clk = devm_clk_get(dev, NULL); in cqspi_probe()
1471 if (IS_ERR(cqspi->clk)) { in cqspi_probe()
1473 ret = PTR_ERR(cqspi->clk); in cqspi_probe()
1479 cqspi->iobase = devm_ioremap_resource(dev, res); in cqspi_probe()
1480 if (IS_ERR(cqspi->iobase)) { in cqspi_probe()
1482 ret = PTR_ERR(cqspi->iobase); in cqspi_probe()
1488 cqspi->ahb_base = devm_ioremap_resource(dev, res_ahb); in cqspi_probe()
1489 if (IS_ERR(cqspi->ahb_base)) { in cqspi_probe()
1491 ret = PTR_ERR(cqspi->ahb_base); in cqspi_probe()
1494 cqspi->mmap_phys_base = (dma_addr_t)res_ahb->start; in cqspi_probe()
1495 cqspi->ahb_size = resource_size(res_ahb); in cqspi_probe()
1497 init_completion(&cqspi->transfer_complete); in cqspi_probe()
1502 ret = -ENXIO; in cqspi_probe()
1513 ret = clk_prepare_enable(cqspi->clk); in cqspi_probe()
1527 rstc_ocp = devm_reset_control_get_optional_exclusive(dev, "qspi-ocp"); in cqspi_probe()
1540 cqspi->master_ref_clk_hz = clk_get_rate(cqspi->clk); in cqspi_probe()
1541 master->max_speed_hz = cqspi->master_ref_clk_hz; in cqspi_probe()
1544 if (ddata->quirks & CQSPI_NEEDS_WR_DELAY) in cqspi_probe()
1545 cqspi->wr_delay = 50 * DIV_ROUND_UP(NSEC_PER_SEC, in cqspi_probe()
1546 cqspi->master_ref_clk_hz); in cqspi_probe()
1547 if (ddata->hwcaps_mask & CQSPI_SUPPORTS_OCTAL) in cqspi_probe()
1548 master->mode_bits |= SPI_RX_OCTAL | SPI_TX_OCTAL; in cqspi_probe()
1549 if (!(ddata->quirks & CQSPI_DISABLE_DAC_MODE)) in cqspi_probe()
1550 cqspi->use_direct_mode = true; in cqspi_probe()
1554 pdev->name, cqspi); in cqspi_probe()
1562 cqspi->current_cs = -1; in cqspi_probe()
1563 cqspi->sclk = 0; in cqspi_probe()
1565 master->num_chipselect = cqspi->num_chipselect; in cqspi_probe()
1573 if (cqspi->use_direct_mode) { in cqspi_probe()
1575 if (ret == -EPROBE_DEFER) in cqspi_probe()
1581 dev_err(&pdev->dev, "failed to register SPI ctlr %d\n", ret); in cqspi_probe()
1589 clk_disable_unprepare(cqspi->clk); in cqspi_probe()
1604 if (cqspi->rx_chan) in cqspi_remove()
1605 dma_release_channel(cqspi->rx_chan); in cqspi_remove()
1607 clk_disable_unprepare(cqspi->clk); in cqspi_remove()
1609 pm_runtime_put_sync(&pdev->dev); in cqspi_remove()
1610 pm_runtime_disable(&pdev->dev); in cqspi_remove()
1661 .compatible = "cdns,qspi-nor",
1665 .compatible = "ti,k2g-qspi",
1669 .compatible = "ti,am654-ospi",
1673 .compatible = "intel,lgm-qspi",