224 #define spi_readl(port, reg) \  macro
354 		mr = spi_readl(as, MR);  in cs_activate()
362 			csr = spi_readl(as, CSR0 + 4 * i);  in cs_activate()
368 		mr = spi_readl(as, MR);  in cs_activate()
389 	mr = spi_readl(as, MR);  in cs_deactivate()
587 	spi_readl(as, RDR);  in atmel_spi_next_xfer_single()
588 	while (spi_readl(as, SR) & SPI_BIT(RDRF)) {  in atmel_spi_next_xfer_single()
589 		spi_readl(as, RDR);  in atmel_spi_next_xfer_single()
631 	while (spi_readl(as, FLR))  in atmel_spi_next_xfer_fifo()
635 	fifomr = spi_readl(as, FMR);  in atmel_spi_next_xfer_fifo()
639 	(void)spi_readl(as, SR);  in atmel_spi_next_xfer_fifo()
841 	csr = spi_readl(as, CSR0 + 4 * chip_select);  in atmel_spi_set_xfer_speed()
978 		*rxp16 = spi_readl(as, RDR);  in atmel_spi_pump_single_data()
981 		*rxp = spi_readl(as, RDR);  in atmel_spi_pump_single_data()
996 	u32 fifolr = spi_readl(as, FLR);  in atmel_spi_pump_fifo_data()
1019 		rd = spi_readl(as, RDR);  in atmel_spi_pump_fifo_data()
1054 	imr = spi_readl(as, IMR);  in atmel_spi_pio_interrupt()
1055 	status = spi_readl(as, SR);  in atmel_spi_pio_interrupt()
1076 		spi_readl(as, SR);  in atmel_spi_pio_interrupt()
1111 	imr = spi_readl(as, IMR);  in atmel_spi_pdc_interrupt()
1112 	status = spi_readl(as, SR);  in atmel_spi_pdc_interrupt()
1123 		spi_readl(as, SR);  in atmel_spi_pdc_interrupt()
1357 				spi_readl(as, TCR), spi_readl(as, RCR));  in atmel_spi_one_transfer()
1368 				if (spi_readl(as, SR) & SPI_BIT(TXEMPTY))  in atmel_spi_one_transfer()
1373 			while (spi_readl(as, SR) & SPI_BIT(RDRF))  in atmel_spi_one_transfer()
1374 				spi_readl(as, RDR);  in atmel_spi_one_transfer()
1377 			spi_readl(as, SR);  in atmel_spi_one_transfer()
1407 	return spi_readl(as, VERSION) & 0x00000fff;  in atmel_get_version()
1629 	spi_readl(as, SR);  in atmel_spi_remove()