Lines Matching +full:0 +full:x78000
50 .ctl_reg = 0x1000 * id, \
51 .io_reg = 0x4 + 0x1000 * id, \
52 .intr_cfg_reg = 0x8 + 0x1000 * id, \
53 .intr_status_reg = 0xc + 0x1000 * id, \
54 .intr_target_reg = 0x8 + 0x1000 * id, \
57 .pull_bit = 0, \
60 .in_bit = 0, \
62 .intr_enable_bit = 0, \
63 .intr_status_bit = 0, \
78 .io_reg = 0, \
79 .intr_cfg_reg = 0, \
80 .intr_status_reg = 0, \
81 .intr_target_reg = 0, \
104 .io_reg = offset + 0x4, \
105 .intr_cfg_reg = 0, \
106 .intr_status_reg = 0, \
107 .intr_target_reg = 0, \
111 .drv_bit = 0, \
114 .out_bit = 0, \
124 PINCTRL_PIN(0, "GPIO_0"),
249 DECLARE_MSM_GPIO_PINS(0);
755 [0] = PINGROUP(0, WEST, qup0, m_voc, ddr_bist, _, phase_flag, qdss_gpio, atest, _, _),
868 [113] = UFS_RESET(ufs_reset, 0x78000),
869 [114] = SDC_QDSD_PINGROUP(sdc1_rclk, WEST, 0x75000, 15, 0),
870 [115] = SDC_QDSD_PINGROUP(sdc1_clk, WEST, 0x75000, 13, 6),
871 [116] = SDC_QDSD_PINGROUP(sdc1_cmd, WEST, 0x75000, 11, 3),
872 [117] = SDC_QDSD_PINGROUP(sdc1_data, WEST, 0x75000, 9, 0),
873 [118] = SDC_QDSD_PINGROUP(sdc2_clk, SOUTH, 0x73000, 14, 6),
874 [119] = SDC_QDSD_PINGROUP(sdc2_cmd, SOUTH, 0x73000, 11, 3),
875 [120] = SDC_QDSD_PINGROUP(sdc2_data, SOUTH, 0x73000, 9, 0),