Lines Matching +full:emc +full:- +full:timings +full:-
1 // SPDX-License-Identifier: GPL-2.0
13 #include <linux/interconnect-provider.h>
185 struct emc_timing *timings; member
195 * There are multiple sources in the EMC driver which could request
200 /* protect shared rate-change code path */
208 struct tegra_emc *emc = data; in tegra_emc_isr() local
212 status = readl_relaxed(emc->regs + EMC_INTSTATUS) & intmask; in tegra_emc_isr()
218 dev_err_ratelimited(emc->dev, in tegra_emc_isr()
222 writel_relaxed(status, emc->regs + EMC_INTSTATUS); in tegra_emc_isr()
227 static struct emc_timing *tegra_emc_find_timing(struct tegra_emc *emc, in tegra_emc_find_timing() argument
233 for (i = 0; i < emc->num_timings; i++) { in tegra_emc_find_timing()
234 if (emc->timings[i].rate >= rate) { in tegra_emc_find_timing()
235 timing = &emc->timings[i]; in tegra_emc_find_timing()
241 dev_err(emc->dev, "no timing for rate %lu\n", rate); in tegra_emc_find_timing()
248 static int emc_prepare_timing_change(struct tegra_emc *emc, unsigned long rate) in emc_prepare_timing_change() argument
250 struct emc_timing *timing = tegra_emc_find_timing(emc, rate); in emc_prepare_timing_change()
254 return -EINVAL; in emc_prepare_timing_change()
256 dev_dbg(emc->dev, "%s: using timing rate %lu for requested rate %lu\n", in emc_prepare_timing_change()
257 __func__, timing->rate, rate); in emc_prepare_timing_change()
260 for (i = 0; i < ARRAY_SIZE(timing->data); i++) in emc_prepare_timing_change()
261 writel_relaxed(timing->data[i], in emc_prepare_timing_change()
262 emc->regs + emc_timing_registers[i]); in emc_prepare_timing_change()
265 readl_relaxed(emc->regs + emc_timing_registers[i - 1]); in emc_prepare_timing_change()
270 static int emc_complete_timing_change(struct tegra_emc *emc, bool flush) in emc_complete_timing_change() argument
275 dev_dbg(emc->dev, "%s: flush %d\n", __func__, flush); in emc_complete_timing_change()
280 emc->regs + EMC_TIMING_CONTROL); in emc_complete_timing_change()
284 err = readl_relaxed_poll_timeout_atomic(emc->regs + EMC_INTSTATUS, v, in emc_complete_timing_change()
288 dev_err(emc->dev, "emc-car handshake timeout: %d\n", err); in emc_complete_timing_change()
298 struct tegra_emc *emc = container_of(nb, struct tegra_emc, clk_nb); in tegra_emc_clk_change_notify() local
304 err = emc_prepare_timing_change(emc, cnd->new_rate); in tegra_emc_clk_change_notify()
308 err = emc_prepare_timing_change(emc, cnd->old_rate); in tegra_emc_clk_change_notify()
312 err = emc_complete_timing_change(emc, true); in tegra_emc_clk_change_notify()
316 err = emc_complete_timing_change(emc, false); in tegra_emc_clk_change_notify()
326 static int load_one_timing_from_dt(struct tegra_emc *emc, in load_one_timing_from_dt() argument
333 if (!of_device_is_compatible(node, "nvidia,tegra20-emc-table")) { in load_one_timing_from_dt()
334 dev_err(emc->dev, "incompatible DT node: %pOF\n", node); in load_one_timing_from_dt()
335 return -EINVAL; in load_one_timing_from_dt()
338 err = of_property_read_u32(node, "clock-frequency", &rate); in load_one_timing_from_dt()
340 dev_err(emc->dev, "timing %pOF: failed to read rate: %d\n", in load_one_timing_from_dt()
345 err = of_property_read_u32_array(node, "nvidia,emc-registers", in load_one_timing_from_dt()
346 timing->data, in load_one_timing_from_dt()
349 dev_err(emc->dev, in load_one_timing_from_dt()
350 "timing %pOF: failed to read emc timing data: %d\n", in load_one_timing_from_dt()
356 * The EMC clock rate is twice the bus rate, and the bus rate is in load_one_timing_from_dt()
359 timing->rate = rate * 2 * 1000; in load_one_timing_from_dt()
361 dev_dbg(emc->dev, "%s: %pOF: EMC rate %lu\n", in load_one_timing_from_dt()
362 __func__, node, timing->rate); in load_one_timing_from_dt()
372 if (a->rate < b->rate) in cmp_timings()
373 return -1; in cmp_timings()
375 if (a->rate > b->rate) in cmp_timings()
381 static int tegra_emc_load_timings_from_dt(struct tegra_emc *emc, in tegra_emc_load_timings_from_dt() argument
391 dev_err(emc->dev, "no memory timings in DT node: %pOF\n", node); in tegra_emc_load_timings_from_dt()
392 return -EINVAL; in tegra_emc_load_timings_from_dt()
395 emc->timings = devm_kcalloc(emc->dev, child_count, sizeof(*timing), in tegra_emc_load_timings_from_dt()
397 if (!emc->timings) in tegra_emc_load_timings_from_dt()
398 return -ENOMEM; in tegra_emc_load_timings_from_dt()
400 emc->num_timings = child_count; in tegra_emc_load_timings_from_dt()
401 timing = emc->timings; in tegra_emc_load_timings_from_dt()
404 err = load_one_timing_from_dt(emc, timing++, child); in tegra_emc_load_timings_from_dt()
411 sort(emc->timings, emc->num_timings, sizeof(*timing), cmp_timings, in tegra_emc_load_timings_from_dt()
414 dev_info_once(emc->dev, in tegra_emc_load_timings_from_dt()
415 "got %u timings for RAM code %u (min %luMHz max %luMHz)\n", in tegra_emc_load_timings_from_dt()
416 emc->num_timings, in tegra_emc_load_timings_from_dt()
418 emc->timings[0].rate / 1000000, in tegra_emc_load_timings_from_dt()
419 emc->timings[emc->num_timings - 1].rate / 1000000); in tegra_emc_load_timings_from_dt()
431 if (of_get_child_count(dev->of_node) == 0) { in tegra_emc_find_node_by_ram_code()
432 dev_info_once(dev, "device-tree doesn't have memory timings\n"); in tegra_emc_find_node_by_ram_code()
436 if (!of_property_read_bool(dev->of_node, "nvidia,use-ram-code")) in tegra_emc_find_node_by_ram_code()
437 return of_node_get(dev->of_node); in tegra_emc_find_node_by_ram_code()
441 for (np = of_find_node_by_name(dev->of_node, "emc-tables"); np; in tegra_emc_find_node_by_ram_code()
442 np = of_find_node_by_name(np, "emc-tables")) { in tegra_emc_find_node_by_ram_code()
443 err = of_property_read_u32(np, "nvidia,ram-code", &value); in tegra_emc_find_node_by_ram_code()
452 dev_err(dev, "no memory timings for RAM code %u found in device tree\n", in tegra_emc_find_node_by_ram_code()
458 static int emc_setup_hw(struct tegra_emc *emc) in emc_setup_hw() argument
463 emc_cfg = readl_relaxed(emc->regs + EMC_CFG_2); in emc_setup_hw()
466 * Depending on a memory type, DRAM should enter either self-refresh in emc_setup_hw()
467 * or power-down state on EMC clock change. in emc_setup_hw()
471 dev_err(emc->dev, in emc_setup_hw()
472 "bootloader didn't specify DRAM auto-suspend mode\n"); in emc_setup_hw()
473 return -EINVAL; in emc_setup_hw()
476 /* enable EMC and CAR to handshake on PLL divider/source changes */ in emc_setup_hw()
478 writel_relaxed(emc_cfg, emc->regs + EMC_CFG_2); in emc_setup_hw()
481 writel_relaxed(intmask, emc->regs + EMC_INTMASK); in emc_setup_hw()
482 writel_relaxed(intmask, emc->regs + EMC_INTSTATUS); in emc_setup_hw()
485 emc_dbg = readl_relaxed(emc->regs + EMC_DBG); in emc_setup_hw()
490 writel_relaxed(emc_dbg, emc->regs + EMC_DBG); in emc_setup_hw()
492 emc_fbio = readl_relaxed(emc->regs + EMC_FBIO_CFG5); in emc_setup_hw()
495 emc->dram_bus_width = 16; in emc_setup_hw()
497 emc->dram_bus_width = 32; in emc_setup_hw()
499 dev_info_once(emc->dev, "%ubit DRAM bus\n", emc->dram_bus_width); in emc_setup_hw()
510 struct tegra_emc *emc = arg; in emc_round_rate() local
513 if (!emc->num_timings) in emc_round_rate()
514 return clk_get_rate(emc->clk); in emc_round_rate()
516 min_rate = min(min_rate, emc->timings[emc->num_timings - 1].rate); in emc_round_rate()
518 for (i = 0; i < emc->num_timings; i++) { in emc_round_rate()
519 if (emc->timings[i].rate < rate && i != emc->num_timings - 1) in emc_round_rate()
522 if (emc->timings[i].rate > max_rate) { in emc_round_rate()
523 i = max(i, 1u) - 1; in emc_round_rate()
525 if (emc->timings[i].rate < min_rate) in emc_round_rate()
529 if (emc->timings[i].rate < min_rate) in emc_round_rate()
532 timing = &emc->timings[i]; in emc_round_rate()
537 dev_err(emc->dev, "no timing for rate %lu min %lu max %lu\n", in emc_round_rate()
539 return -EINVAL; in emc_round_rate()
542 return timing->rate; in emc_round_rate()
545 static void tegra_emc_rate_requests_init(struct tegra_emc *emc) in tegra_emc_rate_requests_init() argument
550 emc->requested_rate[i].min_rate = 0; in tegra_emc_rate_requests_init()
551 emc->requested_rate[i].max_rate = ULONG_MAX; in tegra_emc_rate_requests_init()
555 static int emc_request_rate(struct tegra_emc *emc, in emc_request_rate() argument
560 struct emc_rate_request *req = emc->requested_rate; in emc_request_rate()
571 min_rate = max(req->min_rate, min_rate); in emc_request_rate()
572 max_rate = min(req->max_rate, max_rate); in emc_request_rate()
577 dev_err_ratelimited(emc->dev, "%s: type %u: out of range: %lu %lu\n", in emc_request_rate()
579 return -ERANGE; in emc_request_rate()
583 * EMC rate-changes should go via OPP API because it manages voltage in emc_request_rate()
586 err = dev_pm_opp_set_rate(emc->dev, min_rate); in emc_request_rate()
590 emc->requested_rate[type].min_rate = new_min_rate; in emc_request_rate()
591 emc->requested_rate[type].max_rate = new_max_rate; in emc_request_rate()
596 static int emc_set_min_rate(struct tegra_emc *emc, unsigned long rate, in emc_set_min_rate() argument
599 struct emc_rate_request *req = &emc->requested_rate[type]; in emc_set_min_rate()
602 mutex_lock(&emc->rate_lock); in emc_set_min_rate()
603 ret = emc_request_rate(emc, rate, req->max_rate, type); in emc_set_min_rate()
604 mutex_unlock(&emc->rate_lock); in emc_set_min_rate()
609 static int emc_set_max_rate(struct tegra_emc *emc, unsigned long rate, in emc_set_max_rate() argument
612 struct emc_rate_request *req = &emc->requested_rate[type]; in emc_set_max_rate()
615 mutex_lock(&emc->rate_lock); in emc_set_max_rate()
616 ret = emc_request_rate(emc, req->min_rate, rate, type); in emc_set_max_rate()
617 mutex_unlock(&emc->rate_lock); in emc_set_max_rate()
626 * to control the EMC frequency. The top-level directory can be found here:
628 * /sys/kernel/debug/emc
632 * - available_rates: This file contains a list of valid, space-separated
633 * EMC frequencies.
635 * - min_rate: Writing a value to this file sets the given frequency as the
637 * configured EMC frequency, this will cause the frequency to be
640 * - max_rate: Similarily to the min_rate file, writing a value to this file
642 * the value is lower than the currently configured EMC frequency, this
647 static bool tegra_emc_validate_rate(struct tegra_emc *emc, unsigned long rate) in tegra_emc_validate_rate() argument
651 for (i = 0; i < emc->num_timings; i++) in tegra_emc_validate_rate()
652 if (rate == emc->timings[i].rate) in tegra_emc_validate_rate()
660 struct tegra_emc *emc = s->private; in tegra_emc_debug_available_rates_show() local
664 for (i = 0; i < emc->num_timings; i++) { in tegra_emc_debug_available_rates_show()
665 seq_printf(s, "%s%lu", prefix, emc->timings[i].rate); in tegra_emc_debug_available_rates_show()
678 inode->i_private); in tegra_emc_debug_available_rates_open()
690 struct tegra_emc *emc = data; in tegra_emc_debug_min_rate_get() local
692 *rate = emc->debugfs.min_rate; in tegra_emc_debug_min_rate_get()
699 struct tegra_emc *emc = data; in tegra_emc_debug_min_rate_set() local
702 if (!tegra_emc_validate_rate(emc, rate)) in tegra_emc_debug_min_rate_set()
703 return -EINVAL; in tegra_emc_debug_min_rate_set()
705 err = emc_set_min_rate(emc, rate, EMC_RATE_DEBUG); in tegra_emc_debug_min_rate_set()
709 emc->debugfs.min_rate = rate; in tegra_emc_debug_min_rate_set()
720 struct tegra_emc *emc = data; in tegra_emc_debug_max_rate_get() local
722 *rate = emc->debugfs.max_rate; in tegra_emc_debug_max_rate_get()
729 struct tegra_emc *emc = data; in tegra_emc_debug_max_rate_set() local
732 if (!tegra_emc_validate_rate(emc, rate)) in tegra_emc_debug_max_rate_set()
733 return -EINVAL; in tegra_emc_debug_max_rate_set()
735 err = emc_set_max_rate(emc, rate, EMC_RATE_DEBUG); in tegra_emc_debug_max_rate_set()
739 emc->debugfs.max_rate = rate; in tegra_emc_debug_max_rate_set()
748 static void tegra_emc_debugfs_init(struct tegra_emc *emc) in tegra_emc_debugfs_init() argument
750 struct device *dev = emc->dev; in tegra_emc_debugfs_init()
754 emc->debugfs.min_rate = ULONG_MAX; in tegra_emc_debugfs_init()
755 emc->debugfs.max_rate = 0; in tegra_emc_debugfs_init()
757 for (i = 0; i < emc->num_timings; i++) { in tegra_emc_debugfs_init()
758 if (emc->timings[i].rate < emc->debugfs.min_rate) in tegra_emc_debugfs_init()
759 emc->debugfs.min_rate = emc->timings[i].rate; in tegra_emc_debugfs_init()
761 if (emc->timings[i].rate > emc->debugfs.max_rate) in tegra_emc_debugfs_init()
762 emc->debugfs.max_rate = emc->timings[i].rate; in tegra_emc_debugfs_init()
765 if (!emc->num_timings) { in tegra_emc_debugfs_init()
766 emc->debugfs.min_rate = clk_get_rate(emc->clk); in tegra_emc_debugfs_init()
767 emc->debugfs.max_rate = emc->debugfs.min_rate; in tegra_emc_debugfs_init()
770 err = clk_set_rate_range(emc->clk, emc->debugfs.min_rate, in tegra_emc_debugfs_init()
771 emc->debugfs.max_rate); in tegra_emc_debugfs_init()
773 dev_err(dev, "failed to set rate range [%lu-%lu] for %pC\n", in tegra_emc_debugfs_init()
774 emc->debugfs.min_rate, emc->debugfs.max_rate, in tegra_emc_debugfs_init()
775 emc->clk); in tegra_emc_debugfs_init()
778 emc->debugfs.root = debugfs_create_dir("emc", NULL); in tegra_emc_debugfs_init()
780 debugfs_create_file("available_rates", 0444, emc->debugfs.root, in tegra_emc_debugfs_init()
781 emc, &tegra_emc_debug_available_rates_fops); in tegra_emc_debugfs_init()
782 debugfs_create_file("min_rate", 0644, emc->debugfs.root, in tegra_emc_debugfs_init()
783 emc, &tegra_emc_debug_min_rate_fops); in tegra_emc_debugfs_init()
784 debugfs_create_file("max_rate", 0644, emc->debugfs.root, in tegra_emc_debugfs_init()
785 emc, &tegra_emc_debug_max_rate_fops); in tegra_emc_debugfs_init()
802 list_for_each_entry(node, &provider->nodes, node_list) { in emc_of_icc_xlate_extended()
803 if (node->id != TEGRA_ICC_EMEM) in emc_of_icc_xlate_extended()
808 return ERR_PTR(-ENOMEM); in emc_of_icc_xlate_extended()
814 ndata->tag = TEGRA_MC_ICC_TAG_ISO; in emc_of_icc_xlate_extended()
815 ndata->node = node; in emc_of_icc_xlate_extended()
820 return ERR_PTR(-EPROBE_DEFER); in emc_of_icc_xlate_extended()
825 struct tegra_emc *emc = to_tegra_emc_provider(dst->provider); in emc_icc_set() local
826 unsigned long long peak_bw = icc_units_to_bps(dst->peak_bw); in emc_icc_set()
827 unsigned long long avg_bw = icc_units_to_bps(dst->avg_bw); in emc_icc_set()
833 * Tegra20 EMC runs on x2 clock rate of SDRAM bus because DDR data in emc_icc_set()
834 * is sampled on both clock edges. This means that EMC clock rate in emc_icc_set()
835 * equals to the peak data-rate. in emc_icc_set()
837 dram_data_bus_width_bytes = emc->dram_bus_width / 8; in emc_icc_set()
841 err = emc_set_min_rate(emc, rate, EMC_RATE_ICC); in emc_icc_set()
848 static int tegra_emc_interconnect_init(struct tegra_emc *emc) in tegra_emc_interconnect_init() argument
854 emc->mc = devm_tegra_memory_controller_get(emc->dev); in tegra_emc_interconnect_init()
855 if (IS_ERR(emc->mc)) in tegra_emc_interconnect_init()
856 return PTR_ERR(emc->mc); in tegra_emc_interconnect_init()
858 soc = emc->mc->soc; in tegra_emc_interconnect_init()
860 emc->provider.dev = emc->dev; in tegra_emc_interconnect_init()
861 emc->provider.set = emc_icc_set; in tegra_emc_interconnect_init()
862 emc->provider.data = &emc->provider; in tegra_emc_interconnect_init()
863 emc->provider.aggregate = soc->icc_ops->aggregate; in tegra_emc_interconnect_init()
864 emc->provider.xlate_extended = emc_of_icc_xlate_extended; in tegra_emc_interconnect_init()
866 err = icc_provider_add(&emc->provider); in tegra_emc_interconnect_init()
877 node->name = "External Memory Controller"; in tegra_emc_interconnect_init()
878 icc_node_add(node, &emc->provider); in tegra_emc_interconnect_init()
892 node->name = "External Memory (DRAM)"; in tegra_emc_interconnect_init()
893 icc_node_add(node, &emc->provider); in tegra_emc_interconnect_init()
898 icc_nodes_remove(&emc->provider); in tegra_emc_interconnect_init()
900 icc_provider_del(&emc->provider); in tegra_emc_interconnect_init()
902 dev_err(emc->dev, "failed to initialize ICC: %d\n", err); in tegra_emc_interconnect_init()
914 struct tegra_emc *emc = data; in devm_tegra_emc_unreg_clk_notifier() local
916 clk_notifier_unregister(emc->clk, &emc->clk_nb); in devm_tegra_emc_unreg_clk_notifier()
919 static int tegra_emc_init_clk(struct tegra_emc *emc) in tegra_emc_init_clk() argument
923 tegra20_clk_set_emc_round_callback(emc_round_rate, emc); in tegra_emc_init_clk()
925 err = devm_add_action_or_reset(emc->dev, devm_tegra_emc_unset_callback, in tegra_emc_init_clk()
930 emc->clk = devm_clk_get(emc->dev, NULL); in tegra_emc_init_clk()
931 if (IS_ERR(emc->clk)) { in tegra_emc_init_clk()
932 dev_err(emc->dev, "failed to get EMC clock: %pe\n", emc->clk); in tegra_emc_init_clk()
933 return PTR_ERR(emc->clk); in tegra_emc_init_clk()
936 err = clk_notifier_register(emc->clk, &emc->clk_nb); in tegra_emc_init_clk()
938 dev_err(emc->dev, "failed to register clk notifier: %d\n", err); in tegra_emc_init_clk()
942 err = devm_add_action_or_reset(emc->dev, in tegra_emc_init_clk()
943 devm_tegra_emc_unreg_clk_notifier, emc); in tegra_emc_init_clk()
953 struct tegra_emc *emc = dev_get_drvdata(dev); in tegra_emc_devfreq_target() local
966 return emc_set_min_rate(emc, rate, EMC_RATE_DEVFREQ); in tegra_emc_devfreq_target()
972 struct tegra_emc *emc = dev_get_drvdata(dev); in tegra_emc_devfreq_get_dev_status() local
975 writel_relaxed(EMC_PWR_GATHER_DISABLE, emc->regs + EMC_STAT_CONTROL); in tegra_emc_devfreq_get_dev_status()
978 * busy_time: number of clocks EMC request was accepted in tegra_emc_devfreq_get_dev_status()
981 stat->busy_time = readl_relaxed(emc->regs + EMC_STAT_PWR_COUNT); in tegra_emc_devfreq_get_dev_status()
982 stat->total_time = readl_relaxed(emc->regs + EMC_STAT_PWR_CLOCKS); in tegra_emc_devfreq_get_dev_status()
983 stat->current_frequency = clk_get_rate(emc->clk); in tegra_emc_devfreq_get_dev_status()
986 writel_relaxed(EMC_PWR_GATHER_CLEAR, emc->regs + EMC_STAT_CONTROL); in tegra_emc_devfreq_get_dev_status()
987 writel_relaxed(EMC_PWR_GATHER_ENABLE, emc->regs + EMC_STAT_CONTROL); in tegra_emc_devfreq_get_dev_status()
998 static int tegra_emc_devfreq_init(struct tegra_emc *emc) in tegra_emc_devfreq_init() argument
1003 * PWR_COUNT is 1/2 of PWR_CLOCKS at max, and thus, the up-threshold in tegra_emc_devfreq_init()
1009 emc->ondemand_data.upthreshold = 20; in tegra_emc_devfreq_init()
1016 writel_relaxed(0x00000000, emc->regs + EMC_STAT_CONTROL); in tegra_emc_devfreq_init()
1017 writel_relaxed(0x00000000, emc->regs + EMC_STAT_LLMC_CONTROL); in tegra_emc_devfreq_init()
1018 writel_relaxed(0xffffffff, emc->regs + EMC_STAT_PWR_CLOCK_LIMIT); in tegra_emc_devfreq_init()
1020 devfreq = devm_devfreq_add_device(emc->dev, &tegra_emc_devfreq_profile, in tegra_emc_devfreq_init()
1022 &emc->ondemand_data); in tegra_emc_devfreq_init()
1024 dev_err(emc->dev, "failed to initialize devfreq: %pe", devfreq); in tegra_emc_devfreq_init()
1035 struct tegra_emc *emc; in tegra_emc_probe() local
1040 dev_err(&pdev->dev, "please update your device tree\n"); in tegra_emc_probe()
1044 emc = devm_kzalloc(&pdev->dev, sizeof(*emc), GFP_KERNEL); in tegra_emc_probe()
1045 if (!emc) in tegra_emc_probe()
1046 return -ENOMEM; in tegra_emc_probe()
1048 mutex_init(&emc->rate_lock); in tegra_emc_probe()
1049 emc->clk_nb.notifier_call = tegra_emc_clk_change_notify; in tegra_emc_probe()
1050 emc->dev = &pdev->dev; in tegra_emc_probe()
1052 np = tegra_emc_find_node_by_ram_code(&pdev->dev); in tegra_emc_probe()
1054 err = tegra_emc_load_timings_from_dt(emc, np); in tegra_emc_probe()
1060 emc->regs = devm_platform_ioremap_resource(pdev, 0); in tegra_emc_probe()
1061 if (IS_ERR(emc->regs)) in tegra_emc_probe()
1062 return PTR_ERR(emc->regs); in tegra_emc_probe()
1064 err = emc_setup_hw(emc); in tegra_emc_probe()
1068 err = devm_request_irq(&pdev->dev, irq, tegra_emc_isr, 0, in tegra_emc_probe()
1069 dev_name(&pdev->dev), emc); in tegra_emc_probe()
1071 dev_err(&pdev->dev, "failed to request IRQ: %d\n", err); in tegra_emc_probe()
1075 err = tegra_emc_init_clk(emc); in tegra_emc_probe()
1081 err = devm_tegra_core_dev_init_opp_table(&pdev->dev, &opp_params); in tegra_emc_probe()
1085 platform_set_drvdata(pdev, emc); in tegra_emc_probe()
1086 tegra_emc_rate_requests_init(emc); in tegra_emc_probe()
1087 tegra_emc_debugfs_init(emc); in tegra_emc_probe()
1088 tegra_emc_interconnect_init(emc); in tegra_emc_probe()
1089 tegra_emc_devfreq_init(emc); in tegra_emc_probe()
1102 { .compatible = "nvidia,tegra20-emc", },
1110 .name = "tegra20-emc",
1119 MODULE_DESCRIPTION("NVIDIA Tegra20 EMC driver");