5  * Interrupt architecture for the GIC:
40 #include <linux/irqchip/arm-gic.h>
48 #include "irq-gic-common.h"
113  * The GIC mapping of CPU interfaces does not necessarily match
115  * by the GIC itself.
311 		pr_warn("GIC: PPI%d is secure or misconfigured\n", gicirq - 16);  in gic_set_type()
320 	/* Only interrupts on the primary GIC can be forwarded to a vcpu. */  in gic_irq_set_vcpu_affinity()
339 	struct gic_chip_data *gic = &gic_data[0];  in gic_handle_irq()  local
340 	void __iomem *cpu_base = gic_data_cpu_base(gic);  in gic_handle_irq()
355 		 * is read after we've read the ACK register on the GIC.  in gic_handle_irq()
363 			 * The GIC encodes the source CPU in GICC_IAR,  in gic_handle_irq()
372 		handle_domain_irq(gic->domain, irqnr, regs);  in gic_handle_irq()
420 static u8 gic_get_cpumask(struct gic_chip_data *gic)  in gic_get_cpumask()  argument
422 	void __iomem *base = gic_data_dist_base(gic);  in gic_get_cpumask()
434 		pr_crit("GIC CPU mask not found - kernel will fail to boot.\n");  in gic_get_cpumask()
445 static void gic_cpu_if_up(struct gic_chip_data *gic)  in gic_cpu_if_up()  argument
447 	void __iomem *cpu_base = gic_data_cpu_base(gic);  in gic_cpu_if_up()
452 	if (gic == &gic_data[0] && static_branch_likely(&supports_deactivate_key))  in gic_cpu_if_up()
469 static void gic_dist_init(struct gic_chip_data *gic)  in gic_dist_init()  argument
473 	unsigned int gic_irqs = gic->gic_irqs;  in gic_dist_init()
474 	void __iomem *base = gic_data_dist_base(gic);  in gic_dist_init()
481 	cpumask = gic_get_cpumask(gic);  in gic_dist_init()
492 static int gic_cpu_init(struct gic_chip_data *gic)  in gic_cpu_init()  argument
494 	void __iomem *dist_base = gic_data_dist_base(gic);  in gic_cpu_init()
495 	void __iomem *base = gic_data_cpu_base(gic);  in gic_cpu_init()
500 	 * Setting up the CPU map is only relevant for the primary GIC  in gic_cpu_init()
504 	if (gic == &gic_data[0]) {  in gic_cpu_init()
506 		 * Get what the GIC says our CPU mask is.  in gic_cpu_init()
512 		cpu_mask = gic_get_cpumask(gic);  in gic_cpu_init()
527 	gic_cpu_if_up(gic);  in gic_cpu_init()
550  * Saves the GIC distributor registers during suspend or idle.  Must be called
551  * with interrupts disabled but before powering down the GIC.  After calling
552  * this function, no interrupts will be delivered by the GIC, and another
555 void gic_dist_save(struct gic_chip_data *gic)  in gic_dist_save()  argument
561 	if (WARN_ON(!gic))  in gic_dist_save()
564 	gic_irqs = gic->gic_irqs;  in gic_dist_save()
565 	dist_base = gic_data_dist_base(gic);  in gic_dist_save()
571 		gic->saved_spi_conf[i] =  in gic_dist_save()
575 		gic->saved_spi_target[i] =  in gic_dist_save()
579 		gic->saved_spi_enable[i] =  in gic_dist_save()
583 		gic->saved_spi_active[i] =  in gic_dist_save()
588  * Restores the GIC distributor registers during resume or when coming out of
590  * that occurred while the GIC was suspended is still present, it will be
592  * the GIC and need to be handled by the platform-specific wakeup source.
594 void gic_dist_restore(struct gic_chip_data *gic)  in gic_dist_restore()  argument
600 	if (WARN_ON(!gic))  in gic_dist_restore()
603 	gic_irqs = gic->gic_irqs;  in gic_dist_restore()
604 	dist_base = gic_data_dist_base(gic);  in gic_dist_restore()
612 		writel_relaxed(gic->saved_spi_conf[i],  in gic_dist_restore()
620 		writel_relaxed(gic->saved_spi_target[i],  in gic_dist_restore()
626 		writel_relaxed(gic->saved_spi_enable[i],  in gic_dist_restore()
633 		writel_relaxed(gic->saved_spi_active[i],  in gic_dist_restore()
640 void gic_cpu_save(struct gic_chip_data *gic)  in gic_cpu_save()  argument
647 	if (WARN_ON(!gic))  in gic_cpu_save()
650 	dist_base = gic_data_dist_base(gic);  in gic_cpu_save()
651 	cpu_base = gic_data_cpu_base(gic);  in gic_cpu_save()
656 	ptr = raw_cpu_ptr(gic->saved_ppi_enable);  in gic_cpu_save()
660 	ptr = raw_cpu_ptr(gic->saved_ppi_active);  in gic_cpu_save()
664 	ptr = raw_cpu_ptr(gic->saved_ppi_conf);  in gic_cpu_save()
670 void gic_cpu_restore(struct gic_chip_data *gic)  in gic_cpu_restore()  argument
677 	if (WARN_ON(!gic))  in gic_cpu_restore()
680 	dist_base = gic_data_dist_base(gic);  in gic_cpu_restore()
681 	cpu_base = gic_data_cpu_base(gic);  in gic_cpu_restore()
686 	ptr = raw_cpu_ptr(gic->saved_ppi_enable);  in gic_cpu_restore()
693 	ptr = raw_cpu_ptr(gic->saved_ppi_active);  in gic_cpu_restore()
700 	ptr = raw_cpu_ptr(gic->saved_ppi_conf);  in gic_cpu_restore()
709 	gic_cpu_if_up(gic);  in gic_cpu_restore()
742 static int gic_pm_init(struct gic_chip_data *gic)  in gic_pm_init()  argument
744 	gic->saved_ppi_enable = __alloc_percpu(DIV_ROUND_UP(32, 32) * 4,  in gic_pm_init()
746 	if (WARN_ON(!gic->saved_ppi_enable))  in gic_pm_init()
749 	gic->saved_ppi_active = __alloc_percpu(DIV_ROUND_UP(32, 32) * 4,  in gic_pm_init()
751 	if (WARN_ON(!gic->saved_ppi_active))  in gic_pm_init()
754 	gic->saved_ppi_conf = __alloc_percpu(DIV_ROUND_UP(32, 16) * 4,  in gic_pm_init()
756 	if (WARN_ON(!gic->saved_ppi_conf))  in gic_pm_init()
759 	if (gic == &gic_data[0])  in gic_pm_init()
765 	free_percpu(gic->saved_ppi_active);  in gic_pm_init()
767 	free_percpu(gic->saved_ppi_enable);  in gic_pm_init()
772 static int gic_pm_init(struct gic_chip_data *gic)  in gic_pm_init()  argument
866 				  "irqchip/arm/gic:starting",  in gic_smp_init()
901  * @cpu: the logical CPU number to get the GIC ID for.
1014 		pr_info("GIC physical location is %#lx\n", gic_dist_physaddr);  in gic_init_physaddr()
1025 	struct gic_chip_data *gic = d->host_data;  in gic_irq_domain_map()  local
1031 		irq_domain_set_info(d, irq, hw, &gic->chip, d->host_data,  in gic_irq_domain_map()
1035 		irq_domain_set_info(d, irq, hw, &gic->chip, d->host_data,  in gic_irq_domain_map()
1130 static void gic_init_chip(struct gic_chip_data *gic, struct device *dev,  in gic_init_chip()  argument
1134 	gic->chip = gic_chip;  in gic_init_chip()
1135 	gic->chip.name = name;  in gic_init_chip()
1136 	gic->chip.parent_device = dev;  in gic_init_chip()
1139 		gic->chip.irq_mask = gic_eoimode1_mask_irq;  in gic_init_chip()
1140 		gic->chip.irq_eoi = gic_eoimode1_eoi_irq;  in gic_init_chip()
1141 		gic->chip.irq_set_vcpu_affinity = gic_irq_set_vcpu_affinity;  in gic_init_chip()
1144 	if (gic == &gic_data[0]) {  in gic_init_chip()
1145 		gic->chip.irq_set_affinity = gic_set_affinity;  in gic_init_chip()
1146 		gic->chip.ipi_send_mask = gic_ipi_send_mask;  in gic_init_chip()
1150 static int gic_init_bases(struct gic_chip_data *gic,  in gic_init_bases()  argument
1155 	if (IS_ENABLED(CONFIG_GIC_NON_BANKED) && gic->percpu_offset) {  in gic_init_bases()
1156 		/* Frankein-GIC without banked registers... */  in gic_init_bases()
1159 		gic->dist_base.percpu_base = alloc_percpu(void __iomem *);  in gic_init_bases()
1160 		gic->cpu_base.percpu_base = alloc_percpu(void __iomem *);  in gic_init_bases()
1161 		if (WARN_ON(!gic->dist_base.percpu_base ||  in gic_init_bases()
1162 			    !gic->cpu_base.percpu_base)) {  in gic_init_bases()
1170 			unsigned long offset = gic->percpu_offset * core_id;  in gic_init_bases()
1171 			*per_cpu_ptr(gic->dist_base.percpu_base, cpu) =  in gic_init_bases()
1172 				gic->raw_dist_base + offset;  in gic_init_bases()
1173 			*per_cpu_ptr(gic->cpu_base.percpu_base, cpu) =  in gic_init_bases()
1174 				gic->raw_cpu_base + offset;  in gic_init_bases()
1179 		/* Normal, sane GIC... */  in gic_init_bases()
1180 		WARN(gic->percpu_offset,  in gic_init_bases()
1182 		     gic->percpu_offset);  in gic_init_bases()
1183 		gic->dist_base.common_base = gic->raw_dist_base;  in gic_init_bases()
1184 		gic->cpu_base.common_base = gic->raw_cpu_base;  in gic_init_bases()
1189 	 * The GIC only supports up to 1020 interrupt sources.  in gic_init_bases()
1191 	gic_irqs = readl_relaxed(gic_data_dist_base(gic) + GIC_DIST_CTR) & 0x1f;  in gic_init_bases()
1195 	gic->gic_irqs = gic_irqs;  in gic_init_bases()
1198 		gic->domain = irq_domain_create_linear(handle, gic_irqs,  in gic_init_bases()
1200 						       gic);  in gic_init_bases()
1204 		 * No secondary GIC support whatsoever.  in gic_init_bases()
1217 		gic->domain = irq_domain_add_legacy(NULL, gic_irqs, irq_base,  in gic_init_bases()
1218 						    16, &gic_irq_domain_ops, gic);  in gic_init_bases()
1221 	if (WARN_ON(!gic->domain)) {  in gic_init_bases()
1226 	gic_dist_init(gic);  in gic_init_bases()
1227 	ret = gic_cpu_init(gic);  in gic_init_bases()
1231 	ret = gic_pm_init(gic);  in gic_init_bases()
1238 	if (IS_ENABLED(CONFIG_GIC_NON_BANKED) && gic->percpu_offset) {  in gic_init_bases()
1239 		free_percpu(gic->dist_base.percpu_base);  in gic_init_bases()
1240 		free_percpu(gic->cpu_base.percpu_base);  in gic_init_bases()
1246 static int __init __gic_init_bases(struct gic_chip_data *gic,  in __gic_init_bases()  argument
1252 	if (WARN_ON(!gic || gic->domain))  in __gic_init_bases()
1255 	if (gic == &gic_data[0]) {  in __gic_init_bases()
1259 		 * This is only necessary for the primary GIC.  in __gic_init_bases()
1266 			pr_info("GIC: Using split EOI/Deactivate mode\n");  in __gic_init_bases()
1269 	if (static_branch_likely(&supports_deactivate_key) && gic == &gic_data[0]) {  in __gic_init_bases()
1271 		gic_init_chip(gic, NULL, name, true);  in __gic_init_bases()
1273 		name = kasprintf(GFP_KERNEL, "GIC-%d", (int)(gic-&gic_data[0]));  in __gic_init_bases()
1274 		gic_init_chip(gic, NULL, name, false);  in __gic_init_bases()
1277 	ret = gic_init_bases(gic, handle);  in __gic_init_bases()
1280 	else if (gic == &gic_data[0])  in __gic_init_bases()
1288 	struct gic_chip_data *gic;  in gic_init()  local
1296 	gic = &gic_data[0];  in gic_init()
1297 	gic->raw_dist_base = dist_base;  in gic_init()
1298 	gic->raw_cpu_base = cpu_base;  in gic_init()
1300 	__gic_init_bases(gic, NULL);  in gic_init()
1303 static void gic_teardown(struct gic_chip_data *gic)  in gic_teardown()  argument
1305 	if (WARN_ON(!gic))  in gic_teardown()
1308 	if (gic->raw_dist_base)  in gic_teardown()
1309 		iounmap(gic->raw_dist_base);  in gic_teardown()
1310 	if (gic->raw_cpu_base)  in gic_teardown()
1311 		iounmap(gic->raw_cpu_base);  in gic_teardown()
1342 			pr_warn("GIC: GICv2 detected, but range too small and irqchip.gicv2_force_probe not set\n");  in gic_check_eoimode()
1355 			pr_warn("GIC: GICv2 at %pa, but range is too small (broken DT?), assuming 8kB\n",  in gic_check_eoimode()
1372 		pr_warn("GIC: Aliased GICv2 at %pa, trying to find the canonical range over 128kB\n",  in gic_check_eoimode()
1395 		pr_warn("GIC: Adjusting CPU interface base to %pa\n",  in gic_check_eoimode()
1426 static int gic_of_setup(struct gic_chip_data *gic, struct device_node *node)  in gic_of_setup()  argument
1428 	if (!gic || !node)  in gic_of_setup()
1431 	gic->raw_dist_base = of_iomap(node, 0);  in gic_of_setup()
1432 	if (WARN(!gic->raw_dist_base, "unable to map gic dist registers\n"))  in gic_of_setup()
1435 	gic->raw_cpu_base = of_iomap(node, 1);  in gic_of_setup()
1436 	if (WARN(!gic->raw_cpu_base, "unable to map gic cpu registers\n"))  in gic_of_setup()
1439 	if (of_property_read_u32(node, "cpu-offset", &gic->percpu_offset))  in gic_of_setup()
1440 		gic->percpu_offset = 0;  in gic_of_setup()
1442 	gic_enable_of_quirks(node, gic_quirks, gic);  in gic_of_setup()
1447 	gic_teardown(gic);  in gic_of_setup()
1452 int gic_of_init_child(struct device *dev, struct gic_chip_data **gic, int irq)  in gic_of_init_child()  argument
1456 	if (!dev || !dev->of_node || !gic || !irq)  in gic_of_init_child()
1459 	*gic = devm_kzalloc(dev, sizeof(**gic), GFP_KERNEL);  in gic_of_init_child()
1460 	if (!*gic)  in gic_of_init_child()
1463 	gic_init_chip(*gic, dev, dev->of_node->name, false);  in gic_of_init_child()
1465 	ret = gic_of_setup(*gic, dev->of_node);  in gic_of_init_child()
1469 	ret = gic_init_bases(*gic, &dev->of_node->fwnode);  in gic_of_init_child()
1471 		gic_teardown(*gic);  in gic_of_init_child()
1475 	irq_set_chained_handler_and_data(irq, gic_handle_cascade_irq, *gic);  in gic_of_init_child()
1507 	struct gic_chip_data *gic;  in gic_of_init()  local
1516 	gic = &gic_data[gic_cnt];  in gic_of_init()
1518 	ret = gic_of_setup(gic, node);  in gic_of_init()
1526 	if (gic_cnt == 0 && !gic_check_eoimode(node, &gic->raw_cpu_base))  in gic_of_init()
1529 	ret = __gic_init_bases(gic, &node->fwnode);  in gic_of_init()
1531 		gic_teardown(gic);  in gic_of_init()
1551 IRQCHIP_DECLARE(gic_400, "arm,gic-400", gic_of_init);
1552 IRQCHIP_DECLARE(arm11mp_gic, "arm,arm11mp-gic", gic_of_init);
1553 IRQCHIP_DECLARE(arm1176jzf_dc_gic, "arm,arm1176jzf-devchip-gic", gic_of_init);
1554 IRQCHIP_DECLARE(cortex_a15_gic, "arm,cortex-a15-gic", gic_of_init);
1555 IRQCHIP_DECLARE(cortex_a9_gic, "arm,cortex-a9-gic", gic_of_init);
1556 IRQCHIP_DECLARE(cortex_a7_gic, "arm,cortex-a7-gic", gic_of_init);
1561 int gic_of_init_child(struct device *dev, struct gic_chip_data **gic, int irq)  in gic_of_init_child()  argument
1676 	struct gic_chip_data *gic = &gic_data[0];  in gic_v2_acpi_init()  local
1687 	gic->raw_cpu_base = ioremap(acpi_data.cpu_phys_base, ACPI_GIC_CPU_IF_MEM_SIZE);  in gic_v2_acpi_init()
1688 	if (!gic->raw_cpu_base) {  in gic_v2_acpi_init()
1694 	gic->raw_dist_base = ioremap(dist->base_address,  in gic_v2_acpi_init()
1696 	if (!gic->raw_dist_base) {  in gic_v2_acpi_init()
1698 		gic_teardown(gic);  in gic_v2_acpi_init()
1711 	 * Initialize GIC instance zero (no multi-GIC support).  in gic_v2_acpi_init()
1716 		gic_teardown(gic);  in gic_v2_acpi_init()
1720 	ret = __gic_init_bases(gic, domain_handle);  in gic_v2_acpi_init()
1722 		pr_err("Failed to initialise GIC\n");  in gic_v2_acpi_init()
1724 		gic_teardown(gic);  in gic_v2_acpi_init()