Lines Matching +full:mt8173 +full:- +full:smi +full:- +full:common
1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright (c) 2015-2016 MediaTek Inc.
11 #include <linux/dma-direct.h>
30 #include <soc/mediatek/smi.h>
123 ((((pdata)->flags) & (_x)) == (_x))
149 * |---A---|---B---|---C---|---D---|---E---|
150 * +--I/O--+------------Memory-------------+
156 * |---E---|---B---|---C---|---D---|
157 * +------------Memory-------------+
214 if (pm_runtime_get_if_in_use(data->dev) <= 0) in mtk_iommu_tlb_flush_all()
218 data->base + data->plat_data->inv_sel_reg); in mtk_iommu_tlb_flush_all()
219 writel_relaxed(F_ALL_INVLD, data->base + REG_MMU_INVALIDATE); in mtk_iommu_tlb_flush_all()
222 pm_runtime_put(data->dev); in mtk_iommu_tlb_flush_all()
230 bool has_pm = !!data->dev->pm_domain; in mtk_iommu_tlb_flush_range_sync()
237 if (pm_runtime_get_if_in_use(data->dev) <= 0) in mtk_iommu_tlb_flush_range_sync()
241 spin_lock_irqsave(&data->tlb_lock, flags); in mtk_iommu_tlb_flush_range_sync()
243 data->base + data->plat_data->inv_sel_reg); in mtk_iommu_tlb_flush_range_sync()
246 data->base + REG_MMU_INVLD_START_A); in mtk_iommu_tlb_flush_range_sync()
247 writel_relaxed(MTK_IOMMU_TLB_ADDR(iova + size - 1), in mtk_iommu_tlb_flush_range_sync()
248 data->base + REG_MMU_INVLD_END_A); in mtk_iommu_tlb_flush_range_sync()
250 data->base + REG_MMU_INVALIDATE); in mtk_iommu_tlb_flush_range_sync()
253 ret = readl_poll_timeout_atomic(data->base + REG_MMU_CPE_DONE, in mtk_iommu_tlb_flush_range_sync()
256 dev_warn(data->dev, in mtk_iommu_tlb_flush_range_sync()
261 writel_relaxed(0, data->base + REG_MMU_CPE_DONE); in mtk_iommu_tlb_flush_range_sync()
262 spin_unlock_irqrestore(&data->tlb_lock, flags); in mtk_iommu_tlb_flush_range_sync()
265 pm_runtime_put(data->dev); in mtk_iommu_tlb_flush_range_sync()
272 struct mtk_iommu_domain *dom = data->m4u_dom; in mtk_iommu_isr()
279 int_state = readl_relaxed(data->base + REG_MMU_FAULT_ST1); in mtk_iommu_isr()
281 regval = readl_relaxed(data->base + REG_MMU0_INT_ID); in mtk_iommu_isr()
282 fault_iova = readl_relaxed(data->base + REG_MMU0_FAULT_VA); in mtk_iommu_isr()
283 fault_pa = readl_relaxed(data->base + REG_MMU0_INVLD_PA); in mtk_iommu_isr()
285 regval = readl_relaxed(data->base + REG_MMU1_INT_ID); in mtk_iommu_isr()
286 fault_iova = readl_relaxed(data->base + REG_MMU1_FAULT_VA); in mtk_iommu_isr()
287 fault_pa = readl_relaxed(data->base + REG_MMU1_INVLD_PA); in mtk_iommu_isr()
291 if (MTK_IOMMU_HAS_FLAG(data->plat_data, IOVA_34_EN)) { in mtk_iommu_isr()
300 if (MTK_IOMMU_HAS_FLAG(data->plat_data, HAS_SUB_COMM)) { in mtk_iommu_isr()
306 fault_larb = data->plat_data->larbid_remap[fault_larb][sub_comm]; in mtk_iommu_isr()
308 if (report_iommu_fault(&dom->domain, data->dev, fault_iova, in mtk_iommu_isr()
311 data->dev, in mtk_iommu_isr()
318 regval = readl_relaxed(data->base + REG_MMU_INT_CONTROL0); in mtk_iommu_isr()
320 writel_relaxed(regval, data->base + REG_MMU_INT_CONTROL0); in mtk_iommu_isr()
330 const struct mtk_iommu_iova_region *rgn = plat_data->iova_region; in mtk_iommu_get_domain_id()
331 const struct bus_dma_region *dma_rgn = dev->dma_range_map; in mtk_iommu_get_domain_id()
332 int i, candidate = -1; in mtk_iommu_get_domain_id()
335 if (!dma_rgn || plat_data->iova_region_nr == 1) in mtk_iommu_get_domain_id()
338 dma_end = dma_rgn->dma_start + dma_rgn->size - 1; in mtk_iommu_get_domain_id()
339 for (i = 0; i < plat_data->iova_region_nr; i++, rgn++) { in mtk_iommu_get_domain_id()
341 if (dma_rgn->dma_start == rgn->iova_base && in mtk_iommu_get_domain_id()
342 dma_end == rgn->iova_base + rgn->size - 1) in mtk_iommu_get_domain_id()
345 if (dma_rgn->dma_start >= rgn->iova_base && in mtk_iommu_get_domain_id()
346 dma_end < rgn->iova_base + rgn->size) in mtk_iommu_get_domain_id()
353 &dma_rgn->dma_start, dma_rgn->size); in mtk_iommu_get_domain_id()
354 return -EINVAL; in mtk_iommu_get_domain_id()
366 for (i = 0; i < fwspec->num_ids; ++i) { in mtk_iommu_config()
367 larbid = MTK_M4U_TO_LARB(fwspec->ids[i]); in mtk_iommu_config()
368 portid = MTK_M4U_TO_PORT(fwspec->ids[i]); in mtk_iommu_config()
370 larb_mmu = &data->larb_imu[larbid]; in mtk_iommu_config()
372 region = data->plat_data->iova_region + domid; in mtk_iommu_config()
373 larb_mmu->bank[portid] = upper_32_bits(region->iova_base); in mtk_iommu_config()
376 enable ? "enable" : "disable", dev_name(larb_mmu->dev), in mtk_iommu_config()
377 portid, domid, larb_mmu->bank[portid]); in mtk_iommu_config()
380 larb_mmu->mmu |= MTK_SMI_MMU_EN(portid); in mtk_iommu_config()
382 larb_mmu->mmu &= ~MTK_SMI_MMU_EN(portid); in mtk_iommu_config()
393 if (data->m4u_dom) { in mtk_iommu_domain_finalise()
394 dom->iop = data->m4u_dom->iop; in mtk_iommu_domain_finalise()
395 dom->cfg = data->m4u_dom->cfg; in mtk_iommu_domain_finalise()
396 dom->domain.pgsize_bitmap = data->m4u_dom->cfg.pgsize_bitmap; in mtk_iommu_domain_finalise()
400 dom->cfg = (struct io_pgtable_cfg) { in mtk_iommu_domain_finalise()
405 .ias = MTK_IOMMU_HAS_FLAG(data->plat_data, IOVA_34_EN) ? 34 : 32, in mtk_iommu_domain_finalise()
406 .iommu_dev = data->dev, in mtk_iommu_domain_finalise()
409 if (MTK_IOMMU_HAS_FLAG(data->plat_data, HAS_4GB_MODE)) in mtk_iommu_domain_finalise()
410 dom->cfg.oas = data->enable_4GB ? 33 : 32; in mtk_iommu_domain_finalise()
412 dom->cfg.oas = 35; in mtk_iommu_domain_finalise()
414 dom->iop = alloc_io_pgtable_ops(ARM_V7S, &dom->cfg, data); in mtk_iommu_domain_finalise()
415 if (!dom->iop) { in mtk_iommu_domain_finalise()
416 dev_err(data->dev, "Failed to alloc io pgtable\n"); in mtk_iommu_domain_finalise()
417 return -EINVAL; in mtk_iommu_domain_finalise()
421 dom->domain.pgsize_bitmap = dom->cfg.pgsize_bitmap; in mtk_iommu_domain_finalise()
425 region = data->plat_data->iova_region + domid; in mtk_iommu_domain_finalise()
426 dom->domain.geometry.aperture_start = region->iova_base; in mtk_iommu_domain_finalise()
427 dom->domain.geometry.aperture_end = region->iova_base + region->size - 1; in mtk_iommu_domain_finalise()
428 dom->domain.geometry.force_aperture = true; in mtk_iommu_domain_finalise()
443 return &dom->domain; in mtk_iommu_domain_alloc()
456 struct device *m4udev = data->dev; in mtk_iommu_attach_device()
459 domid = mtk_iommu_get_domain_id(dev, data->plat_data); in mtk_iommu_attach_device()
463 if (!dom->data) { in mtk_iommu_attach_device()
465 return -ENODEV; in mtk_iommu_attach_device()
466 dom->data = data; in mtk_iommu_attach_device()
469 if (!data->m4u_dom) { /* Initialize the M4U HW */ in mtk_iommu_attach_device()
479 data->m4u_dom = dom; in mtk_iommu_attach_device()
480 writel(dom->cfg.arm_v7s_cfg.ttbr & MMU_PT_ADDR_MASK, in mtk_iommu_attach_device()
481 data->base + REG_MMU_PT_BASE_ADDR); in mtk_iommu_attach_device()
504 if (dom->data->enable_4GB) in mtk_iommu_map()
508 return dom->iop->map(dom->iop, iova, paddr, size, prot, gfp); in mtk_iommu_map()
518 return dom->iop->unmap(dom->iop, iova, size, gather); in mtk_iommu_unmap()
525 mtk_iommu_tlb_flush_all(dom->data); in mtk_iommu_flush_iotlb_all()
532 size_t length = gather->end - gather->start + 1; in mtk_iommu_iotlb_sync()
534 mtk_iommu_tlb_flush_range_sync(gather->start, length, gather->pgsize, in mtk_iommu_iotlb_sync()
535 dom->data); in mtk_iommu_iotlb_sync()
543 mtk_iommu_tlb_flush_range_sync(iova, size, size, dom->data); in mtk_iommu_sync_map()
552 pa = dom->iop->iova_to_phys(dom->iop, iova); in mtk_iommu_iova_to_phys()
553 if (dom->data->enable_4GB && pa >= MTK_IOMMU_4GB_MODE_REMAP_BASE) in mtk_iommu_iova_to_phys()
564 if (!fwspec || fwspec->ops != &mtk_iommu_ops) in mtk_iommu_probe_device()
565 return ERR_PTR(-ENODEV); /* Not a iommu client device */ in mtk_iommu_probe_device()
569 return &data->iommu; in mtk_iommu_probe_device()
576 if (!fwspec || fwspec->ops != &mtk_iommu_ops) in mtk_iommu_release_device()
589 return ERR_PTR(-ENODEV); in mtk_iommu_device_group()
591 domid = mtk_iommu_get_domain_id(dev, data->plat_data); in mtk_iommu_device_group()
595 group = data->m4u_group[domid]; in mtk_iommu_device_group()
599 data->m4u_group[domid] = group; in mtk_iommu_device_group()
610 if (args->args_count != 1) { in mtk_iommu_of_xlate()
611 dev_err(dev, "invalid #iommu-cells(%d) property for IOMMU\n", in mtk_iommu_of_xlate()
612 args->args_count); in mtk_iommu_of_xlate()
613 return -EINVAL; in mtk_iommu_of_xlate()
618 m4updev = of_find_device_by_node(args->np); in mtk_iommu_of_xlate()
620 return -EINVAL; in mtk_iommu_of_xlate()
625 return iommu_fwspec_add_ids(dev, args->args, 1); in mtk_iommu_of_xlate()
632 unsigned int domid = mtk_iommu_get_domain_id(dev, data->plat_data), i; in mtk_iommu_get_resv_regions()
639 curdom = data->plat_data->iova_region + domid; in mtk_iommu_get_resv_regions()
640 for (i = 0; i < data->plat_data->iova_region_nr; i++) { in mtk_iommu_get_resv_regions()
641 resv = data->plat_data->iova_region + i; in mtk_iommu_get_resv_regions()
644 if (resv->iova_base <= curdom->iova_base || in mtk_iommu_get_resv_regions()
645 resv->iova_base + resv->size >= curdom->iova_base + curdom->size) in mtk_iommu_get_resv_regions()
648 region = iommu_alloc_resv_region(resv->iova_base, resv->size, in mtk_iommu_get_resv_regions()
653 list_add_tail(®ion->list, head); in mtk_iommu_get_resv_regions()
682 if (data->plat_data->m4u_plat == M4U_MT8173) { in mtk_iommu_hw_init()
686 regval = readl_relaxed(data->base + REG_MMU_CTRL_REG); in mtk_iommu_hw_init()
689 writel_relaxed(regval, data->base + REG_MMU_CTRL_REG); in mtk_iommu_hw_init()
697 writel_relaxed(regval, data->base + REG_MMU_INT_CONTROL0); in mtk_iommu_hw_init()
706 writel_relaxed(regval, data->base + REG_MMU_INT_MAIN_CONTROL); in mtk_iommu_hw_init()
708 if (MTK_IOMMU_HAS_FLAG(data->plat_data, HAS_LEGACY_IVRP_PADDR)) in mtk_iommu_hw_init()
709 regval = (data->protect_base >> 1) | (data->enable_4GB << 31); in mtk_iommu_hw_init()
711 regval = lower_32_bits(data->protect_base) | in mtk_iommu_hw_init()
712 upper_32_bits(data->protect_base); in mtk_iommu_hw_init()
713 writel_relaxed(regval, data->base + REG_MMU_IVRP_PADDR); in mtk_iommu_hw_init()
715 if (data->enable_4GB && in mtk_iommu_hw_init()
716 MTK_IOMMU_HAS_FLAG(data->plat_data, HAS_VLD_PA_RNG)) { in mtk_iommu_hw_init()
722 writel_relaxed(regval, data->base + REG_MMU_VLD_PA_RNG); in mtk_iommu_hw_init()
724 writel_relaxed(0, data->base + REG_MMU_DCM_DIS); in mtk_iommu_hw_init()
725 if (MTK_IOMMU_HAS_FLAG(data->plat_data, WR_THROT_EN)) { in mtk_iommu_hw_init()
727 regval = readl_relaxed(data->base + REG_MMU_WR_LEN_CTRL); in mtk_iommu_hw_init()
729 writel_relaxed(regval, data->base + REG_MMU_WR_LEN_CTRL); in mtk_iommu_hw_init()
732 if (MTK_IOMMU_HAS_FLAG(data->plat_data, RESET_AXI)) { in mtk_iommu_hw_init()
736 regval = readl_relaxed(data->base + REG_MMU_MISC_CTRL); in mtk_iommu_hw_init()
738 if (MTK_IOMMU_HAS_FLAG(data->plat_data, OUT_ORDER_WR_EN)) in mtk_iommu_hw_init()
741 writel_relaxed(regval, data->base + REG_MMU_MISC_CTRL); in mtk_iommu_hw_init()
743 if (devm_request_irq(data->dev, data->irq, mtk_iommu_isr, 0, in mtk_iommu_hw_init()
744 dev_name(data->dev), (void *)data)) { in mtk_iommu_hw_init()
745 writel_relaxed(0, data->base + REG_MMU_PT_BASE_ADDR); in mtk_iommu_hw_init()
746 dev_err(data->dev, "Failed @ IRQ-%d Request\n", data->irq); in mtk_iommu_hw_init()
747 return -ENODEV; in mtk_iommu_hw_init()
761 struct device *dev = &pdev->dev; in mtk_iommu_probe()
776 return -ENOMEM; in mtk_iommu_probe()
777 data->dev = dev; in mtk_iommu_probe()
778 data->plat_data = of_device_get_match_data(dev); in mtk_iommu_probe()
783 return -ENOMEM; in mtk_iommu_probe()
784 data->protect_base = ALIGN(virt_to_phys(protect), MTK_PROTECT_PA_ALIGN); in mtk_iommu_probe()
786 if (MTK_IOMMU_HAS_FLAG(data->plat_data, HAS_4GB_MODE)) { in mtk_iommu_probe()
787 switch (data->plat_data->m4u_plat) { in mtk_iommu_probe()
789 p = "mediatek,mt2712-infracfg"; in mtk_iommu_probe()
792 p = "mediatek,mt8173-infracfg"; in mtk_iommu_probe()
806 data->enable_4GB = !!(val & F_DDR_4GB_SUPPORT_EN); in mtk_iommu_probe()
810 data->base = devm_ioremap_resource(dev, res); in mtk_iommu_probe()
811 if (IS_ERR(data->base)) in mtk_iommu_probe()
812 return PTR_ERR(data->base); in mtk_iommu_probe()
813 ioaddr = res->start; in mtk_iommu_probe()
815 data->irq = platform_get_irq(pdev, 0); in mtk_iommu_probe()
816 if (data->irq < 0) in mtk_iommu_probe()
817 return data->irq; in mtk_iommu_probe()
819 if (MTK_IOMMU_HAS_FLAG(data->plat_data, HAS_BCLK)) { in mtk_iommu_probe()
820 data->bclk = devm_clk_get(dev, "bclk"); in mtk_iommu_probe()
821 if (IS_ERR(data->bclk)) in mtk_iommu_probe()
822 return PTR_ERR(data->bclk); in mtk_iommu_probe()
825 larb_nr = of_count_phandle_with_args(dev->of_node, in mtk_iommu_probe()
833 larbnode = of_parse_phandle(dev->of_node, "mediatek,larbs", i); in mtk_iommu_probe()
835 return -EINVAL; in mtk_iommu_probe()
842 ret = of_property_read_u32(larbnode, "mediatek,larb-id", &id); in mtk_iommu_probe()
849 return -EPROBE_DEFER; in mtk_iommu_probe()
851 data->larb_imu[id].dev = &plarbdev->dev; in mtk_iommu_probe()
857 /* Get smi-common dev from the last larb. */ in mtk_iommu_probe()
858 smicomm_node = of_parse_phandle(larbnode, "mediatek,smi", 0); in mtk_iommu_probe()
860 return -EINVAL; in mtk_iommu_probe()
864 data->smicomm_dev = &plarbdev->dev; in mtk_iommu_probe()
868 link = device_link_add(data->smicomm_dev, dev, in mtk_iommu_probe()
871 dev_err(dev, "Unable to link %s.\n", dev_name(data->smicomm_dev)); in mtk_iommu_probe()
872 ret = -EINVAL; in mtk_iommu_probe()
878 ret = iommu_device_sysfs_add(&data->iommu, dev, NULL, in mtk_iommu_probe()
879 "mtk-iommu.%pa", &ioaddr); in mtk_iommu_probe()
883 ret = iommu_device_register(&data->iommu, &mtk_iommu_ops, dev); in mtk_iommu_probe()
887 spin_lock_init(&data->tlb_lock); in mtk_iommu_probe()
888 list_add_tail(&data->list, &m4ulist); in mtk_iommu_probe()
904 list_del(&data->list); in mtk_iommu_probe()
905 iommu_device_unregister(&data->iommu); in mtk_iommu_probe()
907 iommu_device_sysfs_remove(&data->iommu); in mtk_iommu_probe()
909 device_link_remove(data->smicomm_dev, dev); in mtk_iommu_probe()
919 iommu_device_sysfs_remove(&data->iommu); in mtk_iommu_remove()
920 iommu_device_unregister(&data->iommu); in mtk_iommu_remove()
925 clk_disable_unprepare(data->bclk); in mtk_iommu_remove()
926 device_link_remove(data->smicomm_dev, &pdev->dev); in mtk_iommu_remove()
927 pm_runtime_disable(&pdev->dev); in mtk_iommu_remove()
928 devm_free_irq(&pdev->dev, data->irq, data); in mtk_iommu_remove()
929 component_master_del(&pdev->dev, &mtk_iommu_com_ops); in mtk_iommu_remove()
936 struct mtk_iommu_suspend_reg *reg = &data->reg; in mtk_iommu_runtime_suspend()
937 void __iomem *base = data->base; in mtk_iommu_runtime_suspend()
939 reg->wr_len_ctrl = readl_relaxed(base + REG_MMU_WR_LEN_CTRL); in mtk_iommu_runtime_suspend()
940 reg->misc_ctrl = readl_relaxed(base + REG_MMU_MISC_CTRL); in mtk_iommu_runtime_suspend()
941 reg->dcm_dis = readl_relaxed(base + REG_MMU_DCM_DIS); in mtk_iommu_runtime_suspend()
942 reg->ctrl_reg = readl_relaxed(base + REG_MMU_CTRL_REG); in mtk_iommu_runtime_suspend()
943 reg->int_control0 = readl_relaxed(base + REG_MMU_INT_CONTROL0); in mtk_iommu_runtime_suspend()
944 reg->int_main_control = readl_relaxed(base + REG_MMU_INT_MAIN_CONTROL); in mtk_iommu_runtime_suspend()
945 reg->ivrp_paddr = readl_relaxed(base + REG_MMU_IVRP_PADDR); in mtk_iommu_runtime_suspend()
946 reg->vld_pa_rng = readl_relaxed(base + REG_MMU_VLD_PA_RNG); in mtk_iommu_runtime_suspend()
947 clk_disable_unprepare(data->bclk); in mtk_iommu_runtime_suspend()
954 struct mtk_iommu_suspend_reg *reg = &data->reg; in mtk_iommu_runtime_resume()
955 struct mtk_iommu_domain *m4u_dom = data->m4u_dom; in mtk_iommu_runtime_resume()
956 void __iomem *base = data->base; in mtk_iommu_runtime_resume()
959 ret = clk_prepare_enable(data->bclk); in mtk_iommu_runtime_resume()
961 dev_err(data->dev, "Failed to enable clk(%d) in resume\n", ret); in mtk_iommu_runtime_resume()
972 writel_relaxed(reg->wr_len_ctrl, base + REG_MMU_WR_LEN_CTRL); in mtk_iommu_runtime_resume()
973 writel_relaxed(reg->misc_ctrl, base + REG_MMU_MISC_CTRL); in mtk_iommu_runtime_resume()
974 writel_relaxed(reg->dcm_dis, base + REG_MMU_DCM_DIS); in mtk_iommu_runtime_resume()
975 writel_relaxed(reg->ctrl_reg, base + REG_MMU_CTRL_REG); in mtk_iommu_runtime_resume()
976 writel_relaxed(reg->int_control0, base + REG_MMU_INT_CONTROL0); in mtk_iommu_runtime_resume()
977 writel_relaxed(reg->int_main_control, base + REG_MMU_INT_MAIN_CONTROL); in mtk_iommu_runtime_resume()
978 writel_relaxed(reg->ivrp_paddr, base + REG_MMU_IVRP_PADDR); in mtk_iommu_runtime_resume()
979 writel_relaxed(reg->vld_pa_rng, base + REG_MMU_VLD_PA_RNG); in mtk_iommu_runtime_resume()
980 writel(m4u_dom->cfg.arm_v7s_cfg.ttbr & MMU_PT_ADDR_MASK, base + REG_MMU_PT_BASE_ADDR); in mtk_iommu_runtime_resume()
1048 { .compatible = "mediatek,mt2712-m4u", .data = &mt2712_data},
1049 { .compatible = "mediatek,mt6779-m4u", .data = &mt6779_data},
1050 { .compatible = "mediatek,mt8167-m4u", .data = &mt8167_data},
1051 { .compatible = "mediatek,mt8173-m4u", .data = &mt8173_data},
1052 { .compatible = "mediatek,mt8183-m4u", .data = &mt8183_data},
1053 { .compatible = "mediatek,mt8192-m4u", .data = &mt8192_data},
1061 .name = "mtk-iommu",