Lines Matching +full:fifo +full:- +full:watermark +full:- +full:aligned
1 // SPDX-License-Identifier: GPL-2.0-only
12 #include <linux/dma-mapping.h>
98 /* Interrupt Enable Register - TS X measurement ready */
100 /* Interrupt Enable Register - TS Y measurement ready */
102 /* Interrupt Enable Register - TS pressure measurement ready */
104 /* Interrupt Enable Register - Data ready */
106 /* Interrupt Enable Register - general overrun error */
108 /* Interrupt Enable Register - Pen detect */
110 /* Interrupt Enable Register - No pen detect */
118 /* Interrupt Status Register - Pen touching sense status */
128 /* Extended Mode Register - Oversampling rate */
135 /* Extended Mode Register - Averaging on single trigger event */
150 /* Analog Control Register - Pen detect sensitivity mask */
155 /* Touchscreen Mode Register - No touch mode */
157 /* Touchscreen Mode Register - 4 wire screen, no pressure measurement */
159 /* Touchscreen Mode Register - 4 wire screen, pressure measurement */
161 /* Touchscreen Mode Register - 5 wire screen */
163 /* Touchscreen Mode Register - Average samples mask */
165 /* Touchscreen Mode Register - Average samples */
167 /* Touchscreen Mode Register - Touch/trigger frequency ratio mask */
169 /* Touchscreen Mode Register - Touch/trigger frequency ratio */
171 /* Touchscreen Mode Register - Pen Debounce Time mask */
173 /* Touchscreen Mode Register - Pen Debounce Time */
175 /* Touchscreen Mode Register - No DMA for touch measurements */
177 /* Touchscreen Mode Register - Disable pen detection */
179 /* Touchscreen Mode Register - Enable pen detection */
202 /* Trigger Mode - trigger period mask */
204 /* Trigger Mode - trigger period */
296 .datasheet_name = "CH"#num"-CH"#num2, \
333 #define at91_adc_readl(st, reg) readl_relaxed(st->base + reg)
334 #define at91_adc_writel(st, reg, val) writel_relaxed(val, st->base + reg)
350 * struct at91_adc_dma - at91-sama5d2 dma information struct
357 * @watermark: number of conversions to copy before DMA triggers irq
367 int watermark; member
372 * struct at91_adc_touch - at91-sama5d2 touchscreen information struct
406 /* Ensure naturally aligned timestamp */
471 for (i = 0; i < indio_dev->num_channels; i++) { in at91_adc_chan_xlate()
472 if (indio_dev->channels[i].scan_index == chan) in at91_adc_chan_xlate()
475 return -EINVAL; in at91_adc_chan_xlate()
485 return indio_dev->channels + index; in at91_adc_chan_get()
491 return at91_adc_chan_xlate(indio_dev, iiospec->args[0]); in at91_adc_of_xlate()
499 for_each_set_bit(bit, indio_dev->active_scan_mask, in at91_adc_active_scan_mask_to_reg()
500 indio_dev->num_channels) { in at91_adc_active_scan_mask_to_reg()
503 mask |= BIT(chan->channel); in at91_adc_active_scan_mask_to_reg()
521 switch (st->oversampling_ratio) { in at91_adc_config_emr()
541 if (st->oversampling_ratio == AT91_OSR_1SAMPLES) { in at91_adc_adjust_val_osr()
547 } else if (st->oversampling_ratio == AT91_OSR_4SAMPLES) { in at91_adc_adjust_val_osr()
582 u32 clk_khz = st->current_sample_rate / 1000; in at91_adc_configure_touch()
625 st->touch_st.sample_period_val = in at91_adc_configure_touch()
627 clk_khz / 1000) - 1, 1); in at91_adc_configure_touch()
642 * max = 2^AT91_SAMA5D2_MAX_POS_BITS - 1 in at91_adc_touch_pos()
647 dev_dbg(&st->indio_dev->dev, "pos is 0\n"); in at91_adc_touch_pos()
650 result = (pos << AT91_SAMA5D2_MAX_POS_BITS) - pos; in at91_adc_touch_pos()
653 dev_err(&st->indio_dev->dev, "scale is 0\n"); in at91_adc_touch_pos()
663 st->touch_st.x_pos = at91_adc_touch_pos(st, AT91_SAMA5D2_XPOSR); in at91_adc_touch_x_pos()
664 return st->touch_st.x_pos; in at91_adc_touch_x_pos()
686 pres = rxp * (st->touch_st.x_pos * factor / 1024) * in at91_adc_touch_pressure()
687 (z2 * factor / z1 - factor) / in at91_adc_touch_pressure()
697 return 0xFFFF - pres; in at91_adc_touch_pressure()
703 if (!st->touch_st.touching) in at91_adc_read_position()
704 return -ENODATA; in at91_adc_read_position()
710 return -ENODATA; in at91_adc_read_position()
718 if (!st->touch_st.touching) in at91_adc_read_pressure()
719 return -ENODATA; in at91_adc_read_pressure()
723 return -ENODATA; in at91_adc_read_pressure()
738 status |= st->selected_trig->trgmod_value; in at91_adc_configure_trigger()
752 if (st->dma_st.dma_chan) in at91_adc_reenable_trigger()
755 enable_irq(st->irq); in at91_adc_reenable_trigger()
773 status = dmaengine_tx_status(st->dma_st.dma_chan, in at91_adc_dma_size_done()
774 st->dma_st.dma_chan->cookie, in at91_adc_dma_size_done()
780 i = st->dma_st.rx_buf_sz - state.residue; in at91_adc_dma_size_done()
783 if (i >= st->dma_st.buf_idx) in at91_adc_dma_size_done()
784 size = i - st->dma_st.buf_idx; in at91_adc_dma_size_done()
786 size = st->dma_st.rx_buf_sz + i - st->dma_st.buf_idx; in at91_adc_dma_size_done()
794 iio_trigger_poll_chained(indio_dev->trig); in at91_dma_buffer_done()
805 if (!st->dma_st.dma_chan) in at91_adc_dma_start()
809 st->dma_st.buf_idx = 0; in at91_adc_dma_start()
812 * compute buffer size w.r.t. watermark and enabled channels. in at91_adc_dma_start()
813 * scan_bytes is aligned so we need an exact size for DMA in at91_adc_dma_start()
815 st->dma_st.rx_buf_sz = 0; in at91_adc_dma_start()
817 for_each_set_bit(bit, indio_dev->active_scan_mask, in at91_adc_dma_start()
818 indio_dev->num_channels) { in at91_adc_dma_start()
825 st->dma_st.rx_buf_sz += chan->scan_type.storagebits / 8; in at91_adc_dma_start()
827 st->dma_st.rx_buf_sz *= st->dma_st.watermark; in at91_adc_dma_start()
830 desc = dmaengine_prep_dma_cyclic(st->dma_st.dma_chan, in at91_adc_dma_start()
831 st->dma_st.rx_dma_buf, in at91_adc_dma_start()
832 st->dma_st.rx_buf_sz, in at91_adc_dma_start()
833 st->dma_st.rx_buf_sz / 2, in at91_adc_dma_start()
837 dev_err(&indio_dev->dev, "cannot prepare DMA cyclic\n"); in at91_adc_dma_start()
838 return -EBUSY; in at91_adc_dma_start()
841 desc->callback = at91_dma_buffer_done; in at91_adc_dma_start()
842 desc->callback_param = indio_dev; in at91_adc_dma_start()
847 dev_err(&indio_dev->dev, "cannot submit DMA cyclic\n"); in at91_adc_dma_start()
848 dmaengine_terminate_async(st->dma_st.dma_chan); in at91_adc_dma_start()
855 dma_async_issue_pending(st->dma_st.dma_chan); in at91_adc_dma_start()
858 st->dma_st.dma_ts = iio_get_time_ns(indio_dev); in at91_adc_dma_start()
860 dev_dbg(&indio_dev->dev, "DMA cyclic started\n"); in at91_adc_dma_start()
868 /* if using DMA, we do not use our own IRQ (we use DMA-controller) */ in at91_adc_buffer_check_use_irq()
869 if (st->dma_st.dma_chan) in at91_adc_buffer_check_use_irq()
872 if (iio_trigger_validate_own_device(indio->trig, indio)) in at91_adc_buffer_check_use_irq()
881 return !!bitmap_subset(indio_dev->active_scan_mask, in at91_adc_current_chan_is_touch()
882 &st->touch_st.channels_bitmask, in at91_adc_current_chan_is_touch()
897 if (!(indio_dev->currentmode & INDIO_ALL_TRIGGERED_MODES)) in at91_adc_buffer_prepare()
898 return -EINVAL; in at91_adc_buffer_prepare()
903 dev_err(&indio_dev->dev, "buffer prepare failed\n"); in at91_adc_buffer_prepare()
907 for_each_set_bit(bit, indio_dev->active_scan_mask, in at91_adc_buffer_prepare()
908 indio_dev->num_channels) { in at91_adc_buffer_prepare()
916 if (chan->type == IIO_POSITIONRELATIVE || in at91_adc_buffer_prepare()
917 chan->type == IIO_PRESSURE) in at91_adc_buffer_prepare()
922 if (chan->differential) in at91_adc_buffer_prepare()
923 cor |= (BIT(chan->channel) | BIT(chan->channel2)) << in at91_adc_buffer_prepare()
926 cor &= ~(BIT(chan->channel) << in at91_adc_buffer_prepare()
931 at91_adc_writel(st, AT91_SAMA5D2_CHER, BIT(chan->channel)); in at91_adc_buffer_prepare()
950 if (!(indio_dev->currentmode & INDIO_ALL_TRIGGERED_MODES)) in at91_adc_buffer_postdisable()
951 return -EINVAL; in at91_adc_buffer_postdisable()
959 for_each_set_bit(bit, indio_dev->active_scan_mask, in at91_adc_buffer_postdisable()
960 indio_dev->num_channels) { in at91_adc_buffer_postdisable()
967 if (chan->type == IIO_POSITIONRELATIVE || in at91_adc_buffer_postdisable()
968 chan->type == IIO_PRESSURE) in at91_adc_buffer_postdisable()
971 at91_adc_writel(st, AT91_SAMA5D2_CHDR, BIT(chan->channel)); in at91_adc_buffer_postdisable()
973 if (st->dma_st.dma_chan) in at91_adc_buffer_postdisable()
974 at91_adc_readl(st, chan->address); in at91_adc_buffer_postdisable()
984 if (st->dma_st.dma_chan) in at91_adc_buffer_postdisable()
985 dmaengine_terminate_sync(st->dma_st.dma_chan); in at91_adc_buffer_postdisable()
1000 trig = devm_iio_trigger_alloc(&indio->dev, "%s-dev%d-%s", indio->name, in at91_adc_allocate_trigger()
1005 trig->dev.parent = indio->dev.parent; in at91_adc_allocate_trigger()
1007 trig->ops = &at91_adc_trigger_ops; in at91_adc_allocate_trigger()
1009 ret = devm_iio_trigger_register(&indio->dev, trig); in at91_adc_allocate_trigger()
1032 timeout--; in at91_adc_trigger_handler_nodma()
1039 for_each_set_bit(bit, indio_dev->active_scan_mask, in at91_adc_trigger_handler_nodma()
1040 indio_dev->num_channels) { in at91_adc_trigger_handler_nodma()
1056 if (chan->type == IIO_VOLTAGE) { in at91_adc_trigger_handler_nodma()
1057 val = at91_adc_readl(st, chan->address); in at91_adc_trigger_handler_nodma()
1059 st->buffer[i] = val; in at91_adc_trigger_handler_nodma()
1061 st->buffer[i] = 0; in at91_adc_trigger_handler_nodma()
1066 iio_push_to_buffers_with_timestamp(indio_dev, st->buffer, in at91_adc_trigger_handler_nodma()
1067 pf->timestamp); in at91_adc_trigger_handler_nodma()
1082 indio_dev->name); in at91_adc_trigger_handler_dma()
1084 sample_size = div_s64(st->dma_st.rx_buf_sz, st->dma_st.watermark); in at91_adc_trigger_handler_dma()
1092 interval = div_s64((ns - st->dma_st.dma_ts), sample_count); in at91_adc_trigger_handler_dma()
1100 &st->dma_st.rx_buf[st->dma_st.buf_idx], in at91_adc_trigger_handler_dma()
1104 (st->dma_st.rx_buf + st->dma_st.buf_idx), in at91_adc_trigger_handler_dma()
1105 (st->dma_st.dma_ts + interval * sample_index)); in at91_adc_trigger_handler_dma()
1107 transferred_len -= sample_size; in at91_adc_trigger_handler_dma()
1109 st->dma_st.buf_idx += sample_size; in at91_adc_trigger_handler_dma()
1111 if (st->dma_st.buf_idx >= st->dma_st.rx_buf_sz) in at91_adc_trigger_handler_dma()
1112 st->dma_st.buf_idx = 0; in at91_adc_trigger_handler_dma()
1116 st->dma_st.dma_ts = iio_get_time_ns(indio_dev); in at91_adc_trigger_handler_dma()
1122 struct iio_dev *indio_dev = pf->indio_dev; in at91_adc_trigger_handler()
1129 if (iio_trigger_validate_own_device(indio_dev->trig, indio_dev)) in at91_adc_trigger_handler()
1132 if (st->dma_st.dma_chan) in at91_adc_trigger_handler()
1137 iio_trigger_notify_done(indio_dev->trig); in at91_adc_trigger_handler()
1171 f_per = clk_get_rate(st->per_clk); in at91_adc_setup_samp_freq()
1172 prescal = (f_per / (2 * freq)) - 1; in at91_adc_setup_samp_freq()
1174 startup = at91_adc_startup_time(st->soc_info.startup_time, in at91_adc_setup_samp_freq()
1183 dev_dbg(&indio_dev->dev, "freq: %u, startup: %u, prescal: %u\n", in at91_adc_setup_samp_freq()
1185 st->current_sample_rate = freq; in at91_adc_setup_samp_freq()
1190 return st->current_sample_rate; in at91_adc_get_sample_freq()
1200 for_each_set_bit(bit, indio_dev->active_scan_mask, in at91_adc_touch_data_handler()
1205 if (chan->type == IIO_POSITIONRELATIVE) in at91_adc_touch_data_handler()
1206 at91_adc_read_position(st, chan->channel, &val); in at91_adc_touch_data_handler()
1207 else if (chan->type == IIO_PRESSURE) in at91_adc_touch_data_handler()
1208 at91_adc_read_pressure(st, chan->channel, &val); in at91_adc_touch_data_handler()
1211 st->buffer[i] = val; in at91_adc_touch_data_handler()
1222 schedule_work(&st->touch_st.workq); in at91_adc_touch_data_handler()
1233 AT91_SAMA5D2_TRGR_TRGPER(st->touch_st.sample_period_val)); in at91_adc_pen_detect_interrupt()
1234 st->touch_st.touching = true; in at91_adc_pen_detect_interrupt()
1246 st->touch_st.touching = false; in at91_adc_no_pen_detect_interrupt()
1259 struct iio_dev *indio_dev = st->indio_dev; in at91_adc_workq_handler()
1261 iio_push_to_buffers(indio_dev, st->buffer); in at91_adc_workq_handler()
1283 /* periodic trigger IRQ - during pen sense */ in at91_adc_interrupt()
1297 iio_trigger_poll(indio->trig); in at91_adc_interrupt()
1298 } else if (iio_buffer_enabled(indio) && st->dma_st.dma_chan) { in at91_adc_interrupt()
1299 /* triggered buffer with DMA - should not happen */ in at91_adc_interrupt()
1304 st->conversion_value = at91_adc_readl(st, st->chan->address); in at91_adc_interrupt()
1305 st->conversion_done = true; in at91_adc_interrupt()
1306 wake_up_interruptible(&st->wq_data_available); in at91_adc_interrupt()
1323 if (chan->type == IIO_POSITIONRELATIVE) { in at91_adc_read_info_raw()
1327 mutex_lock(&st->lock); in at91_adc_read_info_raw()
1329 ret = at91_adc_read_position(st, chan->channel, in at91_adc_read_info_raw()
1332 mutex_unlock(&st->lock); in at91_adc_read_info_raw()
1337 if (chan->type == IIO_PRESSURE) { in at91_adc_read_info_raw()
1341 mutex_lock(&st->lock); in at91_adc_read_info_raw()
1343 ret = at91_adc_read_pressure(st, chan->channel, in at91_adc_read_info_raw()
1346 mutex_unlock(&st->lock); in at91_adc_read_info_raw()
1357 mutex_lock(&st->lock); in at91_adc_read_info_raw()
1359 st->chan = chan; in at91_adc_read_info_raw()
1361 if (chan->differential) in at91_adc_read_info_raw()
1362 cor = (BIT(chan->channel) | BIT(chan->channel2)) << in at91_adc_read_info_raw()
1366 at91_adc_writel(st, AT91_SAMA5D2_CHER, BIT(chan->channel)); in at91_adc_read_info_raw()
1367 at91_adc_writel(st, AT91_SAMA5D2_IER, BIT(chan->channel)); in at91_adc_read_info_raw()
1370 ret = wait_event_interruptible_timeout(st->wq_data_available, in at91_adc_read_info_raw()
1371 st->conversion_done, in at91_adc_read_info_raw()
1374 ret = -ETIMEDOUT; in at91_adc_read_info_raw()
1377 *val = st->conversion_value; in at91_adc_read_info_raw()
1379 if (chan->scan_type.sign == 's') in at91_adc_read_info_raw()
1381 st->conversion_done = false; in at91_adc_read_info_raw()
1384 at91_adc_writel(st, AT91_SAMA5D2_IDR, BIT(chan->channel)); in at91_adc_read_info_raw()
1385 at91_adc_writel(st, AT91_SAMA5D2_CHDR, BIT(chan->channel)); in at91_adc_read_info_raw()
1390 mutex_unlock(&st->lock); in at91_adc_read_info_raw()
1406 *val = st->vref_uv / 1000; in at91_adc_read_raw()
1407 if (chan->differential) in at91_adc_read_raw()
1409 *val2 = chan->scan_type.realbits; in at91_adc_read_raw()
1417 *val = st->oversampling_ratio; in at91_adc_read_raw()
1421 return -EINVAL; in at91_adc_read_raw()
1435 return -EINVAL; in at91_adc_write_raw()
1437 if (val == st->oversampling_ratio) in at91_adc_write_raw()
1439 st->oversampling_ratio = val; in at91_adc_write_raw()
1444 if (val < st->soc_info.min_sample_rate || in at91_adc_write_raw()
1445 val > st->soc_info.max_sample_rate) in at91_adc_write_raw()
1446 return -EINVAL; in at91_adc_write_raw()
1451 return -EINVAL; in at91_adc_write_raw()
1461 * We make the buffer double the size of the fifo, in at91_adc_dma_init()
1462 * such that DMA uses one half of the buffer (full fifo size) in at91_adc_dma_init()
1469 if (st->dma_st.dma_chan) in at91_adc_dma_init()
1472 st->dma_st.dma_chan = dma_request_chan(&pdev->dev, "rx"); in at91_adc_dma_init()
1473 if (IS_ERR(st->dma_st.dma_chan)) { in at91_adc_dma_init()
1474 dev_info(&pdev->dev, "can't get DMA channel\n"); in at91_adc_dma_init()
1475 st->dma_st.dma_chan = NULL; in at91_adc_dma_init()
1479 st->dma_st.rx_buf = dma_alloc_coherent(st->dma_st.dma_chan->device->dev, in at91_adc_dma_init()
1481 &st->dma_st.rx_dma_buf, in at91_adc_dma_init()
1483 if (!st->dma_st.rx_buf) { in at91_adc_dma_init()
1484 dev_info(&pdev->dev, "can't allocate coherent DMA area\n"); in at91_adc_dma_init()
1490 config.src_addr = (phys_addr_t)(st->dma_st.phys_addr in at91_adc_dma_init()
1496 if (dmaengine_slave_config(st->dma_st.dma_chan, &config)) { in at91_adc_dma_init()
1497 dev_info(&pdev->dev, "can't configure DMA slave\n"); in at91_adc_dma_init()
1501 dev_info(&pdev->dev, "using %s for rx DMA transfers\n", in at91_adc_dma_init()
1502 dma_chan_name(st->dma_st.dma_chan)); in at91_adc_dma_init()
1507 dma_free_coherent(st->dma_st.dma_chan->device->dev, pages * PAGE_SIZE, in at91_adc_dma_init()
1508 st->dma_st.rx_buf, st->dma_st.rx_dma_buf); in at91_adc_dma_init()
1510 dma_release_channel(st->dma_st.dma_chan); in at91_adc_dma_init()
1511 st->dma_st.dma_chan = NULL; in at91_adc_dma_init()
1513 dev_info(&pdev->dev, "continuing without DMA support\n"); in at91_adc_dma_init()
1525 if (!st->dma_st.dma_chan) in at91_adc_dma_disable()
1529 dmaengine_terminate_sync(st->dma_st.dma_chan); in at91_adc_dma_disable()
1531 dma_free_coherent(st->dma_st.dma_chan->device->dev, pages * PAGE_SIZE, in at91_adc_dma_disable()
1532 st->dma_st.rx_buf, st->dma_st.rx_dma_buf); in at91_adc_dma_disable()
1533 dma_release_channel(st->dma_st.dma_chan); in at91_adc_dma_disable()
1534 st->dma_st.dma_chan = NULL; in at91_adc_dma_disable()
1536 dev_info(&pdev->dev, "continuing without DMA support\n"); in at91_adc_dma_disable()
1545 return -EINVAL; in at91_adc_set_watermark()
1547 if (!st->selected_trig->hw_trig) { in at91_adc_set_watermark()
1548 dev_dbg(&indio_dev->dev, "we need hw trigger for DMA\n"); in at91_adc_set_watermark()
1552 dev_dbg(&indio_dev->dev, "new watermark is %u\n", val); in at91_adc_set_watermark()
1553 st->dma_st.watermark = val; in at91_adc_set_watermark()
1556 * The logic here is: if we have watermark 1, it means we do in at91_adc_set_watermark()
1558 * If the watermark is higher, we do DMA to do all the transfers in bulk in at91_adc_set_watermark()
1562 at91_adc_dma_disable(to_platform_device(&indio_dev->dev)); in at91_adc_set_watermark()
1564 at91_adc_dma_init(to_platform_device(&indio_dev->dev)); in at91_adc_set_watermark()
1567 * We can start the DMA only after setting the watermark and in at91_adc_set_watermark()
1572 at91_adc_dma_disable(to_platform_device(&indio_dev->dev)); in at91_adc_set_watermark()
1582 if (bitmap_subset(scan_mask, &st->touch_st.channels_bitmask, in at91_adc_update_scan_mode()
1589 if (bitmap_intersects(&st->touch_st.channels_bitmask, scan_mask, in at91_adc_update_scan_mode()
1591 return -EINVAL; in at91_adc_update_scan_mode()
1608 at91_adc_setup_samp_freq(indio_dev, st->soc_info.min_sample_rate); in at91_adc_hw_init()
1620 return scnprintf(buf, PAGE_SIZE, "%d\n", !!st->dma_st.dma_chan); in at91_adc_get_fifo_state()
1629 return scnprintf(buf, PAGE_SIZE, "%d\n", st->dma_st.watermark); in at91_adc_get_watermark()
1678 if (st->selected_trig->hw_trig) in at91_adc_buffer_and_trigger_init()
1683 ret = devm_iio_triggered_buffer_setup_ext(&indio->dev, indio, in at91_adc_buffer_and_trigger_init()
1691 if (!st->selected_trig->hw_trig) in at91_adc_buffer_and_trigger_init()
1694 st->trig = at91_adc_allocate_trigger(indio, st->selected_trig->name); in at91_adc_buffer_and_trigger_init()
1695 if (IS_ERR(st->trig)) { in at91_adc_buffer_and_trigger_init()
1697 return PTR_ERR(st->trig); in at91_adc_buffer_and_trigger_init()
1702 * a watermark of 1 in at91_adc_buffer_and_trigger_init()
1704 st->dma_st.watermark = 1; in at91_adc_buffer_and_trigger_init()
1717 indio_dev = devm_iio_device_alloc(&pdev->dev, sizeof(*st)); in at91_adc_probe()
1719 return -ENOMEM; in at91_adc_probe()
1721 indio_dev->name = dev_name(&pdev->dev); in at91_adc_probe()
1722 indio_dev->modes = INDIO_DIRECT_MODE | INDIO_BUFFER_SOFTWARE; in at91_adc_probe()
1723 indio_dev->info = &at91_adc_info; in at91_adc_probe()
1724 indio_dev->channels = at91_adc_channels; in at91_adc_probe()
1725 indio_dev->num_channels = ARRAY_SIZE(at91_adc_channels); in at91_adc_probe()
1728 st->indio_dev = indio_dev; in at91_adc_probe()
1730 bitmap_set(&st->touch_st.channels_bitmask, in at91_adc_probe()
1732 bitmap_set(&st->touch_st.channels_bitmask, in at91_adc_probe()
1734 bitmap_set(&st->touch_st.channels_bitmask, in at91_adc_probe()
1737 st->oversampling_ratio = AT91_OSR_1SAMPLES; in at91_adc_probe()
1739 ret = of_property_read_u32(pdev->dev.of_node, in at91_adc_probe()
1740 "atmel,min-sample-rate-hz", in at91_adc_probe()
1741 &st->soc_info.min_sample_rate); in at91_adc_probe()
1743 dev_err(&pdev->dev, in at91_adc_probe()
1744 "invalid or missing value for atmel,min-sample-rate-hz\n"); in at91_adc_probe()
1748 ret = of_property_read_u32(pdev->dev.of_node, in at91_adc_probe()
1749 "atmel,max-sample-rate-hz", in at91_adc_probe()
1750 &st->soc_info.max_sample_rate); in at91_adc_probe()
1752 dev_err(&pdev->dev, in at91_adc_probe()
1753 "invalid or missing value for atmel,max-sample-rate-hz\n"); in at91_adc_probe()
1757 ret = of_property_read_u32(pdev->dev.of_node, "atmel,startup-time-ms", in at91_adc_probe()
1758 &st->soc_info.startup_time); in at91_adc_probe()
1760 dev_err(&pdev->dev, in at91_adc_probe()
1761 "invalid or missing value for atmel,startup-time-ms\n"); in at91_adc_probe()
1765 ret = of_property_read_u32(pdev->dev.of_node, in at91_adc_probe()
1766 "atmel,trigger-edge-type", &edge_type); in at91_adc_probe()
1768 dev_dbg(&pdev->dev, in at91_adc_probe()
1769 "atmel,trigger-edge-type not specified, only software trigger available\n"); in at91_adc_probe()
1772 st->selected_trig = NULL; in at91_adc_probe()
1777 st->selected_trig = &at91_adc_trigger_list[i]; in at91_adc_probe()
1781 if (!st->selected_trig) { in at91_adc_probe()
1782 dev_err(&pdev->dev, "invalid external trigger edge value\n"); in at91_adc_probe()
1783 return -EINVAL; in at91_adc_probe()
1786 init_waitqueue_head(&st->wq_data_available); in at91_adc_probe()
1787 mutex_init(&st->lock); in at91_adc_probe()
1788 INIT_WORK(&st->touch_st.workq, at91_adc_workq_handler); in at91_adc_probe()
1790 st->base = devm_platform_get_and_ioremap_resource(pdev, 0, &res); in at91_adc_probe()
1791 if (IS_ERR(st->base)) in at91_adc_probe()
1792 return PTR_ERR(st->base); in at91_adc_probe()
1795 st->dma_st.phys_addr = res->start; in at91_adc_probe()
1797 st->irq = platform_get_irq(pdev, 0); in at91_adc_probe()
1798 if (st->irq <= 0) { in at91_adc_probe()
1799 if (!st->irq) in at91_adc_probe()
1800 st->irq = -ENXIO; in at91_adc_probe()
1802 return st->irq; in at91_adc_probe()
1805 st->per_clk = devm_clk_get(&pdev->dev, "adc_clk"); in at91_adc_probe()
1806 if (IS_ERR(st->per_clk)) in at91_adc_probe()
1807 return PTR_ERR(st->per_clk); in at91_adc_probe()
1809 st->reg = devm_regulator_get(&pdev->dev, "vddana"); in at91_adc_probe()
1810 if (IS_ERR(st->reg)) in at91_adc_probe()
1811 return PTR_ERR(st->reg); in at91_adc_probe()
1813 st->vref = devm_regulator_get(&pdev->dev, "vref"); in at91_adc_probe()
1814 if (IS_ERR(st->vref)) in at91_adc_probe()
1815 return PTR_ERR(st->vref); in at91_adc_probe()
1817 ret = devm_request_irq(&pdev->dev, st->irq, at91_adc_interrupt, 0, in at91_adc_probe()
1818 pdev->dev.driver->name, indio_dev); in at91_adc_probe()
1822 ret = regulator_enable(st->reg); in at91_adc_probe()
1826 ret = regulator_enable(st->vref); in at91_adc_probe()
1830 st->vref_uv = regulator_get_voltage(st->vref); in at91_adc_probe()
1831 if (st->vref_uv <= 0) { in at91_adc_probe()
1832 ret = -EINVAL; in at91_adc_probe()
1838 ret = clk_prepare_enable(st->per_clk); in at91_adc_probe()
1844 ret = at91_adc_buffer_and_trigger_init(&pdev->dev, indio_dev); in at91_adc_probe()
1848 if (dma_coerce_mask_and_coherent(&indio_dev->dev, DMA_BIT_MASK(32))) in at91_adc_probe()
1849 dev_info(&pdev->dev, "cannot set DMA mask to 32-bit\n"); in at91_adc_probe()
1855 if (st->selected_trig->hw_trig) in at91_adc_probe()
1856 dev_info(&pdev->dev, "setting up trigger as %s\n", in at91_adc_probe()
1857 st->selected_trig->name); in at91_adc_probe()
1859 dev_info(&pdev->dev, "version: %x\n", in at91_adc_probe()
1860 readl_relaxed(st->base + AT91_SAMA5D2_VERSION)); in at91_adc_probe()
1867 clk_disable_unprepare(st->per_clk); in at91_adc_probe()
1869 regulator_disable(st->vref); in at91_adc_probe()
1871 regulator_disable(st->reg); in at91_adc_probe()
1884 clk_disable_unprepare(st->per_clk); in at91_adc_remove()
1886 regulator_disable(st->vref); in at91_adc_remove()
1887 regulator_disable(st->reg); in at91_adc_remove()
1905 clk_disable_unprepare(st->per_clk); in at91_adc_suspend()
1906 regulator_disable(st->vref); in at91_adc_suspend()
1907 regulator_disable(st->reg); in at91_adc_suspend()
1922 ret = regulator_enable(st->reg); in at91_adc_resume()
1926 ret = regulator_enable(st->vref); in at91_adc_resume()
1930 ret = clk_prepare_enable(st->per_clk); in at91_adc_resume()
1944 return at91_adc_configure_trigger(st->trig, true); in at91_adc_resume()
1950 regulator_disable(st->vref); in at91_adc_resume()
1952 regulator_disable(st->reg); in at91_adc_resume()
1954 dev_err(&indio_dev->dev, "failed to resume\n"); in at91_adc_resume()
1962 .compatible = "atmel,sama5d2-adc",
1973 .name = "at91-sama5d2_adc",