Lines Matching +full:full +full:- +full:ohms
81 struct drm_encoder *encoder = &intel_dsi->base.base; in vlv_dsi_wait_for_fifo_empty()
82 struct drm_device *dev = encoder->dev; in vlv_dsi_wait_for_fifo_empty()
91 drm_err(&dev_priv->drm, "DPI FIFOs are not empty\n"); in vlv_dsi_wait_for_fifo_empty()
103 for (j = 0; j < min_t(u32, len - i, 4); j++) in write_data()
119 for (j = 0; j < min_t(u32, len - i, 4); j++) in read_data()
128 struct drm_device *dev = intel_dsi_host->intel_dsi->base.base.dev; in intel_dsi_host_transfer()
130 enum port port = intel_dsi_host->port; in intel_dsi_host_transfer()
144 if (msg->flags & MIPI_DSI_MSG_USE_LPM) { in intel_dsi_host_transfer()
160 drm_err(&dev_priv->drm, in intel_dsi_host_transfer()
161 "Timeout waiting for HS/LP DATA FIFO !full\n"); in intel_dsi_host_transfer()
167 if (msg->rx_len) { in intel_dsi_host_transfer()
174 drm_err(&dev_priv->drm, in intel_dsi_host_transfer()
175 "Timeout waiting for HS/LP CTRL FIFO !full\n"); in intel_dsi_host_transfer()
181 /* ->rx_len is set only for reads */ in intel_dsi_host_transfer()
182 if (msg->rx_len) { in intel_dsi_host_transfer()
186 drm_err(&dev_priv->drm, in intel_dsi_host_transfer()
189 read_data(dev_priv, data_reg, msg->rx_buf, msg->rx_len); in intel_dsi_host_transfer()
222 struct drm_encoder *encoder = &intel_dsi->base.base; in dpi_send_cmd()
223 struct drm_device *dev = encoder->dev; in dpi_send_cmd()
238 drm_dbg_kms(&dev_priv->drm, in dpi_send_cmd()
245 drm_err(&dev_priv->drm, in dpi_send_cmd()
269 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); in intel_dsi_compute_config()
272 struct intel_connector *intel_connector = intel_dsi->attached_connector; in intel_dsi_compute_config()
273 const struct drm_display_mode *fixed_mode = intel_connector->panel.fixed_mode; in intel_dsi_compute_config()
274 struct drm_display_mode *adjusted_mode = &pipe_config->hw.adjusted_mode; in intel_dsi_compute_config()
277 drm_dbg_kms(&dev_priv->drm, "\n"); in intel_dsi_compute_config()
278 pipe_config->output_format = INTEL_OUTPUT_FORMAT_RGB; in intel_dsi_compute_config()
291 if (adjusted_mode->flags & DRM_MODE_FLAG_DBLSCAN) in intel_dsi_compute_config()
292 return -EINVAL; in intel_dsi_compute_config()
295 adjusted_mode->flags = 0; in intel_dsi_compute_config()
297 if (intel_dsi->pixel_format == MIPI_DSI_FMT_RGB888) in intel_dsi_compute_config()
298 pipe_config->pipe_bpp = 24; in intel_dsi_compute_config()
300 pipe_config->pipe_bpp = 18; in intel_dsi_compute_config()
304 pipe_config->mode_flags |= in intel_dsi_compute_config()
308 if (intel_dsi->ports == BIT(PORT_C)) in intel_dsi_compute_config()
309 pipe_config->cpu_transcoder = TRANSCODER_DSI_C; in intel_dsi_compute_config()
311 pipe_config->cpu_transcoder = TRANSCODER_DSI_A; in intel_dsi_compute_config()
315 return -EINVAL; in intel_dsi_compute_config()
319 return -EINVAL; in intel_dsi_compute_config()
322 pipe_config->clock_set = true; in intel_dsi_compute_config()
329 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); in glk_dsi_enable_io()
339 for_each_dsi_port(port, intel_dsi->ports) { in glk_dsi_enable_io()
351 for_each_dsi_port(port, intel_dsi->ports) { in glk_dsi_enable_io()
361 for_each_dsi_port(port, intel_dsi->ports) { in glk_dsi_enable_io()
364 drm_err(&dev_priv->drm, "MIPIO port is powergated\n"); in glk_dsi_enable_io()
368 for_each_dsi_port(port, intel_dsi->ports) { in glk_dsi_enable_io()
378 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); in glk_dsi_device_ready()
384 for_each_dsi_port(port, intel_dsi->ports) { in glk_dsi_device_ready()
387 drm_err(&dev_priv->drm, "PHY is not ON\n"); in glk_dsi_device_ready()
396 for_each_dsi_port(port, intel_dsi->ports) { in glk_dsi_device_ready()
413 drm_err(&dev_priv->drm, "ULPS not active\n"); in glk_dsi_device_ready()
434 for_each_dsi_port(port, intel_dsi->ports) { in glk_dsi_device_ready()
437 drm_err(&dev_priv->drm, in glk_dsi_device_ready()
442 for_each_dsi_port(port, intel_dsi->ports) { in glk_dsi_device_ready()
445 drm_err(&dev_priv->drm, in glk_dsi_device_ready()
446 "D-PHY not entering LP-11 state\n"); in glk_dsi_device_ready()
452 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); in bxt_dsi_device_ready()
457 drm_dbg_kms(&dev_priv->drm, "\n"); in bxt_dsi_device_ready()
460 for_each_dsi_port(port, intel_dsi->ports) { in bxt_dsi_device_ready()
468 for_each_dsi_port(port, intel_dsi->ports) { in bxt_dsi_device_ready()
480 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); in vlv_dsi_device_ready()
485 drm_dbg_kms(&dev_priv->drm, "\n"); in vlv_dsi_device_ready()
488 /* program rcomp for compliance, reduce from 50 ohms to 45 ohms in vlv_dsi_device_ready()
496 for_each_dsi_port(port, intel_dsi->ports) { in vlv_dsi_device_ready()
523 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); in intel_dsi_device_ready()
535 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); in glk_dsi_enter_low_power_mode()
541 for_each_dsi_port(port, intel_dsi->ports) { in glk_dsi_enter_low_power_mode()
549 for_each_dsi_port(port, intel_dsi->ports) { in glk_dsi_enter_low_power_mode()
552 drm_err(&dev_priv->drm, "PHY is not turning OFF\n"); in glk_dsi_enter_low_power_mode()
556 for_each_dsi_port(port, intel_dsi->ports) { in glk_dsi_enter_low_power_mode()
559 drm_err(&dev_priv->drm, in glk_dsi_enter_low_power_mode()
566 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); in glk_dsi_disable_mipi_io()
577 for_each_dsi_port(port, intel_dsi->ports) { in glk_dsi_disable_mipi_io()
580 drm_err(&dev_priv->drm, "PHY is not turning OFF\n"); in glk_dsi_disable_mipi_io()
584 for_each_dsi_port(port, intel_dsi->ports) { in glk_dsi_disable_mipi_io()
599 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); in vlv_dsi_clear_device_ready()
603 drm_dbg_kms(&dev_priv->drm, "\n"); in vlv_dsi_clear_device_ready()
604 for_each_dsi_port(port, intel_dsi->ports) { in vlv_dsi_clear_device_ready()
623 * On VLV/CHV, wait till Clock lanes are in LP-00 state for MIPI in vlv_dsi_clear_device_ready()
629 drm_err(&dev_priv->drm, "DSI LP not going Low\n"); in vlv_dsi_clear_device_ready()
644 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); in intel_dsi_port_enable()
645 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); in intel_dsi_port_enable()
649 if (intel_dsi->dual_link == DSI_DUAL_LINK_FRONT_BACK) { in intel_dsi_port_enable()
652 for_each_dsi_port(port, intel_dsi->ports) { in intel_dsi_port_enable()
656 intel_dsi->pixel_overlap << in intel_dsi_port_enable()
664 intel_dsi->pixel_overlap << in intel_dsi_port_enable()
670 for_each_dsi_port(port, intel_dsi->ports) { in intel_dsi_port_enable()
680 if (intel_dsi->ports == (BIT(PORT_A) | BIT(PORT_C))) { in intel_dsi_port_enable()
681 temp |= (intel_dsi->dual_link - 1) in intel_dsi_port_enable()
686 temp |= crtc->pipe ? in intel_dsi_port_enable()
691 if (intel_dsi->pixel_format != MIPI_DSI_FMT_RGB888) in intel_dsi_port_enable()
702 struct drm_device *dev = encoder->base.dev; in intel_dsi_port_disable()
707 for_each_dsi_port(port, intel_dsi->ports) { in intel_dsi_port_disable()
712 /* de-assert ip_tg_enable signal */ in intel_dsi_port_disable()
726 intel_dsi->panel_power_off_time); in intel_dsi_wait_panel_power_cycle()
728 if (panel_power_off_duration < (s64)intel_dsi->panel_pwr_cycle_delay) in intel_dsi_wait_panel_power_cycle()
729 msleep(intel_dsi->panel_pwr_cycle_delay - panel_power_off_duration); in intel_dsi_wait_panel_power_cycle()
748 * - power on - MIPIPanelPowerOn - power on
749 * - wait t1+t2 - wait t1+t2
750 * - MIPIDeassertResetPin - MIPIDeassertResetPin - MIPIDeassertResetPin
751 * - io lines to lp-11 - io lines to lp-11 - io lines to lp-11
752 * - MIPISendInitialDcsCmds - MIPISendInitialDcsCmds - MIPISendInitialDcsCmds
753 * - MIPITearOn
754 * - MIPIDisplayOn
755 * - turn on DPI - turn on DPI - set pipe to dsr mode
756 * - MIPIDisplayOn - MIPIDisplayOn
757 * - wait t5 - wait t5
758 * - backlight on - MIPIBacklightOn - backlight on
760 * - backlight off - MIPIBacklightOff - backlight off
761 * - wait t6 - wait t6
762 * - MIPIDisplayOff
763 * - turn off DPI - turn off DPI - disable pipe dsr mode
764 * - MIPITearOff
765 * - MIPIDisplayOff - MIPIDisplayOff
766 * - io lines to lp-00 - io lines to lp-00 - io lines to lp-00
767 * - MIPIAssertResetPin - MIPIAssertResetPin - MIPIAssertResetPin
768 * - wait t3 - wait t3
769 * - power off - MIPIPanelPowerOff - power off
770 * - wait t4 - wait t4
783 struct intel_crtc *crtc = to_intel_crtc(pipe_config->uapi.crtc); in intel_dsi_pre_enable()
784 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); in intel_dsi_pre_enable()
785 enum pipe pipe = crtc->pipe; in intel_dsi_pre_enable()
790 drm_dbg_kms(&dev_priv->drm, "\n"); in intel_dsi_pre_enable()
834 * Give the panel time to power-on and then deassert its reset. in intel_dsi_pre_enable()
835 * Depending on the VBT MIPI sequences version the deassert-seq in intel_dsi_pre_enable()
837 * the delay in that case. If there is no deassert-seq, then an in intel_dsi_pre_enable()
838 * unconditional msleep is used to give the panel time to power-on. in intel_dsi_pre_enable()
840 if (dev_priv->vbt.dsi.sequence[MIPI_SEQ_DEASSERT_RESET]) { in intel_dsi_pre_enable()
841 intel_dsi_msleep(intel_dsi, intel_dsi->panel_on_delay); in intel_dsi_pre_enable()
844 msleep(intel_dsi->panel_on_delay); in intel_dsi_pre_enable()
855 /* Put device in ready state (LP-11) */ in intel_dsi_pre_enable()
866 * Enable port in pre-enable phase itself because as per hw team in intel_dsi_pre_enable()
870 for_each_dsi_port(port, intel_dsi->ports) in intel_dsi_pre_enable()
877 for_each_dsi_port(port, intel_dsi->ports) in intel_dsi_pre_enable()
895 drm_WARN_ON(state->base.dev, crtc_state->has_pch_encoder); in bxt_dsi_enable()
909 struct drm_i915_private *i915 = to_i915(encoder->base.dev); in intel_dsi_disable()
913 drm_dbg_kms(&i915->drm, "\n"); in intel_dsi_disable()
925 for_each_dsi_port(port, intel_dsi->ports) in intel_dsi_disable()
933 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); in intel_dsi_clear_device_ready()
946 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); in intel_dsi_post_disable()
951 drm_dbg_kms(&dev_priv->drm, "\n"); in intel_dsi_post_disable()
960 for_each_dsi_port(port, intel_dsi->ports) in intel_dsi_post_disable()
977 /* Transition to LP-00 */ in intel_dsi_post_disable()
1007 intel_dsi_msleep(intel_dsi, intel_dsi->panel_off_delay); in intel_dsi_post_disable()
1010 intel_dsi->panel_power_off_time = ktime_get_boottime(); in intel_dsi_post_disable()
1023 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); in intel_dsi_get_hw_state()
1029 drm_dbg_kms(&dev_priv->drm, "\n"); in intel_dsi_get_hw_state()
1032 encoder->power_domain); in intel_dsi_get_hw_state()
1046 for_each_dsi_port(port, intel_dsi->ports) { in intel_dsi_get_hw_state()
1078 if (drm_WARN_ON(&dev_priv->drm, tmp > PIPE_C)) in intel_dsi_get_hw_state()
1091 intel_display_power_put(dev_priv, encoder->power_domain, wakeref); in intel_dsi_get_hw_state()
1099 struct drm_device *dev = encoder->base.dev; in bxt_dsi_get_pipe_config()
1102 &pipe_config->hw.adjusted_mode; in bxt_dsi_get_pipe_config()
1104 struct intel_crtc *crtc = to_intel_crtc(pipe_config->uapi.crtc); in bxt_dsi_get_pipe_config()
1106 unsigned int lane_count = intel_dsi->lane_count; in bxt_dsi_get_pipe_config()
1115 adjusted_mode_sw = &crtc->config->hw.adjusted_mode; in bxt_dsi_get_pipe_config()
1118 * Atleast one port is active as encoder->get_config called only if in bxt_dsi_get_pipe_config()
1119 * encoder->get_hw_state() returns true. in bxt_dsi_get_pipe_config()
1121 for_each_dsi_port(port, intel_dsi->ports) { in bxt_dsi_get_pipe_config()
1130 pipe_config->pipe_bpp = bdw_get_pipemisc_bpp(crtc); in bxt_dsi_get_pipe_config()
1133 pipe_config->mode_flags |= in bxt_dsi_get_pipe_config()
1137 adjusted_mode->crtc_hdisplay = in bxt_dsi_get_pipe_config()
1140 adjusted_mode->crtc_vdisplay = in bxt_dsi_get_pipe_config()
1143 adjusted_mode->crtc_vtotal = in bxt_dsi_get_pipe_config()
1147 hactive = adjusted_mode->crtc_hdisplay; in bxt_dsi_get_pipe_config()
1151 * Meaningful for video mode non-burst sync pulse mode only, in bxt_dsi_get_pipe_config()
1152 * can be zero for non-burst sync events and burst modes in bxt_dsi_get_pipe_config()
1159 intel_dsi->burst_mode_ratio); in bxt_dsi_get_pipe_config()
1161 intel_dsi->burst_mode_ratio); in bxt_dsi_get_pipe_config()
1163 intel_dsi->burst_mode_ratio); in bxt_dsi_get_pipe_config()
1165 if (intel_dsi->dual_link) { in bxt_dsi_get_pipe_config()
1176 adjusted_mode->crtc_htotal = hactive + hfp + hsync + hbp; in bxt_dsi_get_pipe_config()
1177 adjusted_mode->crtc_hsync_start = hfp + adjusted_mode->crtc_hdisplay; in bxt_dsi_get_pipe_config()
1178 adjusted_mode->crtc_hsync_end = hsync + adjusted_mode->crtc_hsync_start; in bxt_dsi_get_pipe_config()
1179 adjusted_mode->crtc_hblank_start = adjusted_mode->crtc_hdisplay; in bxt_dsi_get_pipe_config()
1180 adjusted_mode->crtc_hblank_end = adjusted_mode->crtc_htotal; in bxt_dsi_get_pipe_config()
1182 adjusted_mode->crtc_vsync_start = vfp + adjusted_mode->crtc_vdisplay; in bxt_dsi_get_pipe_config()
1183 adjusted_mode->crtc_vsync_end = vsync + adjusted_mode->crtc_vsync_start; in bxt_dsi_get_pipe_config()
1184 adjusted_mode->crtc_vblank_start = adjusted_mode->crtc_vdisplay; in bxt_dsi_get_pipe_config()
1185 adjusted_mode->crtc_vblank_end = adjusted_mode->crtc_vtotal; in bxt_dsi_get_pipe_config()
1199 hfp_sw = adjusted_mode_sw->crtc_hsync_start - in bxt_dsi_get_pipe_config()
1200 adjusted_mode_sw->crtc_hdisplay; in bxt_dsi_get_pipe_config()
1201 hsync_sw = adjusted_mode_sw->crtc_hsync_end - in bxt_dsi_get_pipe_config()
1202 adjusted_mode_sw->crtc_hsync_start; in bxt_dsi_get_pipe_config()
1203 hbp_sw = adjusted_mode_sw->crtc_htotal - in bxt_dsi_get_pipe_config()
1204 adjusted_mode_sw->crtc_hsync_end; in bxt_dsi_get_pipe_config()
1206 if (intel_dsi->dual_link) { in bxt_dsi_get_pipe_config()
1213 intel_dsi->burst_mode_ratio); in bxt_dsi_get_pipe_config()
1215 intel_dsi->burst_mode_ratio); in bxt_dsi_get_pipe_config()
1217 intel_dsi->burst_mode_ratio); in bxt_dsi_get_pipe_config()
1221 intel_dsi->burst_mode_ratio); in bxt_dsi_get_pipe_config()
1223 intel_dsi->burst_mode_ratio); in bxt_dsi_get_pipe_config()
1225 intel_dsi->burst_mode_ratio); in bxt_dsi_get_pipe_config()
1227 if (intel_dsi->dual_link) { in bxt_dsi_get_pipe_config()
1233 crtc_htotal_sw = adjusted_mode_sw->crtc_hdisplay + hfp_sw + in bxt_dsi_get_pipe_config()
1235 crtc_hsync_start_sw = hfp_sw + adjusted_mode_sw->crtc_hdisplay; in bxt_dsi_get_pipe_config()
1237 crtc_hblank_start_sw = adjusted_mode_sw->crtc_hdisplay; in bxt_dsi_get_pipe_config()
1240 if (adjusted_mode->crtc_htotal == crtc_htotal_sw) in bxt_dsi_get_pipe_config()
1241 adjusted_mode->crtc_htotal = adjusted_mode_sw->crtc_htotal; in bxt_dsi_get_pipe_config()
1243 if (adjusted_mode->crtc_hsync_start == crtc_hsync_start_sw) in bxt_dsi_get_pipe_config()
1244 adjusted_mode->crtc_hsync_start = in bxt_dsi_get_pipe_config()
1245 adjusted_mode_sw->crtc_hsync_start; in bxt_dsi_get_pipe_config()
1247 if (adjusted_mode->crtc_hsync_end == crtc_hsync_end_sw) in bxt_dsi_get_pipe_config()
1248 adjusted_mode->crtc_hsync_end = in bxt_dsi_get_pipe_config()
1249 adjusted_mode_sw->crtc_hsync_end; in bxt_dsi_get_pipe_config()
1251 if (adjusted_mode->crtc_hblank_start == crtc_hblank_start_sw) in bxt_dsi_get_pipe_config()
1252 adjusted_mode->crtc_hblank_start = in bxt_dsi_get_pipe_config()
1253 adjusted_mode_sw->crtc_hblank_start; in bxt_dsi_get_pipe_config()
1255 if (adjusted_mode->crtc_hblank_end == crtc_hblank_end_sw) in bxt_dsi_get_pipe_config()
1256 adjusted_mode->crtc_hblank_end = in bxt_dsi_get_pipe_config()
1257 adjusted_mode_sw->crtc_hblank_end; in bxt_dsi_get_pipe_config()
1263 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); in intel_dsi_get_config()
1265 drm_dbg_kms(&dev_priv->drm, "\n"); in intel_dsi_get_config()
1267 pipe_config->output_types |= BIT(INTEL_OUTPUT_DSI); in intel_dsi_get_config()
1277 pipe_config->hw.adjusted_mode.crtc_clock = pclk; in intel_dsi_get_config()
1278 pipe_config->port_clock = pclk; in intel_dsi_get_config()
1299 struct drm_device *dev = encoder->dev; in set_dsi_timings()
1303 unsigned int bpp = mipi_dsi_pixel_format_to_bpp(intel_dsi->pixel_format); in set_dsi_timings()
1304 unsigned int lane_count = intel_dsi->lane_count; in set_dsi_timings()
1308 hactive = adjusted_mode->crtc_hdisplay; in set_dsi_timings()
1309 hfp = adjusted_mode->crtc_hsync_start - adjusted_mode->crtc_hdisplay; in set_dsi_timings()
1310 hsync = adjusted_mode->crtc_hsync_end - adjusted_mode->crtc_hsync_start; in set_dsi_timings()
1311 hbp = adjusted_mode->crtc_htotal - adjusted_mode->crtc_hsync_end; in set_dsi_timings()
1313 if (intel_dsi->dual_link) { in set_dsi_timings()
1315 if (intel_dsi->dual_link == DSI_DUAL_LINK_FRONT_BACK) in set_dsi_timings()
1316 hactive += intel_dsi->pixel_overlap; in set_dsi_timings()
1322 vfp = adjusted_mode->crtc_vsync_start - adjusted_mode->crtc_vdisplay; in set_dsi_timings()
1323 vsync = adjusted_mode->crtc_vsync_end - adjusted_mode->crtc_vsync_start; in set_dsi_timings()
1324 vbp = adjusted_mode->crtc_vtotal - adjusted_mode->crtc_vsync_end; in set_dsi_timings()
1328 intel_dsi->burst_mode_ratio); in set_dsi_timings()
1329 hfp = txbyteclkhs(hfp, bpp, lane_count, intel_dsi->burst_mode_ratio); in set_dsi_timings()
1331 intel_dsi->burst_mode_ratio); in set_dsi_timings()
1332 hbp = txbyteclkhs(hbp, bpp, lane_count, intel_dsi->burst_mode_ratio); in set_dsi_timings()
1334 for_each_dsi_port(port, intel_dsi->ports) { in set_dsi_timings()
1343 adjusted_mode->crtc_hdisplay); in set_dsi_timings()
1345 adjusted_mode->crtc_vdisplay); in set_dsi_timings()
1347 adjusted_mode->crtc_vtotal); in set_dsi_timings()
1354 /* meaningful for video mode non-burst sync pulse mode only, in set_dsi_timings()
1355 * can be zero for non-burst sync events and burst modes */ in set_dsi_timings()
1388 struct drm_encoder *encoder = &intel_encoder->base; in intel_dsi_prepare()
1389 struct drm_device *dev = encoder->dev; in intel_dsi_prepare()
1391 struct intel_crtc *crtc = to_intel_crtc(pipe_config->uapi.crtc); in intel_dsi_prepare()
1393 const struct drm_display_mode *adjusted_mode = &pipe_config->hw.adjusted_mode; in intel_dsi_prepare()
1395 unsigned int bpp = mipi_dsi_pixel_format_to_bpp(intel_dsi->pixel_format); in intel_dsi_prepare()
1399 drm_dbg_kms(&dev_priv->drm, "pipe %c\n", pipe_name(crtc->pipe)); in intel_dsi_prepare()
1401 mode_hdisplay = adjusted_mode->crtc_hdisplay; in intel_dsi_prepare()
1403 if (intel_dsi->dual_link) { in intel_dsi_prepare()
1405 if (intel_dsi->dual_link == DSI_DUAL_LINK_FRONT_BACK) in intel_dsi_prepare()
1406 mode_hdisplay += intel_dsi->pixel_overlap; in intel_dsi_prepare()
1409 for_each_dsi_port(port, intel_dsi->ports) { in intel_dsi_prepare()
1426 enum pipe pipe = crtc->pipe; in intel_dsi_prepare()
1440 intel_dsi->dphy_reg); in intel_dsi_prepare()
1443 …adjusted_mode->crtc_vdisplay << VERTICAL_ADDRESS_SHIFT | mode_hdisplay << HORIZONTAL_ADDRESS_SHIFT… in intel_dsi_prepare()
1448 val = intel_dsi->lane_count << DATA_LANES_PRG_REG_SHIFT; in intel_dsi_prepare()
1450 val |= intel_dsi->channel << CMD_MODE_CHANNEL_NUMBER_SHIFT; in intel_dsi_prepare()
1453 val |= intel_dsi->channel << VID_MODE_CHANNEL_NUMBER_SHIFT; in intel_dsi_prepare()
1454 val |= pixel_format_to_reg(intel_dsi->pixel_format); in intel_dsi_prepare()
1458 if (intel_dsi->eotp_pkt == 0) in intel_dsi_prepare()
1460 if (intel_dsi->clock_stop) in intel_dsi_prepare()
1469 for_each_dsi_port(port, intel_dsi->ports) { in intel_dsi_prepare()
1480 * In non-burst mode, Value greater than one DPI frame time in in intel_dsi_prepare()
1490 intel_dsi->video_mode_format == VIDEO_MODE_BURST) { in intel_dsi_prepare()
1492 …txbyteclkhs(adjusted_mode->crtc_htotal, bpp, intel_dsi->lane_count, intel_dsi->burst_mode_ratio) +… in intel_dsi_prepare()
1495 …txbyteclkhs(adjusted_mode->crtc_vtotal * adjusted_mode->crtc_htotal, bpp, intel_dsi->lane_count, i… in intel_dsi_prepare()
1498 intel_dsi->lp_rx_timeout); in intel_dsi_prepare()
1500 intel_dsi->turn_arnd_val); in intel_dsi_prepare()
1502 intel_dsi->rst_timer_val); in intel_dsi_prepare()
1508 txclkesc(intel_dsi->escape_clk_div, 100)); in intel_dsi_prepare()
1511 !intel_dsi->dual_link) { in intel_dsi_prepare()
1520 intel_dsi->init_count); in intel_dsi_prepare()
1528 intel_dsi->init_count); in intel_dsi_prepare()
1536 intel_dsi->hs_to_lp_count); in intel_dsi_prepare()
1545 intel_dsi->lp_byte_clk); in intel_dsi_prepare()
1549 intel_dsi->lp_byte_clk); in intel_dsi_prepare()
1552 intel_dsi->dphy_reg); in intel_dsi_prepare()
1561 intel_dsi->bw_timer); in intel_dsi_prepare()
1564 …intel_dsi->clk_lp_to_hs_count << LP_HS_SSW_CNT_SHIFT | intel_dsi->clk_hs_to_lp_count << HS_LP_PWR_… in intel_dsi_prepare()
1571 …intel_dsi->video_frmt_cfg_bits | intel_dsi->video_mode_format | IP_TG_CONFIG | RANDOM_DPI_DISPLAY_… in intel_dsi_prepare()
1577 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); in intel_dsi_unprepare()
1585 for_each_dsi_port(port, intel_dsi->ports) { in intel_dsi_unprepare()
1635 struct drm_i915_private *dev_priv = to_i915(connector->base.dev); in vlv_dsi_add_properties()
1637 if (connector->panel.fixed_mode) { in vlv_dsi_add_properties()
1644 drm_connector_attach_scaling_mode_property(&connector->base, in vlv_dsi_add_properties()
1647 connector->base.state->scaling_mode = DRM_MODE_SCALE_ASPECT; in vlv_dsi_add_properties()
1650 &connector->base, in vlv_dsi_add_properties()
1652 connector->panel.fixed_mode->hdisplay, in vlv_dsi_add_properties()
1653 connector->panel.fixed_mode->vdisplay); in vlv_dsi_add_properties()
1666 struct drm_device *dev = intel_dsi->base.base.dev; in vlv_dphy_param_init()
1668 struct mipi_config *mipi_config = dev_priv->vbt.dsi.config; in vlv_dphy_param_init()
1679 switch (intel_dsi->lane_count) { in vlv_dphy_param_init()
1697 tclk_prepare_clkzero = mipi_config->tclk_prepare_clkzero; in vlv_dphy_param_init()
1698 ths_prepare_hszero = mipi_config->ths_prepare_hszero; in vlv_dphy_param_init()
1704 intel_dsi->lp_byte_clk = DIV_ROUND_UP(tlpx_ns * ui_den, 8 * ui_num); in vlv_dphy_param_init()
1716 ths_prepare_ns = max(mipi_config->ths_prepare, in vlv_dphy_param_init()
1717 mipi_config->tclk_prepare); in vlv_dphy_param_init()
1723 drm_dbg_kms(&dev_priv->drm, "prepare count too high %u\n", in vlv_dphy_param_init()
1730 (ths_prepare_hszero - ths_prepare_ns) * ui_den, in vlv_dphy_param_init()
1744 drm_dbg_kms(&dev_priv->drm, "exit zero count too high %u\n", in vlv_dphy_param_init()
1751 (tclk_prepare_clkzero - ths_prepare_ns) in vlv_dphy_param_init()
1755 drm_dbg_kms(&dev_priv->drm, "clock zero count too high %u\n", in vlv_dphy_param_init()
1761 tclk_trail_ns = max(mipi_config->tclk_trail, mipi_config->ths_trail); in vlv_dphy_param_init()
1765 drm_dbg_kms(&dev_priv->drm, "trail count too high %u\n", in vlv_dphy_param_init()
1771 intel_dsi->dphy_reg = exit_zero_cnt << 24 | trail_cnt << 16 | in vlv_dphy_param_init()
1778 * HS to LP switch count = THS-TRAIL + 2TLPX + Extra Byte Count in vlv_dphy_param_init()
1792 hs_to_lp_switch = DIV_ROUND_UP(mipi_config->ths_trail + 2 * tlpx_ui, 8); in vlv_dphy_param_init()
1794 intel_dsi->hs_to_lp_count = max(lp_to_hs_switch, hs_to_lp_switch); in vlv_dphy_param_init()
1795 intel_dsi->hs_to_lp_count += extra_byte_count; in vlv_dphy_param_init()
1798 /* LP -> HS for clock lanes in vlv_dphy_param_init()
1806 intel_dsi->clk_lp_to_hs_count = in vlv_dphy_param_init()
1812 intel_dsi->clk_lp_to_hs_count += extra_byte_count; in vlv_dphy_param_init()
1814 /* HS->LP for Clock Lanes in vlv_dphy_param_init()
1821 intel_dsi->clk_hs_to_lp_count = in vlv_dphy_param_init()
1824 intel_dsi->clk_hs_to_lp_count += extra_byte_count; in vlv_dphy_param_init()
1831 struct drm_device *dev = &dev_priv->drm; in vlv_dsi_init()
1841 drm_dbg_kms(&dev_priv->drm, "\n"); in vlv_dsi_init()
1848 dev_priv->mipi_mmio_base = BXT_MIPI_BASE; in vlv_dsi_init()
1850 dev_priv->mipi_mmio_base = VLV_MIPI_BASE; in vlv_dsi_init()
1862 intel_encoder = &intel_dsi->base; in vlv_dsi_init()
1863 encoder = &intel_encoder->base; in vlv_dsi_init()
1864 intel_dsi->attached_connector = intel_connector; in vlv_dsi_init()
1866 connector = &intel_connector->base; in vlv_dsi_init()
1871 intel_encoder->compute_config = intel_dsi_compute_config; in vlv_dsi_init()
1872 intel_encoder->pre_enable = intel_dsi_pre_enable; in vlv_dsi_init()
1874 intel_encoder->enable = bxt_dsi_enable; in vlv_dsi_init()
1875 intel_encoder->disable = intel_dsi_disable; in vlv_dsi_init()
1876 intel_encoder->post_disable = intel_dsi_post_disable; in vlv_dsi_init()
1877 intel_encoder->get_hw_state = intel_dsi_get_hw_state; in vlv_dsi_init()
1878 intel_encoder->get_config = intel_dsi_get_config; in vlv_dsi_init()
1879 intel_encoder->update_pipe = intel_panel_update_backlight; in vlv_dsi_init()
1880 intel_encoder->shutdown = intel_dsi_shutdown; in vlv_dsi_init()
1882 intel_connector->get_hw_state = intel_connector_get_hw_state; in vlv_dsi_init()
1884 intel_encoder->port = port; in vlv_dsi_init()
1885 intel_encoder->type = INTEL_OUTPUT_DSI; in vlv_dsi_init()
1886 intel_encoder->power_domain = POWER_DOMAIN_PORT_DSI; in vlv_dsi_init()
1887 intel_encoder->cloneable = 0; in vlv_dsi_init()
1894 intel_encoder->pipe_mask = ~0; in vlv_dsi_init()
1896 intel_encoder->pipe_mask = BIT(PIPE_A); in vlv_dsi_init()
1898 intel_encoder->pipe_mask = BIT(PIPE_B); in vlv_dsi_init()
1900 intel_dsi->panel_power_off_time = ktime_get_boottime(); in vlv_dsi_init()
1902 if (dev_priv->vbt.dsi.config->dual_link) in vlv_dsi_init()
1903 intel_dsi->ports = BIT(PORT_A) | BIT(PORT_C); in vlv_dsi_init()
1905 intel_dsi->ports = BIT(port); in vlv_dsi_init()
1907 intel_dsi->dcs_backlight_ports = dev_priv->vbt.dsi.bl_ports; in vlv_dsi_init()
1908 intel_dsi->dcs_cabc_ports = dev_priv->vbt.dsi.cabc_ports; in vlv_dsi_init()
1911 for_each_dsi_port(port, intel_dsi->ports) { in vlv_dsi_init()
1919 intel_dsi->dsi_hosts[port] = host; in vlv_dsi_init()
1923 drm_dbg_kms(&dev_priv->drm, "no device found\n"); in vlv_dsi_init()
1927 /* Use clock read-back from current hw-state for fastboot */ in vlv_dsi_init()
1930 drm_dbg_kms(&dev_priv->drm, "Calculated pclk %d GOP %d\n", in vlv_dsi_init()
1931 intel_dsi->pclk, current_mode->clock); in vlv_dsi_init()
1932 if (intel_fuzzy_clock_check(intel_dsi->pclk, in vlv_dsi_init()
1933 current_mode->clock)) { in vlv_dsi_init()
1934 drm_dbg_kms(&dev_priv->drm, "Using GOP pclk\n"); in vlv_dsi_init()
1935 intel_dsi->pclk = current_mode->clock; in vlv_dsi_init()
1951 connector->display_info.subpixel_order = SubPixelHorizontalRGB; /*XXX*/ in vlv_dsi_init()
1952 connector->interlace_allowed = false; in vlv_dsi_init()
1953 connector->doublescan_allowed = false; in vlv_dsi_init()
1957 mutex_lock(&dev->mode_config.mutex); in vlv_dsi_init()
1959 mutex_unlock(&dev->mode_config.mutex); in vlv_dsi_init()
1962 drm_dbg_kms(&dev_priv->drm, "no fixed mode\n"); in vlv_dsi_init()
1966 intel_panel_init(&intel_connector->panel, fixed_mode, NULL); in vlv_dsi_init()
1974 drm_connector_cleanup(&intel_connector->base); in vlv_dsi_init()
1976 drm_encoder_cleanup(&intel_encoder->base); in vlv_dsi_init()