Lines Matching refs:ucode
567 struct amdgpu_firmware_info *ucode, in amdgpu_ucode_init_single_fw() argument
576 if (NULL == ucode->fw) in amdgpu_ucode_init_single_fw()
579 ucode->mc_addr = mc_addr; in amdgpu_ucode_init_single_fw()
580 ucode->kaddr = kptr; in amdgpu_ucode_init_single_fw()
582 if (ucode->ucode_id == AMDGPU_UCODE_ID_STORAGE) in amdgpu_ucode_init_single_fw()
585 header = (const struct common_firmware_header *)ucode->fw->data; in amdgpu_ucode_init_single_fw()
586 cp_hdr = (const struct gfx_firmware_header_v1_0 *)ucode->fw->data; in amdgpu_ucode_init_single_fw()
587 dmcu_hdr = (const struct dmcu_firmware_header_v1_0 *)ucode->fw->data; in amdgpu_ucode_init_single_fw()
588 dmcub_hdr = (const struct dmcub_firmware_header_v1_0 *)ucode->fw->data; in amdgpu_ucode_init_single_fw()
589 mes_hdr = (const struct mes_firmware_header_v1_0 *)ucode->fw->data; in amdgpu_ucode_init_single_fw()
592 (ucode->ucode_id != AMDGPU_UCODE_ID_CP_MEC1 && in amdgpu_ucode_init_single_fw()
593 ucode->ucode_id != AMDGPU_UCODE_ID_CP_MEC2 && in amdgpu_ucode_init_single_fw()
594 ucode->ucode_id != AMDGPU_UCODE_ID_CP_MEC1_JT && in amdgpu_ucode_init_single_fw()
595 ucode->ucode_id != AMDGPU_UCODE_ID_CP_MEC2_JT && in amdgpu_ucode_init_single_fw()
596 ucode->ucode_id != AMDGPU_UCODE_ID_CP_MES && in amdgpu_ucode_init_single_fw()
597 ucode->ucode_id != AMDGPU_UCODE_ID_CP_MES_DATA && in amdgpu_ucode_init_single_fw()
598 ucode->ucode_id != AMDGPU_UCODE_ID_RLC_RESTORE_LIST_CNTL && in amdgpu_ucode_init_single_fw()
599 ucode->ucode_id != AMDGPU_UCODE_ID_RLC_RESTORE_LIST_GPM_MEM && in amdgpu_ucode_init_single_fw()
600 ucode->ucode_id != AMDGPU_UCODE_ID_RLC_RESTORE_LIST_SRM_MEM && in amdgpu_ucode_init_single_fw()
601 ucode->ucode_id != AMDGPU_UCODE_ID_RLC_IRAM && in amdgpu_ucode_init_single_fw()
602 ucode->ucode_id != AMDGPU_UCODE_ID_RLC_DRAM && in amdgpu_ucode_init_single_fw()
603 ucode->ucode_id != AMDGPU_UCODE_ID_DMCU_ERAM && in amdgpu_ucode_init_single_fw()
604 ucode->ucode_id != AMDGPU_UCODE_ID_DMCU_INTV && in amdgpu_ucode_init_single_fw()
605 ucode->ucode_id != AMDGPU_UCODE_ID_DMCUB)) { in amdgpu_ucode_init_single_fw()
606 ucode->ucode_size = le32_to_cpu(header->ucode_size_bytes); in amdgpu_ucode_init_single_fw()
608 memcpy(ucode->kaddr, (void *)((uint8_t *)ucode->fw->data + in amdgpu_ucode_init_single_fw()
610 ucode->ucode_size); in amdgpu_ucode_init_single_fw()
611 } else if (ucode->ucode_id == AMDGPU_UCODE_ID_CP_MEC1 || in amdgpu_ucode_init_single_fw()
612 ucode->ucode_id == AMDGPU_UCODE_ID_CP_MEC2) { in amdgpu_ucode_init_single_fw()
613 ucode->ucode_size = le32_to_cpu(header->ucode_size_bytes) - in amdgpu_ucode_init_single_fw()
616 memcpy(ucode->kaddr, (void *)((uint8_t *)ucode->fw->data + in amdgpu_ucode_init_single_fw()
618 ucode->ucode_size); in amdgpu_ucode_init_single_fw()
619 } else if (ucode->ucode_id == AMDGPU_UCODE_ID_CP_MEC1_JT || in amdgpu_ucode_init_single_fw()
620 ucode->ucode_id == AMDGPU_UCODE_ID_CP_MEC2_JT) { in amdgpu_ucode_init_single_fw()
621 ucode->ucode_size = le32_to_cpu(cp_hdr->jt_size) * 4; in amdgpu_ucode_init_single_fw()
623 memcpy(ucode->kaddr, (void *)((uint8_t *)ucode->fw->data + in amdgpu_ucode_init_single_fw()
626 ucode->ucode_size); in amdgpu_ucode_init_single_fw()
627 } else if (ucode->ucode_id == AMDGPU_UCODE_ID_DMCU_ERAM) { in amdgpu_ucode_init_single_fw()
628 ucode->ucode_size = le32_to_cpu(header->ucode_size_bytes) - in amdgpu_ucode_init_single_fw()
631 memcpy(ucode->kaddr, (void *)((uint8_t *)ucode->fw->data + in amdgpu_ucode_init_single_fw()
633 ucode->ucode_size); in amdgpu_ucode_init_single_fw()
634 } else if (ucode->ucode_id == AMDGPU_UCODE_ID_DMCU_INTV) { in amdgpu_ucode_init_single_fw()
635 ucode->ucode_size = le32_to_cpu(dmcu_hdr->intv_size_bytes); in amdgpu_ucode_init_single_fw()
637 memcpy(ucode->kaddr, (void *)((uint8_t *)ucode->fw->data + in amdgpu_ucode_init_single_fw()
640 ucode->ucode_size); in amdgpu_ucode_init_single_fw()
641 } else if (ucode->ucode_id == AMDGPU_UCODE_ID_DMCUB) { in amdgpu_ucode_init_single_fw()
642 ucode->ucode_size = le32_to_cpu(dmcub_hdr->inst_const_bytes); in amdgpu_ucode_init_single_fw()
643 memcpy(ucode->kaddr, in amdgpu_ucode_init_single_fw()
644 (void *)((uint8_t *)ucode->fw->data + in amdgpu_ucode_init_single_fw()
646 ucode->ucode_size); in amdgpu_ucode_init_single_fw()
647 } else if (ucode->ucode_id == AMDGPU_UCODE_ID_RLC_RESTORE_LIST_CNTL) { in amdgpu_ucode_init_single_fw()
648 ucode->ucode_size = adev->gfx.rlc.save_restore_list_cntl_size_bytes; in amdgpu_ucode_init_single_fw()
649 memcpy(ucode->kaddr, adev->gfx.rlc.save_restore_list_cntl, in amdgpu_ucode_init_single_fw()
650 ucode->ucode_size); in amdgpu_ucode_init_single_fw()
651 } else if (ucode->ucode_id == AMDGPU_UCODE_ID_RLC_RESTORE_LIST_GPM_MEM) { in amdgpu_ucode_init_single_fw()
652 ucode->ucode_size = adev->gfx.rlc.save_restore_list_gpm_size_bytes; in amdgpu_ucode_init_single_fw()
653 memcpy(ucode->kaddr, adev->gfx.rlc.save_restore_list_gpm, in amdgpu_ucode_init_single_fw()
654 ucode->ucode_size); in amdgpu_ucode_init_single_fw()
655 } else if (ucode->ucode_id == AMDGPU_UCODE_ID_RLC_RESTORE_LIST_SRM_MEM) { in amdgpu_ucode_init_single_fw()
656 ucode->ucode_size = adev->gfx.rlc.save_restore_list_srm_size_bytes; in amdgpu_ucode_init_single_fw()
657 memcpy(ucode->kaddr, adev->gfx.rlc.save_restore_list_srm, in amdgpu_ucode_init_single_fw()
658 ucode->ucode_size); in amdgpu_ucode_init_single_fw()
659 } else if (ucode->ucode_id == AMDGPU_UCODE_ID_RLC_IRAM) { in amdgpu_ucode_init_single_fw()
660 ucode->ucode_size = adev->gfx.rlc.rlc_iram_ucode_size_bytes; in amdgpu_ucode_init_single_fw()
661 memcpy(ucode->kaddr, adev->gfx.rlc.rlc_iram_ucode, in amdgpu_ucode_init_single_fw()
662 ucode->ucode_size); in amdgpu_ucode_init_single_fw()
663 } else if (ucode->ucode_id == AMDGPU_UCODE_ID_RLC_DRAM) { in amdgpu_ucode_init_single_fw()
664 ucode->ucode_size = adev->gfx.rlc.rlc_dram_ucode_size_bytes; in amdgpu_ucode_init_single_fw()
665 memcpy(ucode->kaddr, adev->gfx.rlc.rlc_dram_ucode, in amdgpu_ucode_init_single_fw()
666 ucode->ucode_size); in amdgpu_ucode_init_single_fw()
667 } else if (ucode->ucode_id == AMDGPU_UCODE_ID_CP_MES) { in amdgpu_ucode_init_single_fw()
668 ucode->ucode_size = le32_to_cpu(mes_hdr->mes_ucode_size_bytes); in amdgpu_ucode_init_single_fw()
669 memcpy(ucode->kaddr, (void *)((uint8_t *)adev->mes.fw->data + in amdgpu_ucode_init_single_fw()
671 ucode->ucode_size); in amdgpu_ucode_init_single_fw()
672 } else if (ucode->ucode_id == AMDGPU_UCODE_ID_CP_MES_DATA) { in amdgpu_ucode_init_single_fw()
673 ucode->ucode_size = le32_to_cpu(mes_hdr->mes_ucode_data_size_bytes); in amdgpu_ucode_init_single_fw()
674 memcpy(ucode->kaddr, (void *)((uint8_t *)adev->mes.fw->data + in amdgpu_ucode_init_single_fw()
676 ucode->ucode_size); in amdgpu_ucode_init_single_fw()
682 static int amdgpu_ucode_patch_jt(struct amdgpu_firmware_info *ucode, in amdgpu_ucode_patch_jt() argument
690 if (NULL == ucode->fw) in amdgpu_ucode_patch_jt()
693 comm_hdr = (const struct common_firmware_header *)ucode->fw->data; in amdgpu_ucode_patch_jt()
694 header = (const struct gfx_firmware_header_v1_0 *)ucode->fw->data; in amdgpu_ucode_patch_jt()
695 dst_addr = ucode->kaddr + in amdgpu_ucode_patch_jt()
698 src_addr = (uint8_t *)ucode->fw->data + in amdgpu_ucode_patch_jt()
736 struct amdgpu_firmware_info *ucode = NULL; in amdgpu_ucode_init_bo() local
755 ucode = &adev->firmware.ucode[i]; in amdgpu_ucode_init_bo()
756 if (ucode->fw) { in amdgpu_ucode_init_bo()
757 amdgpu_ucode_init_single_fw(adev, ucode, adev->firmware.fw_buf_mc + fw_offset, in amdgpu_ucode_init_bo()
762 cp_hdr = (const struct gfx_firmware_header_v1_0 *)ucode->fw->data; in amdgpu_ucode_init_bo()
763 amdgpu_ucode_patch_jt(ucode, adev->firmware.fw_buf_mc + fw_offset, in amdgpu_ucode_init_bo()
767 fw_offset += ALIGN(ucode->ucode_size, PAGE_SIZE); in amdgpu_ucode_init_bo()