Lines Matching +full:aips +full:- +full:bus
1 // SPDX-License-Identifier: GPL-2.0+
3 // drivers/dma/imx-sdma.c
11 // Copyright 2004-2009 Freescale Semiconductor, Inc. All Rights Reserved.
26 #include <linux/dma-mapping.h>
38 #include <linux/platform_data/dma-imx.h>
41 #include <linux/mfd/syscon/imx6q-iomuxc-gpr.h>
44 #include "virt-dma.h"
128 * 0-7 Lower WML Lower watermark level
136 * 0: Source on AIPS
138 * 0: Destination on AIPS
139 * 13-15 --------- MUST BE 0
140 * 16-23 Higher WML HWML
141 * 24-27 N Total number of samples after
152 * 30 --------- MUST BE 0
184 * struct sdma_script_start_addrs - SDMA script start pointers
243 * Mode/Count of data node descriptors - IPCv2
262 * struct sdma_channel_control - Channel control Block
276 * struct sdma_state_registers - SDMA context for a channel
305 * struct sdma_context_data - sdma context specific to a channel
363 * struct sdma_desc - descriptor structor for one transfer
370 * @chn_real_count: the real count updated from bd->mode.count
389 * struct sdma_channel - housekeeping for a SDMA channel
456 * struct sdma_firmware_header - Layout of the firmware image
644 { .compatible = "fsl,imx6q-sdma", .data = &sdma_imx6q, },
645 { .compatible = "fsl,imx53-sdma", .data = &sdma_imx53, },
646 { .compatible = "fsl,imx51-sdma", .data = &sdma_imx51, },
647 { .compatible = "fsl,imx35-sdma", .data = &sdma_imx35, },
648 { .compatible = "fsl,imx31-sdma", .data = &sdma_imx31, },
649 { .compatible = "fsl,imx25-sdma", .data = &sdma_imx25, },
650 { .compatible = "fsl,imx7d-sdma", .data = &sdma_imx7d, },
651 { .compatible = "fsl,imx6ul-sdma", .data = &sdma_imx6ul, },
652 { .compatible = "fsl,imx8mq-sdma", .data = &sdma_imx8mq, },
658 #define SDMA_H_CONFIG_RTD_PINS BIT(11) /* indicates if Real-Time Debug pins are enabled */
664 u32 chnenbl0 = sdma->drvdata->chnenbl0; in chnenbl_ofs()
671 struct sdma_engine *sdma = sdmac->sdma; in sdma_config_ownership()
672 int channel = sdmac->channel; in sdma_config_ownership()
676 return -EINVAL; in sdma_config_ownership()
678 evt = readl_relaxed(sdma->regs + SDMA_H_EVTOVR); in sdma_config_ownership()
679 mcu = readl_relaxed(sdma->regs + SDMA_H_HOSTOVR); in sdma_config_ownership()
680 dsp = readl_relaxed(sdma->regs + SDMA_H_DSPOVR); in sdma_config_ownership()
697 writel_relaxed(evt, sdma->regs + SDMA_H_EVTOVR); in sdma_config_ownership()
698 writel_relaxed(mcu, sdma->regs + SDMA_H_HOSTOVR); in sdma_config_ownership()
699 writel_relaxed(dsp, sdma->regs + SDMA_H_DSPOVR); in sdma_config_ownership()
706 writel(BIT(channel), sdma->regs + SDMA_H_START); in sdma_enable_channel()
710 * sdma_run_channel0 - run a channel and wait till it's done
719 ret = readl_relaxed_poll_timeout_atomic(sdma->regs + SDMA_H_STATSTOP, in sdma_run_channel0()
722 dev_err(sdma->dev, "Timeout waiting for CH0 ready\n"); in sdma_run_channel0()
725 reg = readl(sdma->regs + SDMA_H_CONFIG); in sdma_run_channel0()
728 writel_relaxed(reg, sdma->regs + SDMA_H_CONFIG); in sdma_run_channel0()
737 struct sdma_buffer_descriptor *bd0 = sdma->bd0; in sdma_load_script()
743 buf_virt = dma_alloc_coherent(sdma->dev, size, &buf_phys, GFP_KERNEL); in sdma_load_script()
745 return -ENOMEM; in sdma_load_script()
748 spin_lock_irqsave(&sdma->channel_0_lock, flags); in sdma_load_script()
750 bd0->mode.command = C0_SETPM; in sdma_load_script()
751 bd0->mode.status = BD_DONE | BD_WRAP | BD_EXTD; in sdma_load_script()
752 bd0->mode.count = size / 2; in sdma_load_script()
753 bd0->buffer_addr = buf_phys; in sdma_load_script()
754 bd0->ext_buffer_addr = address; in sdma_load_script()
760 spin_unlock_irqrestore(&sdma->channel_0_lock, flags); in sdma_load_script()
762 dma_free_coherent(sdma->dev, size, buf_virt, buf_phys); in sdma_load_script()
769 struct sdma_engine *sdma = sdmac->sdma; in sdma_event_enable()
770 int channel = sdmac->channel; in sdma_event_enable()
774 val = readl_relaxed(sdma->regs + chnenbl); in sdma_event_enable()
776 writel_relaxed(val, sdma->regs + chnenbl); in sdma_event_enable()
781 struct sdma_engine *sdma = sdmac->sdma; in sdma_event_disable()
782 int channel = sdmac->channel; in sdma_event_disable()
786 val = readl_relaxed(sdma->regs + chnenbl); in sdma_event_disable()
788 writel_relaxed(val, sdma->regs + chnenbl); in sdma_event_disable()
798 struct virt_dma_desc *vd = vchan_next_desc(&sdmac->vc); in sdma_start_desc()
800 struct sdma_engine *sdma = sdmac->sdma; in sdma_start_desc()
801 int channel = sdmac->channel; in sdma_start_desc()
804 sdmac->desc = NULL; in sdma_start_desc()
807 sdmac->desc = desc = to_sdma_desc(&vd->tx); in sdma_start_desc()
809 list_del(&vd->node); in sdma_start_desc()
811 sdma->channel_control[channel].base_bd_ptr = desc->bd_phys; in sdma_start_desc()
812 sdma->channel_control[channel].current_bd_ptr = desc->bd_phys; in sdma_start_desc()
813 sdma_enable_channel(sdma, sdmac->channel); in sdma_start_desc()
820 enum dma_status old_status = sdmac->status; in sdma_update_channel_loop()
823 * loop mode. Iterate over descriptors, re-setup them and in sdma_update_channel_loop()
826 while (sdmac->desc) { in sdma_update_channel_loop()
827 struct sdma_desc *desc = sdmac->desc; in sdma_update_channel_loop()
829 bd = &desc->bd[desc->buf_tail]; in sdma_update_channel_loop()
831 if (bd->mode.status & BD_DONE) in sdma_update_channel_loop()
834 if (bd->mode.status & BD_RROR) { in sdma_update_channel_loop()
835 bd->mode.status &= ~BD_RROR; in sdma_update_channel_loop()
836 sdmac->status = DMA_ERROR; in sdma_update_channel_loop()
837 error = -EIO; in sdma_update_channel_loop()
841 * We use bd->mode.count to calculate the residue, since contains in sdma_update_channel_loop()
845 desc->chn_real_count = bd->mode.count; in sdma_update_channel_loop()
846 bd->mode.status |= BD_DONE; in sdma_update_channel_loop()
847 bd->mode.count = desc->period_len; in sdma_update_channel_loop()
848 desc->buf_ptail = desc->buf_tail; in sdma_update_channel_loop()
849 desc->buf_tail = (desc->buf_tail + 1) % desc->num_bd; in sdma_update_channel_loop()
857 spin_unlock(&sdmac->vc.lock); in sdma_update_channel_loop()
858 dmaengine_desc_get_callback_invoke(&desc->vd.tx, NULL); in sdma_update_channel_loop()
859 spin_lock(&sdmac->vc.lock); in sdma_update_channel_loop()
862 sdmac->status = old_status; in sdma_update_channel_loop()
872 sdmac->desc->chn_real_count = 0; in mxc_sdma_handle_channel_normal()
877 for (i = 0; i < sdmac->desc->num_bd; i++) { in mxc_sdma_handle_channel_normal()
878 bd = &sdmac->desc->bd[i]; in mxc_sdma_handle_channel_normal()
880 if (bd->mode.status & (BD_DONE | BD_RROR)) in mxc_sdma_handle_channel_normal()
881 error = -EIO; in mxc_sdma_handle_channel_normal()
882 sdmac->desc->chn_real_count += bd->mode.count; in mxc_sdma_handle_channel_normal()
886 sdmac->status = DMA_ERROR; in mxc_sdma_handle_channel_normal()
888 sdmac->status = DMA_COMPLETE; in mxc_sdma_handle_channel_normal()
896 stat = readl_relaxed(sdma->regs + SDMA_H_INTR); in sdma_int_handler()
897 writel_relaxed(stat, sdma->regs + SDMA_H_INTR); in sdma_int_handler()
902 int channel = fls(stat) - 1; in sdma_int_handler()
903 struct sdma_channel *sdmac = &sdma->channel[channel]; in sdma_int_handler()
906 spin_lock(&sdmac->vc.lock); in sdma_int_handler()
907 desc = sdmac->desc; in sdma_int_handler()
909 if (sdmac->flags & IMX_DMA_SG_LOOP) { in sdma_int_handler()
913 vchan_cookie_complete(&desc->vd); in sdma_int_handler()
918 spin_unlock(&sdmac->vc.lock); in sdma_int_handler()
931 struct sdma_engine *sdma = sdmac->sdma; in sdma_get_pc()
935 * two peripherals or memory-to-memory transfers in sdma_get_pc()
939 sdmac->pc_from_device = 0; in sdma_get_pc()
940 sdmac->pc_to_device = 0; in sdma_get_pc()
941 sdmac->device_to_device = 0; in sdma_get_pc()
942 sdmac->pc_to_pc = 0; in sdma_get_pc()
943 sdmac->is_ram_script = false; in sdma_get_pc()
947 emi_2_emi = sdma->script_addrs->ap_2_ap_addr; in sdma_get_pc()
950 emi_2_per = sdma->script_addrs->bp_2_ap_addr; in sdma_get_pc()
951 per_2_emi = sdma->script_addrs->ap_2_bp_addr; in sdma_get_pc()
954 per_2_emi = sdma->script_addrs->firi_2_mcu_addr; in sdma_get_pc()
955 emi_2_per = sdma->script_addrs->mcu_2_firi_addr; in sdma_get_pc()
958 per_2_emi = sdma->script_addrs->uart_2_mcu_addr; in sdma_get_pc()
959 emi_2_per = sdma->script_addrs->mcu_2_app_addr; in sdma_get_pc()
962 per_2_emi = sdma->script_addrs->uartsh_2_mcu_addr; in sdma_get_pc()
963 emi_2_per = sdma->script_addrs->mcu_2_shp_addr; in sdma_get_pc()
966 per_2_emi = sdma->script_addrs->ata_2_mcu_addr; in sdma_get_pc()
967 emi_2_per = sdma->script_addrs->mcu_2_ata_addr; in sdma_get_pc()
970 per_2_emi = sdma->script_addrs->app_2_mcu_addr; in sdma_get_pc()
973 if (sdmac->sdma->drvdata->ecspi_fixed) { in sdma_get_pc()
974 emi_2_per = sdma->script_addrs->mcu_2_app_addr; in sdma_get_pc()
976 emi_2_per = sdma->script_addrs->mcu_2_ecspi_addr; in sdma_get_pc()
977 sdmac->is_ram_script = true; in sdma_get_pc()
984 per_2_emi = sdma->script_addrs->app_2_mcu_addr; in sdma_get_pc()
985 emi_2_per = sdma->script_addrs->mcu_2_app_addr; in sdma_get_pc()
988 per_2_emi = sdma->script_addrs->ssish_2_mcu_addr; in sdma_get_pc()
989 emi_2_per = sdma->script_addrs->mcu_2_ssish_addr; in sdma_get_pc()
990 sdmac->is_ram_script = true; in sdma_get_pc()
998 per_2_emi = sdma->script_addrs->shp_2_mcu_addr; in sdma_get_pc()
999 emi_2_per = sdma->script_addrs->mcu_2_shp_addr; in sdma_get_pc()
1002 per_2_emi = sdma->script_addrs->asrc_2_mcu_addr; in sdma_get_pc()
1003 emi_2_per = sdma->script_addrs->asrc_2_mcu_addr; in sdma_get_pc()
1004 per_2_per = sdma->script_addrs->per_2_per_addr; in sdma_get_pc()
1005 sdmac->is_ram_script = true; in sdma_get_pc()
1008 per_2_emi = sdma->script_addrs->shp_2_mcu_addr; in sdma_get_pc()
1009 emi_2_per = sdma->script_addrs->mcu_2_shp_addr; in sdma_get_pc()
1010 per_2_per = sdma->script_addrs->per_2_per_addr; in sdma_get_pc()
1013 per_2_emi = sdma->script_addrs->mshc_2_mcu_addr; in sdma_get_pc()
1014 emi_2_per = sdma->script_addrs->mcu_2_mshc_addr; in sdma_get_pc()
1017 per_2_emi = sdma->script_addrs->dptc_dvfs_addr; in sdma_get_pc()
1020 per_2_emi = sdma->script_addrs->spdif_2_mcu_addr; in sdma_get_pc()
1021 emi_2_per = sdma->script_addrs->mcu_2_spdif_addr; in sdma_get_pc()
1024 emi_2_per = sdma->script_addrs->ext_mem_2_ipu_addr; in sdma_get_pc()
1030 sdmac->pc_from_device = per_2_emi; in sdma_get_pc()
1031 sdmac->pc_to_device = emi_2_per; in sdma_get_pc()
1032 sdmac->device_to_device = per_2_per; in sdma_get_pc()
1033 sdmac->pc_to_pc = emi_2_emi; in sdma_get_pc()
1038 struct sdma_engine *sdma = sdmac->sdma; in sdma_load_context()
1039 int channel = sdmac->channel; in sdma_load_context()
1041 struct sdma_context_data *context = sdma->context; in sdma_load_context()
1042 struct sdma_buffer_descriptor *bd0 = sdma->bd0; in sdma_load_context()
1046 if (sdmac->direction == DMA_DEV_TO_MEM) in sdma_load_context()
1047 load_address = sdmac->pc_from_device; in sdma_load_context()
1048 else if (sdmac->direction == DMA_DEV_TO_DEV) in sdma_load_context()
1049 load_address = sdmac->device_to_device; in sdma_load_context()
1050 else if (sdmac->direction == DMA_MEM_TO_MEM) in sdma_load_context()
1051 load_address = sdmac->pc_to_pc; in sdma_load_context()
1053 load_address = sdmac->pc_to_device; in sdma_load_context()
1058 dev_dbg(sdma->dev, "load_address = %d\n", load_address); in sdma_load_context()
1059 dev_dbg(sdma->dev, "wml = 0x%08x\n", (u32)sdmac->watermark_level); in sdma_load_context()
1060 dev_dbg(sdma->dev, "shp_addr = 0x%08x\n", sdmac->shp_addr); in sdma_load_context()
1061 dev_dbg(sdma->dev, "per_addr = 0x%08x\n", sdmac->per_addr); in sdma_load_context()
1062 dev_dbg(sdma->dev, "event_mask0 = 0x%08x\n", (u32)sdmac->event_mask[0]); in sdma_load_context()
1063 dev_dbg(sdma->dev, "event_mask1 = 0x%08x\n", (u32)sdmac->event_mask[1]); in sdma_load_context()
1065 spin_lock_irqsave(&sdma->channel_0_lock, flags); in sdma_load_context()
1068 context->channel_state.pc = load_address; in sdma_load_context()
1073 context->gReg[0] = sdmac->event_mask[1]; in sdma_load_context()
1074 context->gReg[1] = sdmac->event_mask[0]; in sdma_load_context()
1075 context->gReg[2] = sdmac->per_addr; in sdma_load_context()
1076 context->gReg[6] = sdmac->shp_addr; in sdma_load_context()
1077 context->gReg[7] = sdmac->watermark_level; in sdma_load_context()
1079 bd0->mode.command = C0_SETDM; in sdma_load_context()
1080 bd0->mode.status = BD_DONE | BD_WRAP | BD_EXTD; in sdma_load_context()
1081 bd0->mode.count = sizeof(*context) / 4; in sdma_load_context()
1082 bd0->buffer_addr = sdma->context_phys; in sdma_load_context()
1083 bd0->ext_buffer_addr = 2048 + (sizeof(*context) / 4) * channel; in sdma_load_context()
1086 spin_unlock_irqrestore(&sdma->channel_0_lock, flags); in sdma_load_context()
1099 struct sdma_engine *sdma = sdmac->sdma; in sdma_disable_channel()
1100 int channel = sdmac->channel; in sdma_disable_channel()
1102 writel_relaxed(BIT(channel), sdma->regs + SDMA_H_STATSTOP); in sdma_disable_channel()
1103 sdmac->status = DMA_ERROR; in sdma_disable_channel()
1119 vchan_dma_desc_free_list(&sdmac->vc, &sdmac->terminated); in sdma_channel_terminate_work()
1127 spin_lock_irqsave(&sdmac->vc.lock, flags); in sdma_terminate_all()
1131 if (sdmac->desc) { in sdma_terminate_all()
1132 vchan_terminate_vdesc(&sdmac->desc->vd); in sdma_terminate_all()
1139 vchan_get_all_descriptors(&sdmac->vc, &sdmac->terminated); in sdma_terminate_all()
1140 sdmac->desc = NULL; in sdma_terminate_all()
1141 schedule_work(&sdmac->terminate_worker); in sdma_terminate_all()
1144 spin_unlock_irqrestore(&sdmac->vc.lock, flags); in sdma_terminate_all()
1153 vchan_synchronize(&sdmac->vc); in sdma_channel_synchronize()
1155 flush_work(&sdmac->terminate_worker); in sdma_channel_synchronize()
1160 struct sdma_engine *sdma = sdmac->sdma; in sdma_set_watermarklevel_for_p2p()
1162 int lwml = sdmac->watermark_level & SDMA_WATERMARK_LEVEL_LWML; in sdma_set_watermarklevel_for_p2p()
1163 int hwml = (sdmac->watermark_level & SDMA_WATERMARK_LEVEL_HWML) >> 16; in sdma_set_watermarklevel_for_p2p()
1165 set_bit(sdmac->event_id0 % 32, &sdmac->event_mask[1]); in sdma_set_watermarklevel_for_p2p()
1166 set_bit(sdmac->event_id1 % 32, &sdmac->event_mask[0]); in sdma_set_watermarklevel_for_p2p()
1168 if (sdmac->event_id0 > 31) in sdma_set_watermarklevel_for_p2p()
1169 sdmac->watermark_level |= SDMA_WATERMARK_LEVEL_LWE; in sdma_set_watermarklevel_for_p2p()
1171 if (sdmac->event_id1 > 31) in sdma_set_watermarklevel_for_p2p()
1172 sdmac->watermark_level |= SDMA_WATERMARK_LEVEL_HWE; in sdma_set_watermarklevel_for_p2p()
1180 sdmac->watermark_level &= ~(SDMA_WATERMARK_LEVEL_LWML | in sdma_set_watermarklevel_for_p2p()
1182 sdmac->watermark_level |= hwml; in sdma_set_watermarklevel_for_p2p()
1183 sdmac->watermark_level |= lwml << 16; in sdma_set_watermarklevel_for_p2p()
1184 swap(sdmac->event_mask[0], sdmac->event_mask[1]); in sdma_set_watermarklevel_for_p2p()
1187 if (sdmac->per_address2 >= sdma->spba_start_addr && in sdma_set_watermarklevel_for_p2p()
1188 sdmac->per_address2 <= sdma->spba_end_addr) in sdma_set_watermarklevel_for_p2p()
1189 sdmac->watermark_level |= SDMA_WATERMARK_LEVEL_SP; in sdma_set_watermarklevel_for_p2p()
1191 if (sdmac->per_address >= sdma->spba_start_addr && in sdma_set_watermarklevel_for_p2p()
1192 sdmac->per_address <= sdma->spba_end_addr) in sdma_set_watermarklevel_for_p2p()
1193 sdmac->watermark_level |= SDMA_WATERMARK_LEVEL_DP; in sdma_set_watermarklevel_for_p2p()
1195 sdmac->watermark_level |= SDMA_WATERMARK_LEVEL_CONT; in sdma_set_watermarklevel_for_p2p()
1204 sdmac->event_mask[0] = 0; in sdma_config_channel()
1205 sdmac->event_mask[1] = 0; in sdma_config_channel()
1206 sdmac->shp_addr = 0; in sdma_config_channel()
1207 sdmac->per_addr = 0; in sdma_config_channel()
1209 switch (sdmac->peripheral_type) { in sdma_config_channel()
1221 sdma_get_pc(sdmac, sdmac->peripheral_type); in sdma_config_channel()
1223 if ((sdmac->peripheral_type != IMX_DMATYPE_MEMORY) && in sdma_config_channel()
1224 (sdmac->peripheral_type != IMX_DMATYPE_DSP)) { in sdma_config_channel()
1226 if (sdmac->event_id1) { in sdma_config_channel()
1227 if (sdmac->peripheral_type == IMX_DMATYPE_ASRC_SP || in sdma_config_channel()
1228 sdmac->peripheral_type == IMX_DMATYPE_ASRC) in sdma_config_channel()
1231 __set_bit(sdmac->event_id0, sdmac->event_mask); in sdma_config_channel()
1234 sdmac->shp_addr = sdmac->per_address; in sdma_config_channel()
1235 sdmac->per_addr = sdmac->per_address2; in sdma_config_channel()
1237 sdmac->watermark_level = 0; /* FIXME: M3_BASE_ADDRESS */ in sdma_config_channel()
1246 struct sdma_engine *sdma = sdmac->sdma; in sdma_set_channel_priority()
1247 int channel = sdmac->channel; in sdma_set_channel_priority()
1251 return -EINVAL; in sdma_set_channel_priority()
1254 writel_relaxed(priority, sdma->regs + SDMA_CHNPRI_0 + 4 * channel); in sdma_set_channel_priority()
1261 int ret = -EBUSY; in sdma_request_channel0()
1263 sdma->bd0 = dma_alloc_coherent(sdma->dev, PAGE_SIZE, &sdma->bd0_phys, in sdma_request_channel0()
1265 if (!sdma->bd0) { in sdma_request_channel0()
1266 ret = -ENOMEM; in sdma_request_channel0()
1270 sdma->channel_control[0].base_bd_ptr = sdma->bd0_phys; in sdma_request_channel0()
1271 sdma->channel_control[0].current_bd_ptr = sdma->bd0_phys; in sdma_request_channel0()
1273 sdma_set_channel_priority(&sdma->channel[0], MXC_SDMA_DEFAULT_PRIORITY); in sdma_request_channel0()
1283 u32 bd_size = desc->num_bd * sizeof(struct sdma_buffer_descriptor); in sdma_alloc_bd()
1286 desc->bd = dma_alloc_coherent(desc->sdmac->sdma->dev, bd_size, in sdma_alloc_bd()
1287 &desc->bd_phys, GFP_NOWAIT); in sdma_alloc_bd()
1288 if (!desc->bd) { in sdma_alloc_bd()
1289 ret = -ENOMEM; in sdma_alloc_bd()
1298 u32 bd_size = desc->num_bd * sizeof(struct sdma_buffer_descriptor); in sdma_free_bd()
1300 dma_free_coherent(desc->sdmac->sdma->dev, bd_size, desc->bd, in sdma_free_bd()
1301 desc->bd_phys); in sdma_free_bd()
1315 struct imx_dma_data *data = chan->private; in sdma_alloc_chan_resources()
1320 * MEMCPY may never setup chan->private by filter function such as in sdma_alloc_chan_resources()
1322 * Please note in any other slave case, you have to setup chan->private in sdma_alloc_chan_resources()
1329 dev_dbg(sdmac->sdma->dev, "MEMCPY in case?\n"); in sdma_alloc_chan_resources()
1339 switch (data->priority) { in sdma_alloc_chan_resources()
1352 sdmac->peripheral_type = data->peripheral_type; in sdma_alloc_chan_resources()
1353 sdmac->event_id0 = data->dma_request; in sdma_alloc_chan_resources()
1354 sdmac->event_id1 = data->dma_request2; in sdma_alloc_chan_resources()
1356 ret = clk_enable(sdmac->sdma->clk_ipg); in sdma_alloc_chan_resources()
1359 ret = clk_enable(sdmac->sdma->clk_ahb); in sdma_alloc_chan_resources()
1370 clk_disable(sdmac->sdma->clk_ahb); in sdma_alloc_chan_resources()
1372 clk_disable(sdmac->sdma->clk_ipg); in sdma_alloc_chan_resources()
1379 struct sdma_engine *sdma = sdmac->sdma; in sdma_free_chan_resources()
1385 sdma_event_disable(sdmac, sdmac->event_id0); in sdma_free_chan_resources()
1386 if (sdmac->event_id1) in sdma_free_chan_resources()
1387 sdma_event_disable(sdmac, sdmac->event_id1); in sdma_free_chan_resources()
1389 sdmac->event_id0 = 0; in sdma_free_chan_resources()
1390 sdmac->event_id1 = 0; in sdma_free_chan_resources()
1394 clk_disable(sdma->clk_ipg); in sdma_free_chan_resources()
1395 clk_disable(sdma->clk_ahb); in sdma_free_chan_resources()
1403 if (!sdmac->sdma->fw_loaded && sdmac->is_ram_script) { in sdma_transfer_init()
1404 dev_warn_once(sdmac->sdma->dev, "sdma firmware not ready!\n"); in sdma_transfer_init()
1412 sdmac->status = DMA_IN_PROGRESS; in sdma_transfer_init()
1413 sdmac->direction = direction; in sdma_transfer_init()
1414 sdmac->flags = 0; in sdma_transfer_init()
1416 desc->chn_count = 0; in sdma_transfer_init()
1417 desc->chn_real_count = 0; in sdma_transfer_init()
1418 desc->buf_tail = 0; in sdma_transfer_init()
1419 desc->buf_ptail = 0; in sdma_transfer_init()
1420 desc->sdmac = sdmac; in sdma_transfer_init()
1421 desc->num_bd = bds; in sdma_transfer_init()
1446 struct sdma_engine *sdma = sdmac->sdma; in sdma_prep_memcpy()
1447 int channel = sdmac->channel; in sdma_prep_memcpy()
1456 dev_dbg(sdma->dev, "memcpy: %pad->%pad, len=%zu, channel=%d.\n", in sdma_prep_memcpy()
1466 bd = &desc->bd[i]; in sdma_prep_memcpy()
1467 bd->buffer_addr = dma_src; in sdma_prep_memcpy()
1468 bd->ext_buffer_addr = dma_dst; in sdma_prep_memcpy()
1469 bd->mode.count = count; in sdma_prep_memcpy()
1470 desc->chn_count += count; in sdma_prep_memcpy()
1471 bd->mode.command = 0; in sdma_prep_memcpy()
1475 len -= count; in sdma_prep_memcpy()
1486 dev_dbg(sdma->dev, "entry %d: count: %zd dma: 0x%x %s%s\n", in sdma_prep_memcpy()
1487 i, count, bd->buffer_addr, in sdma_prep_memcpy()
1491 bd->mode.status = param; in sdma_prep_memcpy()
1494 return vchan_tx_prep(&sdmac->vc, &desc->vd, flags); in sdma_prep_memcpy()
1503 struct sdma_engine *sdma = sdmac->sdma; in sdma_prep_slave_sg()
1505 int channel = sdmac->channel; in sdma_prep_slave_sg()
1509 sdma_config_write(chan, &sdmac->slave_config, direction); in sdma_prep_slave_sg()
1515 dev_dbg(sdma->dev, "setting up %d entries for channel %d.\n", in sdma_prep_slave_sg()
1519 struct sdma_buffer_descriptor *bd = &desc->bd[i]; in sdma_prep_slave_sg()
1522 bd->buffer_addr = sg->dma_address; in sdma_prep_slave_sg()
1527 dev_err(sdma->dev, "SDMA channel %d: maximum bytes for sg entry exceeded: %d > %d\n", in sdma_prep_slave_sg()
1532 bd->mode.count = count; in sdma_prep_slave_sg()
1533 desc->chn_count += count; in sdma_prep_slave_sg()
1535 if (sdmac->word_size > DMA_SLAVE_BUSWIDTH_4_BYTES) in sdma_prep_slave_sg()
1538 switch (sdmac->word_size) { in sdma_prep_slave_sg()
1540 bd->mode.command = 0; in sdma_prep_slave_sg()
1541 if (count & 3 || sg->dma_address & 3) in sdma_prep_slave_sg()
1545 bd->mode.command = 2; in sdma_prep_slave_sg()
1546 if (count & 1 || sg->dma_address & 1) in sdma_prep_slave_sg()
1550 bd->mode.command = 1; in sdma_prep_slave_sg()
1564 dev_dbg(sdma->dev, "entry %d: count: %d dma: %#llx %s%s\n", in sdma_prep_slave_sg()
1565 i, count, (u64)sg->dma_address, in sdma_prep_slave_sg()
1569 bd->mode.status = param; in sdma_prep_slave_sg()
1572 return vchan_tx_prep(&sdmac->vc, &desc->vd, flags); in sdma_prep_slave_sg()
1577 sdmac->status = DMA_ERROR; in sdma_prep_slave_sg()
1587 struct sdma_engine *sdma = sdmac->sdma; in sdma_prep_dma_cyclic()
1589 int channel = sdmac->channel; in sdma_prep_dma_cyclic()
1593 dev_dbg(sdma->dev, "%s channel: %d\n", __func__, channel); in sdma_prep_dma_cyclic()
1595 sdma_config_write(chan, &sdmac->slave_config, direction); in sdma_prep_dma_cyclic()
1601 desc->period_len = period_len; in sdma_prep_dma_cyclic()
1603 sdmac->flags |= IMX_DMA_SG_LOOP; in sdma_prep_dma_cyclic()
1606 dev_err(sdma->dev, "SDMA channel %d: maximum period size exceeded: %zu > %d\n", in sdma_prep_dma_cyclic()
1612 struct sdma_buffer_descriptor *bd = &desc->bd[i]; in sdma_prep_dma_cyclic()
1615 bd->buffer_addr = dma_addr; in sdma_prep_dma_cyclic()
1617 bd->mode.count = period_len; in sdma_prep_dma_cyclic()
1619 if (sdmac->word_size > DMA_SLAVE_BUSWIDTH_4_BYTES) in sdma_prep_dma_cyclic()
1621 if (sdmac->word_size == DMA_SLAVE_BUSWIDTH_4_BYTES) in sdma_prep_dma_cyclic()
1622 bd->mode.command = 0; in sdma_prep_dma_cyclic()
1624 bd->mode.command = sdmac->word_size; in sdma_prep_dma_cyclic()
1630 dev_dbg(sdma->dev, "entry %d: count: %zu dma: %#llx %s%s\n", in sdma_prep_dma_cyclic()
1635 bd->mode.status = param; in sdma_prep_dma_cyclic()
1643 return vchan_tx_prep(&sdmac->vc, &desc->vd, flags); in sdma_prep_dma_cyclic()
1648 sdmac->status = DMA_ERROR; in sdma_prep_dma_cyclic()
1659 sdmac->per_address = dmaengine_cfg->src_addr; in sdma_config_write()
1660 sdmac->watermark_level = dmaengine_cfg->src_maxburst * in sdma_config_write()
1661 dmaengine_cfg->src_addr_width; in sdma_config_write()
1662 sdmac->word_size = dmaengine_cfg->src_addr_width; in sdma_config_write()
1664 sdmac->per_address2 = dmaengine_cfg->src_addr; in sdma_config_write()
1665 sdmac->per_address = dmaengine_cfg->dst_addr; in sdma_config_write()
1666 sdmac->watermark_level = dmaengine_cfg->src_maxburst & in sdma_config_write()
1668 sdmac->watermark_level |= (dmaengine_cfg->dst_maxburst << 16) & in sdma_config_write()
1670 sdmac->word_size = dmaengine_cfg->dst_addr_width; in sdma_config_write()
1672 sdmac->per_address = dmaengine_cfg->dst_addr; in sdma_config_write()
1673 sdmac->watermark_level = dmaengine_cfg->dst_maxburst * in sdma_config_write()
1674 dmaengine_cfg->dst_addr_width; in sdma_config_write()
1675 sdmac->word_size = dmaengine_cfg->dst_addr_width; in sdma_config_write()
1677 sdmac->direction = direction; in sdma_config_write()
1686 memcpy(&sdmac->slave_config, dmaengine_cfg, sizeof(*dmaengine_cfg)); in sdma_config()
1689 if (sdmac->event_id0 >= sdmac->sdma->drvdata->num_events) in sdma_config()
1690 return -EINVAL; in sdma_config()
1691 sdma_event_enable(sdmac, sdmac->event_id0); in sdma_config()
1693 if (sdmac->event_id1) { in sdma_config()
1694 if (sdmac->event_id1 >= sdmac->sdma->drvdata->num_events) in sdma_config()
1695 return -EINVAL; in sdma_config()
1696 sdma_event_enable(sdmac, sdmac->event_id1); in sdma_config()
1717 spin_lock_irqsave(&sdmac->vc.lock, flags); in sdma_tx_status()
1719 vd = vchan_find_desc(&sdmac->vc, cookie); in sdma_tx_status()
1721 desc = to_sdma_desc(&vd->tx); in sdma_tx_status()
1722 else if (sdmac->desc && sdmac->desc->vd.tx.cookie == cookie) in sdma_tx_status()
1723 desc = sdmac->desc; in sdma_tx_status()
1726 if (sdmac->flags & IMX_DMA_SG_LOOP) in sdma_tx_status()
1727 residue = (desc->num_bd - desc->buf_ptail) * in sdma_tx_status()
1728 desc->period_len - desc->chn_real_count; in sdma_tx_status()
1730 residue = desc->chn_count - desc->chn_real_count; in sdma_tx_status()
1735 spin_unlock_irqrestore(&sdmac->vc.lock, flags); in sdma_tx_status()
1737 dma_set_tx_state(txstate, chan->completed_cookie, chan->cookie, in sdma_tx_status()
1740 return sdmac->status; in sdma_tx_status()
1748 spin_lock_irqsave(&sdmac->vc.lock, flags); in sdma_issue_pending()
1749 if (vchan_issue_pending(&sdmac->vc) && !sdmac->desc) in sdma_issue_pending()
1751 spin_unlock_irqrestore(&sdmac->vc.lock, flags); in sdma_issue_pending()
1763 s32 *saddr_arr = (u32 *)sdma->script_addrs; in sdma_add_scripts()
1767 if (!sdma->script_number) in sdma_add_scripts()
1768 sdma->script_number = SDMA_SCRIPT_ADDRS_ARRAY_SIZE_V1; in sdma_add_scripts()
1770 if (sdma->script_number > sizeof(struct sdma_script_start_addrs) in sdma_add_scripts()
1772 dev_err(sdma->dev, in sdma_add_scripts()
1774 sdma->script_number); in sdma_add_scripts()
1778 for (i = 0; i < sdma->script_number; i++) in sdma_add_scripts()
1789 if (addr->uart_2_mcu_addr) in sdma_add_scripts()
1790 sdma->script_addrs->uart_2_mcu_addr = addr->uart_2_mcu_addr; in sdma_add_scripts()
1791 if (addr->uartsh_2_mcu_addr) in sdma_add_scripts()
1792 sdma->script_addrs->uartsh_2_mcu_addr = addr->uartsh_2_mcu_addr; in sdma_add_scripts()
1804 dev_info(sdma->dev, "external firmware not found, using ROM firmware\n"); in sdma_load_firmware()
1809 if (fw->size < sizeof(*header)) in sdma_load_firmware()
1812 header = (struct sdma_firmware_header *)fw->data; in sdma_load_firmware()
1814 if (header->magic != SDMA_FIRMWARE_MAGIC) in sdma_load_firmware()
1816 if (header->ram_code_start + header->ram_code_size > fw->size) in sdma_load_firmware()
1818 switch (header->version_major) { in sdma_load_firmware()
1820 sdma->script_number = SDMA_SCRIPT_ADDRS_ARRAY_SIZE_V1; in sdma_load_firmware()
1823 sdma->script_number = SDMA_SCRIPT_ADDRS_ARRAY_SIZE_V2; in sdma_load_firmware()
1826 sdma->script_number = SDMA_SCRIPT_ADDRS_ARRAY_SIZE_V3; in sdma_load_firmware()
1829 sdma->script_number = SDMA_SCRIPT_ADDRS_ARRAY_SIZE_V4; in sdma_load_firmware()
1832 dev_err(sdma->dev, "unknown firmware version\n"); in sdma_load_firmware()
1836 addr = (void *)header + header->script_addrs_start; in sdma_load_firmware()
1837 ram_code = (void *)header + header->ram_code_start; in sdma_load_firmware()
1839 clk_enable(sdma->clk_ipg); in sdma_load_firmware()
1840 clk_enable(sdma->clk_ahb); in sdma_load_firmware()
1843 header->ram_code_size, in sdma_load_firmware()
1844 addr->ram_code_start_addr); in sdma_load_firmware()
1845 clk_disable(sdma->clk_ipg); in sdma_load_firmware()
1846 clk_disable(sdma->clk_ahb); in sdma_load_firmware()
1850 sdma->fw_loaded = true; in sdma_load_firmware()
1852 dev_info(sdma->dev, "loaded firmware %d.%d\n", in sdma_load_firmware()
1853 header->version_major, in sdma_load_firmware()
1854 header->version_minor); in sdma_load_firmware()
1864 struct device_node *np = sdma->dev->of_node; in sdma_event_remap()
1868 char propname[] = "fsl,sdma-event-remap"; in sdma_event_remap()
1876 num_map = event_remap ? (event_remap->length / sizeof(u32)) : 0; in sdma_event_remap()
1878 dev_dbg(sdma->dev, "no event needs to be remapped\n"); in sdma_event_remap()
1881 dev_err(sdma->dev, "the property %s must modulo %d\n", in sdma_event_remap()
1883 ret = -EINVAL; in sdma_event_remap()
1889 dev_err(sdma->dev, "failed to get gpr regmap\n"); in sdma_event_remap()
1897 dev_err(sdma->dev, "failed to read property %s index %d\n", in sdma_event_remap()
1904 dev_err(sdma->dev, "failed to read property %s index %d\n", in sdma_event_remap()
1911 dev_err(sdma->dev, "failed to read property %s index %d\n", in sdma_event_remap()
1932 FW_ACTION_UEVENT, fw_name, sdma->dev, in sdma_get_firmware()
1943 ret = clk_enable(sdma->clk_ipg); in sdma_init()
1946 ret = clk_enable(sdma->clk_ahb); in sdma_init()
1950 if (sdma->drvdata->check_ratio && in sdma_init()
1951 (clk_get_rate(sdma->clk_ahb) == clk_get_rate(sdma->clk_ipg))) in sdma_init()
1952 sdma->clk_ratio = 1; in sdma_init()
1955 writel_relaxed(0, sdma->regs + SDMA_H_C0PTR); in sdma_init()
1957 sdma->channel_control = dma_alloc_coherent(sdma->dev, in sdma_init()
1962 if (!sdma->channel_control) { in sdma_init()
1963 ret = -ENOMEM; in sdma_init()
1967 sdma->context = (void *)sdma->channel_control + in sdma_init()
1969 sdma->context_phys = ccb_phys + in sdma_init()
1973 for (i = 0; i < sdma->drvdata->num_events; i++) in sdma_init()
1974 writel_relaxed(0, sdma->regs + chnenbl_ofs(sdma, i)); in sdma_init()
1978 writel_relaxed(0, sdma->regs + SDMA_CHNPRI_0 + i * 4); in sdma_init()
1984 sdma_config_ownership(&sdma->channel[0], false, true, false); in sdma_init()
1987 writel_relaxed(0x4050, sdma->regs + SDMA_CHN0ADDR); in sdma_init()
1990 if (sdma->clk_ratio) in sdma_init()
1991 writel_relaxed(SDMA_H_CONFIG_ACR, sdma->regs + SDMA_H_CONFIG); in sdma_init()
1993 writel_relaxed(0, sdma->regs + SDMA_H_CONFIG); in sdma_init()
1995 writel_relaxed(ccb_phys, sdma->regs + SDMA_H_C0PTR); in sdma_init()
1998 sdma_set_channel_priority(&sdma->channel[0], 7); in sdma_init()
2000 clk_disable(sdma->clk_ipg); in sdma_init()
2001 clk_disable(sdma->clk_ahb); in sdma_init()
2006 clk_disable(sdma->clk_ahb); in sdma_init()
2008 clk_disable(sdma->clk_ipg); in sdma_init()
2009 dev_err(sdma->dev, "initialisation failed with %d\n", ret); in sdma_init()
2021 sdmac->data = *data; in sdma_filter_fn()
2022 chan->private = &sdmac->data; in sdma_filter_fn()
2030 struct sdma_engine *sdma = ofdma->of_dma_data; in sdma_xlate()
2031 dma_cap_mask_t mask = sdma->dma_device.cap_mask; in sdma_xlate()
2034 if (dma_spec->args_count != 3) in sdma_xlate()
2037 data.dma_request = dma_spec->args[0]; in sdma_xlate()
2038 data.peripheral_type = dma_spec->args[1]; in sdma_xlate()
2039 data.priority = dma_spec->args[2]; in sdma_xlate()
2043 * chan->private will point to the imx_dma_data, and in in sdma_xlate()
2045 * be set to sdmac->event_id1. in sdma_xlate()
2050 ofdma->of_node); in sdma_xlate()
2055 struct device_node *np = pdev->dev.of_node; in sdma_probe()
2066 ret = dma_coerce_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(32)); in sdma_probe()
2070 sdma = devm_kzalloc(&pdev->dev, sizeof(*sdma), GFP_KERNEL); in sdma_probe()
2072 return -ENOMEM; in sdma_probe()
2074 spin_lock_init(&sdma->channel_0_lock); in sdma_probe()
2076 sdma->dev = &pdev->dev; in sdma_probe()
2077 sdma->drvdata = of_device_get_match_data(sdma->dev); in sdma_probe()
2084 sdma->regs = devm_ioremap_resource(&pdev->dev, iores); in sdma_probe()
2085 if (IS_ERR(sdma->regs)) in sdma_probe()
2086 return PTR_ERR(sdma->regs); in sdma_probe()
2088 sdma->clk_ipg = devm_clk_get(&pdev->dev, "ipg"); in sdma_probe()
2089 if (IS_ERR(sdma->clk_ipg)) in sdma_probe()
2090 return PTR_ERR(sdma->clk_ipg); in sdma_probe()
2092 sdma->clk_ahb = devm_clk_get(&pdev->dev, "ahb"); in sdma_probe()
2093 if (IS_ERR(sdma->clk_ahb)) in sdma_probe()
2094 return PTR_ERR(sdma->clk_ahb); in sdma_probe()
2096 ret = clk_prepare(sdma->clk_ipg); in sdma_probe()
2100 ret = clk_prepare(sdma->clk_ahb); in sdma_probe()
2104 ret = devm_request_irq(&pdev->dev, irq, sdma_int_handler, 0, "sdma", in sdma_probe()
2109 sdma->irq = irq; in sdma_probe()
2111 sdma->script_addrs = kzalloc(sizeof(*sdma->script_addrs), GFP_KERNEL); in sdma_probe()
2112 if (!sdma->script_addrs) { in sdma_probe()
2113 ret = -ENOMEM; in sdma_probe()
2118 saddr_arr = (s32 *)sdma->script_addrs; in sdma_probe()
2119 for (i = 0; i < sizeof(*sdma->script_addrs) / sizeof(s32); i++) in sdma_probe()
2120 saddr_arr[i] = -EINVAL; in sdma_probe()
2122 dma_cap_set(DMA_SLAVE, sdma->dma_device.cap_mask); in sdma_probe()
2123 dma_cap_set(DMA_CYCLIC, sdma->dma_device.cap_mask); in sdma_probe()
2124 dma_cap_set(DMA_MEMCPY, sdma->dma_device.cap_mask); in sdma_probe()
2126 INIT_LIST_HEAD(&sdma->dma_device.channels); in sdma_probe()
2129 struct sdma_channel *sdmac = &sdma->channel[i]; in sdma_probe()
2131 sdmac->sdma = sdma; in sdma_probe()
2133 sdmac->channel = i; in sdma_probe()
2134 sdmac->vc.desc_free = sdma_desc_free; in sdma_probe()
2135 INIT_LIST_HEAD(&sdmac->terminated); in sdma_probe()
2136 INIT_WORK(&sdmac->terminate_worker, in sdma_probe()
2144 vchan_init(&sdmac->vc, &sdma->dma_device); in sdma_probe()
2155 if (sdma->drvdata->script_addrs) in sdma_probe()
2156 sdma_add_scripts(sdma, sdma->drvdata->script_addrs); in sdma_probe()
2158 sdma->dma_device.dev = &pdev->dev; in sdma_probe()
2160 sdma->dma_device.device_alloc_chan_resources = sdma_alloc_chan_resources; in sdma_probe()
2161 sdma->dma_device.device_free_chan_resources = sdma_free_chan_resources; in sdma_probe()
2162 sdma->dma_device.device_tx_status = sdma_tx_status; in sdma_probe()
2163 sdma->dma_device.device_prep_slave_sg = sdma_prep_slave_sg; in sdma_probe()
2164 sdma->dma_device.device_prep_dma_cyclic = sdma_prep_dma_cyclic; in sdma_probe()
2165 sdma->dma_device.device_config = sdma_config; in sdma_probe()
2166 sdma->dma_device.device_terminate_all = sdma_terminate_all; in sdma_probe()
2167 sdma->dma_device.device_synchronize = sdma_channel_synchronize; in sdma_probe()
2168 sdma->dma_device.src_addr_widths = SDMA_DMA_BUSWIDTHS; in sdma_probe()
2169 sdma->dma_device.dst_addr_widths = SDMA_DMA_BUSWIDTHS; in sdma_probe()
2170 sdma->dma_device.directions = SDMA_DMA_DIRECTIONS; in sdma_probe()
2171 sdma->dma_device.residue_granularity = DMA_RESIDUE_GRANULARITY_SEGMENT; in sdma_probe()
2172 sdma->dma_device.device_prep_dma_memcpy = sdma_prep_memcpy; in sdma_probe()
2173 sdma->dma_device.device_issue_pending = sdma_issue_pending; in sdma_probe()
2174 sdma->dma_device.copy_align = 2; in sdma_probe()
2175 dma_set_max_seg_size(sdma->dma_device.dev, SDMA_BD_MAX_CNT); in sdma_probe()
2179 ret = dma_async_device_register(&sdma->dma_device); in sdma_probe()
2181 dev_err(&pdev->dev, "unable to register\n"); in sdma_probe()
2188 dev_err(&pdev->dev, "failed to register controller\n"); in sdma_probe()
2192 spba_bus = of_find_compatible_node(NULL, NULL, "fsl,spba-bus"); in sdma_probe()
2195 sdma->spba_start_addr = spba_res.start; in sdma_probe()
2196 sdma->spba_end_addr = spba_res.end; in sdma_probe()
2206 ret = of_property_read_string(np, "fsl,sdma-ram-script-name", in sdma_probe()
2209 dev_warn(&pdev->dev, "failed to get firmware name\n"); in sdma_probe()
2213 dev_warn(&pdev->dev, "failed to get firmware from device tree\n"); in sdma_probe()
2219 dma_async_device_unregister(&sdma->dma_device); in sdma_probe()
2221 kfree(sdma->script_addrs); in sdma_probe()
2223 clk_unprepare(sdma->clk_ahb); in sdma_probe()
2225 clk_unprepare(sdma->clk_ipg); in sdma_probe()
2234 devm_free_irq(&pdev->dev, sdma->irq, sdma); in sdma_remove()
2235 dma_async_device_unregister(&sdma->dma_device); in sdma_remove()
2236 kfree(sdma->script_addrs); in sdma_remove()
2237 clk_unprepare(sdma->clk_ahb); in sdma_remove()
2238 clk_unprepare(sdma->clk_ipg); in sdma_remove()
2241 struct sdma_channel *sdmac = &sdma->channel[i]; in sdma_remove()
2243 tasklet_kill(&sdmac->vc.task); in sdma_remove()
2244 sdma_free_chan_resources(&sdmac->vc.chan); in sdma_remove()
2253 .name = "imx-sdma",
2265 MODULE_FIRMWARE("imx/sdma/sdma-imx6q.bin");
2268 MODULE_FIRMWARE("imx/sdma/sdma-imx7d.bin");