Lines Matching +full:broken +full:- +full:turn +full:- +full:around
1 // SPDX-License-Identifier: GPL-2.0
19 #include <asm/intel-family.h>
64 * Processors which have self-snooping capability can handle conflicting
72 switch (c->x86_model) { in check_memory_type_self_snoop_errata()
104 if (c->x86 != 6) in probe_xeon_phi_r3mwait()
106 switch (c->x86_model) { in probe_xeon_phi_r3mwait()
126 * Early microcode releases for the Spectre v2 mitigation were broken.
128 * - https://newsroom.intel.com/wp-content/uploads/sites/11/2018/03/microcode-update-guidance.pdf
129 * - https://kb.vmware.com/s/article/52345
130 * - Microcode revisions observed in the wild
131 * - Release note from 20180108 microcode release
173 if (c->x86 != 6) in bad_spectre_microcode()
177 if (c->x86_model == spectre_bad_microcodes[i].model && in bad_spectre_microcode()
178 c->x86_stepping == spectre_bad_microcodes[i].stepping) in bad_spectre_microcode()
179 return (c->microcode <= spectre_bad_microcodes[i].microcode); in bad_spectre_microcode()
189 if (c->x86 > 6 || (c->x86 == 6 && c->x86_model >= 0xd)) { in early_init_intel()
192 c->cpuid_level = cpuid_eax(0); in early_init_intel()
197 if ((c->x86 == 0xf && c->x86_model >= 0x03) || in early_init_intel()
198 (c->x86 == 0x6 && c->x86_model >= 0x0e)) in early_init_intel()
201 if (c->x86 >= 6 && !cpu_has(c, X86_FEATURE_IA64)) in early_init_intel()
202 c->microcode = intel_get_microcode_revision(); in early_init_intel()
209 pr_warn("Intel Spectre v2 broken microcode detected; disabling Speculation Control\n"); in early_init_intel()
224 * a large page. This is worked around in microcode, but we in early_init_intel()
228 if (c->x86 == 6 && c->x86_model == 0x1c && c->x86_stepping <= 2 && in early_init_intel()
229 c->microcode < 0x20e) { in early_init_intel()
238 if (c->x86 == 15 && c->x86_cache_alignment == 64) in early_init_intel()
239 c->x86_cache_alignment = 128; in early_init_intel()
243 if (c->x86 == 0xF && c->x86_model == 0x3 in early_init_intel()
244 && (c->x86_stepping == 0x3 || c->x86_stepping == 0x4)) in early_init_intel()
245 c->x86_phys_bits = 36; in early_init_intel()
248 * c->x86_power is 8000_0007 edx. Bit 8 is TSC runs at constant rate in early_init_intel()
249 * with P/T states and does not stop in deep C-states. in early_init_intel()
252 * cabinets - we turn it off in that case explicitly.) in early_init_intel()
254 if (c->x86_power & (1 << 8)) { in early_init_intel()
260 if (c->x86 == 6) { in early_init_intel()
261 switch (c->x86_model) { in early_init_intel()
283 if (c->x86 == 6 && c->x86_model < 15) in early_init_intel()
290 if (c->x86 > 6 || (c->x86 == 6 && c->x86_model >= 0xd)) { in early_init_intel()
309 if (c->x86 == 5 && c->x86_model == 9) { in early_init_intel()
314 if (c->cpuid_level >= 0x00000001) { in early_init_intel()
324 c->x86_coreid_bits = get_count_order((ebx >> 16) & 0xff); in early_init_intel()
365 if (!c->cpu_index) in intel_smp_check()
371 if (c->x86 == 5 && in intel_smp_check()
372 c->x86_stepping >= 1 && c->x86_stepping <= 4 && in intel_smp_check()
373 c->x86_model <= 3) { in intel_smp_check()
400 if (c->x86 == 5 && c->x86_model < 9) { in intel_workarounds()
405 pr_notice("Intel Pentium with F0 0F bug - workaround enabled.\n"); in intel_workarounds()
415 if ((c->x86<<8 | c->x86_model<<4 | c->x86_stepping) < 0x633) in intel_workarounds()
433 if ((c->x86 == 15) && (c->x86_model == 1) && (c->x86_stepping == 1)) { in intel_workarounds()
447 if (boot_cpu_has(X86_FEATURE_APIC) && (c->x86<<8 | c->x86_model<<4) == 0x520 && in intel_workarounds()
448 (c->x86_stepping < 0x6 || c->x86_stepping == 0xb)) in intel_workarounds()
456 switch (c->x86) { in intel_workarounds()
461 case 6: /* PII/PIII only like movsl with 8-byte alignment */ in intel_workarounds()
464 case 15: /* P4 is OK down to 8-byte alignment */ in intel_workarounds()
525 /* Broken BIOS? */ in detect_tme()
559 nr_keyids = (1UL << keyid_bits) - 1; in detect_tme()
576 c->x86_phys_bits -= keyid_bits; in detect_tme()
636 if (c->cpuid_level > 9) { in init_intel()
656 if (c->x86 == 6 && boot_cpu_has(X86_FEATURE_CLFLUSH) && in init_intel()
657 (c->x86_model == 29 || c->x86_model == 46 || c->x86_model == 47)) in init_intel()
660 if (c->x86 == 6 && boot_cpu_has(X86_FEATURE_MWAIT) && in init_intel()
661 ((c->x86_model == INTEL_FAM6_ATOM_GOLDMONT))) in init_intel()
665 if (c->x86 == 15) in init_intel()
666 c->x86_cache_alignment = c->x86_clflush_size * 2; in init_intel()
667 if (c->x86 == 6) in init_intel()
675 if (c->x86 == 6) { in init_intel()
676 unsigned int l2 = c->x86_cache_size; in init_intel()
679 switch (c->x86_model) { in init_intel()
690 else if (c->x86_stepping == 0 || c->x86_stepping == 5) in init_intel()
691 p = "Celeron-A"; in init_intel()
701 strcpy(c->x86_model_id, p); in init_intel()
704 if (c->x86 == 15) in init_intel()
706 if (c->x86 == 6) in init_intel()
710 /* Work around errata */ in init_intel()
742 if ((c->x86 == 6) && (c->x86_model == 11) && (size == 0)) in intel_size_cache()
746 * Intel Quark SoC X1000 contains a 4-way set associative in intel_size_cache()
749 if ((c->x86 == 5) && (c->x86_model == 9)) in intel_size_cache()
777 { 0x01, TLB_INST_4K, 32, " TLB_INST 4 KByte pages, 4-way set associative" },
779 { 0x03, TLB_DATA_4K, 64, " TLB_DATA 4 KByte pages, 4-way set associative" },
780 { 0x04, TLB_DATA_4M, 8, " TLB_DATA 4 MByte pages, 4-way set associative" },
781 { 0x05, TLB_DATA_4M, 32, " TLB_DATA 4 MByte pages, 4-way set associative" },
782 { 0x0b, TLB_INST_4M, 4, " TLB_INST 4 MByte pages, 4-way set associative" },
784 { 0x50, TLB_INST_ALL, 64, " TLB_INST 4 KByte and 2-MByte or 4-MByte pages" },
785 { 0x51, TLB_INST_ALL, 128, " TLB_INST 4 KByte and 2-MByte or 4-MByte pages" },
786 { 0x52, TLB_INST_ALL, 256, " TLB_INST 4 KByte and 2-MByte or 4-MByte pages" },
787 { 0x55, TLB_INST_2M_4M, 7, " TLB_INST 2-MByte or 4-MByte pages, fully associative" },
788 { 0x56, TLB_DATA0_4M, 16, " TLB_DATA0 4 MByte pages, 4-way set associative" },
789 { 0x57, TLB_DATA0_4K, 16, " TLB_DATA0 4 KByte pages, 4-way associative" },
791 { 0x5a, TLB_DATA0_2M_4M, 32, " TLB_DATA0 2-MByte or 4 MByte pages, 4-way set associative" },
796 { 0x63, TLB_DATA_1G, 4, " TLB_DATA 1 GByte pages, 4-way set associative" },
797 { 0x6b, TLB_DATA_4K, 256, " TLB_DATA 4 KByte pages, 8-way associative" },
798 { 0x6c, TLB_DATA_2M_4M, 128, " TLB_DATA 2 MByte or 4 MByte pages, 8-way associative" },
800 { 0x76, TLB_INST_2M_4M, 8, " TLB_INST 2-MByte or 4-MByte pages, fully associative" },
801 { 0xb0, TLB_INST_4K, 128, " TLB_INST 4 KByte pages, 4-way set associative" },
802 { 0xb1, TLB_INST_2M_4M, 4, " TLB_INST 2M pages, 4-way, 8 entries or 4M pages, 4-way entries" },
803 { 0xb2, TLB_INST_4K, 64, " TLB_INST 4KByte pages, 4-way set associative" },
804 { 0xb3, TLB_DATA_4K, 128, " TLB_DATA 4 KByte pages, 4-way set associative" },
805 { 0xb4, TLB_DATA_4K, 256, " TLB_DATA 4 KByte pages, 4-way associative" },
806 { 0xb5, TLB_INST_4K, 64, " TLB_INST 4 KByte pages, 8-way set associative" },
807 { 0xb6, TLB_INST_4K, 128, " TLB_INST 4 KByte pages, 8-way set associative" },
808 { 0xba, TLB_DATA_4K, 64, " TLB_DATA 4 KByte pages, 4-way associative" },
809 { 0xc0, TLB_DATA_4K_4M, 8, " TLB_DATA 4 KByte and 4 MByte pages, 4-way associative" },
810 { 0xc1, STLB_4K_2M, 1024, " STLB 4 KByte and 2 MByte pages, 8-way associative" },
811 { 0xc2, TLB_DATA_2M_4M, 16, " TLB_DATA 2 MByte/4MByte pages, 4-way associative" },
812 { 0xca, STLB_4K, 512, " STLB 4 KByte pages, 4-way associative" },
909 if (c->cpuid_level < 2) in intel_detect_tlb()
936 [0] = "486 DX-25/33",
937 [1] = "486 DX-50",
942 [7] = "486 DX/2-WB",
944 [9] = "486 DX/4-WB"
949 [0] = "Pentium 60/66 A-step",
951 [2] = "Pentium 75 - 200",
954 [7] = "Mobile Pentium 75 - 200",
961 [0] = "Pentium Pro A-step",
1122 current->comm, current->pid, ip); in split_lock_warn()
1126 * progress and set TIF_SLD so the detection is re-enabled via in split_lock_warn()
1141 current->comm, current->pid, in handle_guest_split_lock()
1144 current->thread.error_code = 0; in handle_guest_split_lock()
1145 current->thread.trap_nr = X86_TRAP_AC; in handle_guest_split_lock()
1176 if ((regs->flags & X86_EFLAGS_AC) || sld_state == sld_fatal) in handle_user_split_lock()
1178 split_lock_warn(regs->ip); in handle_user_split_lock()
1195 current->comm, current->pid, regs->ip); in handle_bus_lock()
1205 * different split-lock detection modes. It sets the MSR for the
1222 * - 0: CPU models that are known to have the per-core split-lock detection
1225 * - 1: CPU models which may enumerate IA32_CORE_CAPABILITIES and if so use
1226 * bit 5 to enumerate the per-core split-lock detection feature.
1255 switch (m->driver_data) { in split_lock_setup()
1285 … pr_info("#AC: crashing the kernel on kernel split_locks and warning on user-space split_locks\n"); in sld_state_show()
1287 pr_info("#DB: warning on user-space bus_locks\n"); in sld_state_show()
1291 …pr_info("#AC: crashing the kernel on kernel split_locks and sending SIGBUS on user-space split_loc… in sld_state_show()
1293 pr_info("#DB: sending SIGBUS on user-space bus_locks%s\n", in sld_state_show()
1295 " from non-WB" : ""); in sld_state_show()
1315 * get_this_hybrid_cpu_type() - Get the type of this hybrid CPU