42 	sld_off = 0,
59  * on CPUs that do not support SLD can cause fireworks, even when writing '0'.
94 	return 0;  in ring3mwait_disable()
104 	if (c->x86 != 6)  in probe_xeon_phi_r3mwait()
139 	{ INTEL_FAM6_KABYLAKE,		0x0B,	0x80 },
140 	{ INTEL_FAM6_KABYLAKE,		0x0A,	0x80 },
141 	{ INTEL_FAM6_KABYLAKE,		0x09,	0x80 },
142 	{ INTEL_FAM6_KABYLAKE_L,	0x0A,	0x80 },
143 	{ INTEL_FAM6_KABYLAKE_L,	0x09,	0x80 },
144 	{ INTEL_FAM6_SKYLAKE_X,		0x03,	0x0100013e },
145 	{ INTEL_FAM6_SKYLAKE_X,		0x04,	0x0200003c },
146 	{ INTEL_FAM6_BROADWELL,		0x04,	0x28 },
147 	{ INTEL_FAM6_BROADWELL_G,	0x01,	0x1b },
148 	{ INTEL_FAM6_BROADWELL_D,	0x02,	0x14 },
149 	{ INTEL_FAM6_BROADWELL_D,	0x03,	0x07000011 },
150 	{ INTEL_FAM6_BROADWELL_X,	0x01,	0x0b000025 },
151 	{ INTEL_FAM6_HASWELL_L,		0x01,	0x21 },
152 	{ INTEL_FAM6_HASWELL_G,		0x01,	0x18 },
153 	{ INTEL_FAM6_HASWELL,		0x03,	0x23 },
154 	{ INTEL_FAM6_HASWELL_X,		0x02,	0x3b },
155 	{ INTEL_FAM6_HASWELL_X,		0x04,	0x10 },
156 	{ INTEL_FAM6_IVYBRIDGE_X,	0x04,	0x42a },
158 	{ INTEL_FAM6_SANDYBRIDGE_X,	0x06,	0x61b },
159 	{ INTEL_FAM6_SANDYBRIDGE_X,	0x07,	0x712 },
173 	if (c->x86 != 6)  in bad_spectre_microcode()
176 	for (i = 0; i < ARRAY_SIZE(spectre_bad_microcodes); i++) {  in bad_spectre_microcode()
189 	if (c->x86 > 6 || (c->x86 == 6 && c->x86_model >= 0xd)) {  in early_init_intel()
191 				  MSR_IA32_MISC_ENABLE_LIMIT_CPUID_BIT) > 0) {  in early_init_intel()
192 			c->cpuid_level = cpuid_eax(0);  in early_init_intel()
197 	if ((c->x86 == 0xf && c->x86_model >= 0x03) ||  in early_init_intel()
198 		(c->x86 == 0x6 && c->x86_model >= 0x0e))  in early_init_intel()
201 	if (c->x86 >= 6 && !cpu_has(c, X86_FEATURE_IA64))  in early_init_intel()
228 	if (c->x86 == 6 && c->x86_model == 0x1c && c->x86_stepping <= 2 &&  in early_init_intel()
229 	    c->microcode < 0x20e) {  in early_init_intel()
238 	if (c->x86 == 15 && c->x86_cache_alignment == 64)  in early_init_intel()
242 	/* CPUID workaround for 0F33/0F34 CPU */  in early_init_intel()
243 	if (c->x86 == 0xF && c->x86_model == 0x3  in early_init_intel()
244 	    && (c->x86_stepping == 0x3 || c->x86_stepping == 0x4))  in early_init_intel()
260 	if (c->x86 == 6) {  in early_init_intel()
283 	if (c->x86 == 6 && c->x86_model < 15)  in early_init_intel()
290 	if (c->x86 > 6 || (c->x86 == 6 && c->x86_model >= 0xd)) {  in early_init_intel()
305 	 * As a result, boot_cpu_has(X86_FEATURE_PGE) in arch/x86/include/asm/tlbflush.h  in early_init_intel()
309 	if (c->x86 == 5 && c->x86_model == 9) {  in early_init_intel()
314 	if (c->cpuid_level >= 0x00000001) {  in early_init_intel()
317 		cpuid(0x00000001, &eax, &ebx, &ecx, &edx);  in early_init_intel()
324 			c->x86_coreid_bits = get_count_order((ebx >> 16) & 0xff);  in early_init_intel()
333 	if (detect_extended_topology_early(c) < 0)  in early_init_intel()
353 	    boot_cpu_data.x86 == 6 &&  in ppro_with_ram_bug()
359 	return 0;  in ppro_with_ram_bug()
371 	if (c->x86 == 5 &&  in intel_smp_check()
395 	 * have the F0 0F bug, which lets nonprivileged users lock up the  in intel_workarounds()
400 	if (c->x86 == 5 && c->x86_model < 9) {  in intel_workarounds()
405 			pr_notice("Intel Pentium with F0 0F bug - workaround enabled.\n");  in intel_workarounds()
415 	if ((c->x86<<8 | c->x86_model<<4 | c->x86_stepping) < 0x633)  in intel_workarounds()
433 	if ((c->x86 == 15) && (c->x86_model == 1) && (c->x86_stepping == 1)) {  in intel_workarounds()
435 				MSR_IA32_MISC_ENABLE_PREFETCH_DISABLE_BIT) > 0) {  in intel_workarounds()
447 	if (boot_cpu_has(X86_FEATURE_APIC) && (c->x86<<8 | c->x86_model<<4) == 0x520 &&  in intel_workarounds()
448 	    (c->x86_stepping < 0x6 || c->x86_stepping == 0xb))  in intel_workarounds()
456 	switch (c->x86) {  in intel_workarounds()
495 #define MSR_IA32_TME_ACTIVATE		0x982
498 #define TME_ACTIVATE_LOCKED(x)		(x & 0x1)
499 #define TME_ACTIVATE_ENABLED(x)		(x & 0x2)
501 #define TME_ACTIVATE_POLICY(x)		((x >> 4) & 0xf)	/* Bits 7:4 */
502 #define TME_ACTIVATE_POLICY_AES_XTS_128	0
504 #define TME_ACTIVATE_KEYID_BITS(x)	((x >> 32) & 0xf)	/* Bits 35:32 */
506 #define TME_ACTIVATE_CRYPTO_ALGS(x)	((x >> 48) & 0xffff)	/* Bits 63:48 */
510 #define MKTME_ENABLED			0
518 	int keyid_bits = 0, nr_keyids = 0;  in detect_tme()
519 	static u64 tme_activate_cpu0 = 0;  in detect_tme()
526 			pr_err_once("x86/tme: configuration is inconsistent between CPUs\n");  in detect_tme()
527 			pr_err_once("x86/tme: MKTME is not usable\n");  in detect_tme()
537 		pr_info_once("x86/tme: not enabled by BIOS\n");  in detect_tme()
545 	pr_info("x86/tme: enabled by BIOS\n");  in detect_tme()
549 		pr_warn("x86/tme: Unknown policy is active: %#llx\n", tme_policy);  in detect_tme()
553 		pr_err("x86/mktme: No known encryption algorithm is supported: %#llx\n",  in detect_tme()
561 		pr_info_once("x86/mktme: enabled by BIOS\n");  in detect_tme()
562 		pr_info_once("x86/mktme: %d KeyIDs available\n", nr_keyids);  in detect_tme()
564 		pr_info_once("x86/mktme: disabled by BIOS\n");  in detect_tme()
597 	this_cpu_write(msr_misc_features_shadow, 0);  in init_intel_misc_features()
625 		 * let's use the legacy cpuid vector 0x1 and 0x4 for topology  in init_intel()
639 		if ((eax & 0xff) && (((eax>>8) & 0xff) > 1))  in init_intel()
656 	if (c->x86 == 6 && boot_cpu_has(X86_FEATURE_CLFLUSH) &&  in init_intel()
660 	if (c->x86 == 6 && boot_cpu_has(X86_FEATURE_MWAIT) &&  in init_intel()
665 	if (c->x86 == 15)  in init_intel()
667 	if (c->x86 == 6)  in init_intel()
675 	if (c->x86 == 6) {  in init_intel()
681 			if (l2 == 0)  in init_intel()
690 			else if (c->x86_stepping == 0 || c->x86_stepping == 5)  in init_intel()
704 	if (c->x86 == 15)  in init_intel()
706 	if (c->x86 == 6)  in init_intel()
742 	if ((c->x86 == 6) && (c->x86_model == 11) && (size == 0))  in intel_size_cache()
749 	if ((c->x86 == 5) && (c->x86_model == 9))  in intel_size_cache()
755 #define TLB_INST_4K	0x01
756 #define TLB_INST_4M	0x02
757 #define TLB_INST_2M_4M	0x03
759 #define TLB_INST_ALL	0x05
760 #define TLB_INST_1G	0x06
762 #define TLB_DATA_4K	0x11
763 #define TLB_DATA_4M	0x12
764 #define TLB_DATA_2M_4M	0x13
765 #define TLB_DATA_4K_4M	0x14
767 #define TLB_DATA_1G	0x16
769 #define TLB_DATA0_4K	0x21
770 #define TLB_DATA0_4M	0x22
771 #define TLB_DATA0_2M_4M	0x23
773 #define STLB_4K		0x41
774 #define STLB_4K_2M	0x42
777 	{ 0x01, TLB_INST_4K,		32,	" TLB_INST 4 KByte pages, 4-way set associative" },
778 	{ 0x02, TLB_INST_4M,		2,	" TLB_INST 4 MByte pages, full associative" },
779 	{ 0x03, TLB_DATA_4K,		64,	" TLB_DATA 4 KByte pages, 4-way set associative" },
780 	{ 0x04, TLB_DATA_4M,		8,	" TLB_DATA 4 MByte pages, 4-way set associative" },
781 	{ 0x05, TLB_DATA_4M,		32,	" TLB_DATA 4 MByte pages, 4-way set associative" },
782 	{ 0x0b, TLB_INST_4M,		4,	" TLB_INST 4 MByte pages, 4-way set associative" },
783 	{ 0x4f, TLB_INST_4K,		32,	" TLB_INST 4 KByte pages" },
784 	{ 0x50, TLB_INST_ALL,		64,	" TLB_INST 4 KByte and 2-MByte or 4-MByte pages" },
785 	{ 0x51, TLB_INST_ALL,		128,	" TLB_INST 4 KByte and 2-MByte or 4-MByte pages" },
786 	{ 0x52, TLB_INST_ALL,		256,	" TLB_INST 4 KByte and 2-MByte or 4-MByte pages" },
787 	{ 0x55, TLB_INST_2M_4M,		7,	" TLB_INST 2-MByte or 4-MByte pages, fully associative" },
788 	{ 0x56, TLB_DATA0_4M,		16,	" TLB_DATA0 4 MByte pages, 4-way set associative" },
789 	{ 0x57, TLB_DATA0_4K,		16,	" TLB_DATA0 4 KByte pages, 4-way associative" },
790 	{ 0x59, TLB_DATA0_4K,		16,	" TLB_DATA0 4 KByte pages, fully associative" },
791 	{ 0x5a, TLB_DATA0_2M_4M,	32,	" TLB_DATA0 2-MByte or 4 MByte pages, 4-way set associative" },
792 	{ 0x5b, TLB_DATA_4K_4M,		64,	" TLB_DATA 4 KByte and 4 MByte pages" },
793 	{ 0x5c, TLB_DATA_4K_4M,		128,	" TLB_DATA 4 KByte and 4 MByte pages" },
794 	{ 0x5d, TLB_DATA_4K_4M,		256,	" TLB_DATA 4 KByte and 4 MByte pages" },
795 	{ 0x61, TLB_INST_4K,		48,	" TLB_INST 4 KByte pages, full associative" },
796 	{ 0x63, TLB_DATA_1G,		4,	" TLB_DATA 1 GByte pages, 4-way set associative" },
797 	{ 0x6b, TLB_DATA_4K,		256,	" TLB_DATA 4 KByte pages, 8-way associative" },
798 	{ 0x6c, TLB_DATA_2M_4M,		128,	" TLB_DATA 2 MByte or 4 MByte pages, 8-way associative" },
799 	{ 0x6d, TLB_DATA_1G,		16,	" TLB_DATA 1 GByte pages, fully associative" },
800 	{ 0x76, TLB_INST_2M_4M,		8,	" TLB_INST 2-MByte or 4-MByte pages, fully associative" },
801 	{ 0xb0, TLB_INST_4K,		128,	" TLB_INST 4 KByte pages, 4-way set associative" },
802 	{ 0xb1, TLB_INST_2M_4M,		4,	" TLB_INST 2M pages, 4-way, 8 entries or 4M pages, 4-way entries" },
803 	{ 0xb2, TLB_INST_4K,		64,	" TLB_INST 4KByte pages, 4-way set associative" },
804 	{ 0xb3, TLB_DATA_4K,		128,	" TLB_DATA 4 KByte pages, 4-way set associative" },
805 	{ 0xb4, TLB_DATA_4K,		256,	" TLB_DATA 4 KByte pages, 4-way associative" },
806 	{ 0xb5, TLB_INST_4K,		64,	" TLB_INST 4 KByte pages, 8-way set associative" },
807 	{ 0xb6, TLB_INST_4K,		128,	" TLB_INST 4 KByte pages, 8-way set associative" },
808 	{ 0xba, TLB_DATA_4K,		64,	" TLB_DATA 4 KByte pages, 4-way associative" },
809 	{ 0xc0, TLB_DATA_4K_4M,		8,	" TLB_DATA 4 KByte and 4 MByte pages, 4-way associative" },
810 	{ 0xc1, STLB_4K_2M,		1024,	" STLB 4 KByte and 2 MByte pages, 8-way associative" },
811 	{ 0xc2, TLB_DATA_2M_4M,		16,	" TLB_DATA 2 MByte/4MByte pages, 4-way associative" },
812 	{ 0xca, STLB_4K,		512,	" STLB 4 KByte pages, 4-way associative" },
813 	{ 0x00, 0, 0 }
819 	if (desc == 0)  in intel_tlb_lookup()
823 	for (k = 0; intel_tlb_table[k].descriptor != desc &&  in intel_tlb_lookup()
824 	     intel_tlb_table[k].descriptor != 0; k++)  in intel_tlb_lookup()
827 	if (intel_tlb_table[k].tlb_type == 0)  in intel_tlb_lookup()
913 	n = cpuid_eax(2) & 0xFF;  in intel_detect_tlb()
915 	for (i = 0 ; i < n ; i++) {  in intel_detect_tlb()
916 		cpuid(2, &regs[0], &regs[1], &regs[2], &regs[3]);  in intel_detect_tlb()
919 		for (j = 0 ; j < 3 ; j++)  in intel_detect_tlb()
921 				regs[j] = 0;  in intel_detect_tlb()
923 		/* Byte 0 is level count, not a descriptor */  in intel_detect_tlb()
936 			  [0] = "486 DX-25/33",
949 			  [0] = "Pentium 60/66 A-step",
961 			  [0] = "Pentium Pro A-step",
975 			  [0] = "Pentium 4 (Unknown)",
995 #define pr_fmt(fmt) "x86/split lock detection: " fmt
1021 	    ratelimit > 0 && ratelimit <= 1000) {  in match_option()
1058 	if (ret >= 0) {  in sld_state_setup()
1059 		for (i = 0; i < ARRAY_SIZE(sld_options); i++) {  in sld_state_setup()
1121 	pr_warn_ratelimited("#AC: %s/%d took a split_lock trap at address: 0x%lx\n",  in split_lock_warn()
1140 	pr_warn_once("#AC: %s/%d %s split_lock trap at address: 0x%lx\n",  in handle_guest_split_lock()
1144 	current->thread.error_code = 0;  in handle_guest_split_lock()
1194 		pr_warn_ratelimited("#DB: %s/%d took a bus_lock trap at address: 0x%lx\n",  in handle_bus_lock()
1222  * - 0: CPU models that are known to have the per-core split-lock detection
1229 	X86_MATCH_INTEL_FAM6_MODEL(ICELAKE_X,		0),
1230 	X86_MATCH_INTEL_FAM6_MODEL(ICELAKE_L,		0),
1231 	X86_MATCH_INTEL_FAM6_MODEL(ICELAKE_D,		0),
1256 	case 0:  in split_lock_setup()
1318  * a hybrid processor. If the processor is not hybrid, returns 0.
1323 		return 0;  in get_this_hybrid_cpu_type()
1325 	return cpuid_eax(0x0000001a) >> X86_HYBRID_CPU_TYPE_ID_SHIFT;  in get_this_hybrid_cpu_type()