Lines Matching +full:opp +full:- +full:level
1 // SPDX-License-Identifier: BSD-3-Clause
3 * Copyright (c) 2017-2019, The Linux Foundation. All rights reserved.
7 #include <dt-bindings/dma/qcom-gpi.h>
8 #include <dt-bindings/interrupt-controller/arm-gic.h>
9 #include <dt-bindings/power/qcom-aoss-qmp.h>
10 #include <dt-bindings/power/qcom-rpmpd.h>
11 #include <dt-bindings/soc/qcom,rpmh-rsc.h>
12 #include <dt-bindings/clock/qcom,rpmh.h>
13 #include <dt-bindings/clock/qcom,gcc-sm8150.h>
14 #include <dt-bindings/clock/qcom,gpucc-sm8150.h>
15 #include <dt-bindings/interconnect/qcom,osm-l3.h>
16 #include <dt-bindings/interconnect/qcom,sm8150.h>
17 #include <dt-bindings/thermal/thermal.h>
20 interrupt-parent = <&intc>;
22 #address-cells = <2>;
23 #size-cells = <2>;
28 xo_board: xo-board {
29 compatible = "fixed-clock";
30 #clock-cells = <0>;
31 clock-frequency = <38400000>;
32 clock-output-names = "xo_board";
35 sleep_clk: sleep-clk {
36 compatible = "fixed-clock";
37 #clock-cells = <0>;
38 clock-frequency = <32764>;
39 clock-output-names = "sleep_clk";
44 #address-cells = <2>;
45 #size-cells = <0>;
51 enable-method = "psci";
52 capacity-dmips-mhz = <488>;
53 dynamic-power-coefficient = <232>;
54 next-level-cache = <&L2_0>;
55 qcom,freq-domain = <&cpufreq_hw 0>;
56 operating-points-v2 = <&cpu0_opp_table>;
59 power-domains = <&CPU_PD0>;
60 power-domain-names = "psci";
61 #cooling-cells = <2>;
62 L2_0: l2-cache {
64 next-level-cache = <&L3_0>;
65 L3_0: l3-cache {
75 enable-method = "psci";
76 capacity-dmips-mhz = <488>;
77 dynamic-power-coefficient = <232>;
78 next-level-cache = <&L2_100>;
79 qcom,freq-domain = <&cpufreq_hw 0>;
80 operating-points-v2 = <&cpu0_opp_table>;
83 power-domains = <&CPU_PD1>;
84 power-domain-names = "psci";
85 #cooling-cells = <2>;
86 L2_100: l2-cache {
88 next-level-cache = <&L3_0>;
97 enable-method = "psci";
98 capacity-dmips-mhz = <488>;
99 dynamic-power-coefficient = <232>;
100 next-level-cache = <&L2_200>;
101 qcom,freq-domain = <&cpufreq_hw 0>;
102 operating-points-v2 = <&cpu0_opp_table>;
105 power-domains = <&CPU_PD2>;
106 power-domain-names = "psci";
107 #cooling-cells = <2>;
108 L2_200: l2-cache {
110 next-level-cache = <&L3_0>;
118 enable-method = "psci";
119 capacity-dmips-mhz = <488>;
120 dynamic-power-coefficient = <232>;
121 next-level-cache = <&L2_300>;
122 qcom,freq-domain = <&cpufreq_hw 0>;
123 operating-points-v2 = <&cpu0_opp_table>;
126 power-domains = <&CPU_PD3>;
127 power-domain-names = "psci";
128 #cooling-cells = <2>;
129 L2_300: l2-cache {
131 next-level-cache = <&L3_0>;
139 enable-method = "psci";
140 capacity-dmips-mhz = <1024>;
141 dynamic-power-coefficient = <369>;
142 next-level-cache = <&L2_400>;
143 qcom,freq-domain = <&cpufreq_hw 1>;
144 operating-points-v2 = <&cpu4_opp_table>;
147 power-domains = <&CPU_PD4>;
148 power-domain-names = "psci";
149 #cooling-cells = <2>;
150 L2_400: l2-cache {
152 next-level-cache = <&L3_0>;
160 enable-method = "psci";
161 capacity-dmips-mhz = <1024>;
162 dynamic-power-coefficient = <369>;
163 next-level-cache = <&L2_500>;
164 qcom,freq-domain = <&cpufreq_hw 1>;
165 operating-points-v2 = <&cpu4_opp_table>;
168 power-domains = <&CPU_PD5>;
169 power-domain-names = "psci";
170 #cooling-cells = <2>;
171 L2_500: l2-cache {
173 next-level-cache = <&L3_0>;
181 enable-method = "psci";
182 capacity-dmips-mhz = <1024>;
183 dynamic-power-coefficient = <369>;
184 next-level-cache = <&L2_600>;
185 qcom,freq-domain = <&cpufreq_hw 1>;
186 operating-points-v2 = <&cpu4_opp_table>;
189 power-domains = <&CPU_PD6>;
190 power-domain-names = "psci";
191 #cooling-cells = <2>;
192 L2_600: l2-cache {
194 next-level-cache = <&L3_0>;
202 enable-method = "psci";
203 capacity-dmips-mhz = <1024>;
204 dynamic-power-coefficient = <421>;
205 next-level-cache = <&L2_700>;
206 qcom,freq-domain = <&cpufreq_hw 2>;
207 operating-points-v2 = <&cpu7_opp_table>;
210 power-domains = <&CPU_PD7>;
211 power-domain-names = "psci";
212 #cooling-cells = <2>;
213 L2_700: l2-cache {
215 next-level-cache = <&L3_0>;
219 cpu-map {
255 idle-states {
256 entry-method = "psci";
258 LITTLE_CPU_SLEEP_0: cpu-sleep-0-0 {
259 compatible = "arm,idle-state";
260 idle-state-name = "little-rail-power-collapse";
261 arm,psci-suspend-param = <0x40000004>;
262 entry-latency-us = <355>;
263 exit-latency-us = <909>;
264 min-residency-us = <3934>;
265 local-timer-stop;
268 BIG_CPU_SLEEP_0: cpu-sleep-1-0 {
269 compatible = "arm,idle-state";
270 idle-state-name = "big-rail-power-collapse";
271 arm,psci-suspend-param = <0x40000004>;
272 entry-latency-us = <241>;
273 exit-latency-us = <1461>;
274 min-residency-us = <4488>;
275 local-timer-stop;
279 domain-idle-states {
280 CLUSTER_SLEEP_0: cluster-sleep-0 {
281 compatible = "domain-idle-state";
282 idle-state-name = "cluster-power-collapse";
283 arm,psci-suspend-param = <0x4100c244>;
284 entry-latency-us = <3263>;
285 exit-latency-us = <6562>;
286 min-residency-us = <9987>;
287 local-timer-stop;
293 compatible = "operating-points-v2";
294 opp-shared;
296 cpu0_opp1: opp-300000000 {
297 opp-hz = /bits/ 64 <300000000>;
298 opp-peak-kBps = <800000 9600000>;
301 cpu0_opp2: opp-403200000 {
302 opp-hz = /bits/ 64 <403200000>;
303 opp-peak-kBps = <800000 9600000>;
306 cpu0_opp3: opp-499200000 {
307 opp-hz = /bits/ 64 <499200000>;
308 opp-peak-kBps = <800000 12902400>;
311 cpu0_opp4: opp-576000000 {
312 opp-hz = /bits/ 64 <576000000>;
313 opp-peak-kBps = <800000 12902400>;
316 cpu0_opp5: opp-672000000 {
317 opp-hz = /bits/ 64 <672000000>;
318 opp-peak-kBps = <800000 15974400>;
321 cpu0_opp6: opp-768000000 {
322 opp-hz = /bits/ 64 <768000000>;
323 opp-peak-kBps = <1804000 19660800>;
326 cpu0_opp7: opp-844800000 {
327 opp-hz = /bits/ 64 <844800000>;
328 opp-peak-kBps = <1804000 19660800>;
331 cpu0_opp8: opp-940800000 {
332 opp-hz = /bits/ 64 <940800000>;
333 opp-peak-kBps = <1804000 22732800>;
336 cpu0_opp9: opp-1036800000 {
337 opp-hz = /bits/ 64 <1036800000>;
338 opp-peak-kBps = <1804000 22732800>;
341 cpu0_opp10: opp-1113600000 {
342 opp-hz = /bits/ 64 <1113600000>;
343 opp-peak-kBps = <2188000 25804800>;
346 cpu0_opp11: opp-1209600000 {
347 opp-hz = /bits/ 64 <1209600000>;
348 opp-peak-kBps = <2188000 31948800>;
351 cpu0_opp12: opp-1305600000 {
352 opp-hz = /bits/ 64 <1305600000>;
353 opp-peak-kBps = <3072000 31948800>;
356 cpu0_opp13: opp-1382400000 {
357 opp-hz = /bits/ 64 <1382400000>;
358 opp-peak-kBps = <3072000 31948800>;
361 cpu0_opp14: opp-1478400000 {
362 opp-hz = /bits/ 64 <1478400000>;
363 opp-peak-kBps = <3072000 31948800>;
366 cpu0_opp15: opp-1555200000 {
367 opp-hz = /bits/ 64 <1555200000>;
368 opp-peak-kBps = <3072000 40550400>;
371 cpu0_opp16: opp-1632000000 {
372 opp-hz = /bits/ 64 <1632000000>;
373 opp-peak-kBps = <3072000 40550400>;
376 cpu0_opp17: opp-1708800000 {
377 opp-hz = /bits/ 64 <1708800000>;
378 opp-peak-kBps = <3072000 43008000>;
381 cpu0_opp18: opp-1785600000 {
382 opp-hz = /bits/ 64 <1785600000>;
383 opp-peak-kBps = <3072000 43008000>;
388 compatible = "operating-points-v2";
389 opp-shared;
391 cpu4_opp1: opp-710400000 {
392 opp-hz = /bits/ 64 <710400000>;
393 opp-peak-kBps = <1804000 15974400>;
396 cpu4_opp2: opp-825600000 {
397 opp-hz = /bits/ 64 <825600000>;
398 opp-peak-kBps = <2188000 19660800>;
401 cpu4_opp3: opp-940800000 {
402 opp-hz = /bits/ 64 <940800000>;
403 opp-peak-kBps = <2188000 22732800>;
406 cpu4_opp4: opp-1056000000 {
407 opp-hz = /bits/ 64 <1056000000>;
408 opp-peak-kBps = <3072000 25804800>;
411 cpu4_opp5: opp-1171200000 {
412 opp-hz = /bits/ 64 <1171200000>;
413 opp-peak-kBps = <3072000 31948800>;
416 cpu4_opp6: opp-1286400000 {
417 opp-hz = /bits/ 64 <1286400000>;
418 opp-peak-kBps = <4068000 31948800>;
421 cpu4_opp7: opp-1401600000 {
422 opp-hz = /bits/ 64 <1401600000>;
423 opp-peak-kBps = <4068000 31948800>;
426 cpu4_opp8: opp-1497600000 {
427 opp-hz = /bits/ 64 <1497600000>;
428 opp-peak-kBps = <4068000 40550400>;
431 cpu4_opp9: opp-1612800000 {
432 opp-hz = /bits/ 64 <1612800000>;
433 opp-peak-kBps = <4068000 40550400>;
436 cpu4_opp10: opp-1708800000 {
437 opp-hz = /bits/ 64 <1708800000>;
438 opp-peak-kBps = <4068000 43008000>;
441 cpu4_opp11: opp-1804800000 {
442 opp-hz = /bits/ 64 <1804800000>;
443 opp-peak-kBps = <6220000 43008000>;
446 cpu4_opp12: opp-1920000000 {
447 opp-hz = /bits/ 64 <1920000000>;
448 opp-peak-kBps = <6220000 49152000>;
451 cpu4_opp13: opp-2016000000 {
452 opp-hz = /bits/ 64 <2016000000>;
453 opp-peak-kBps = <7216000 49152000>;
456 cpu4_opp14: opp-2131200000 {
457 opp-hz = /bits/ 64 <2131200000>;
458 opp-peak-kBps = <8368000 49152000>;
461 cpu4_opp15: opp-2227200000 {
462 opp-hz = /bits/ 64 <2227200000>;
463 opp-peak-kBps = <8368000 51609600>;
466 cpu4_opp16: opp-2323200000 {
467 opp-hz = /bits/ 64 <2323200000>;
468 opp-peak-kBps = <8368000 51609600>;
471 cpu4_opp17: opp-2419200000 {
472 opp-hz = /bits/ 64 <2419200000>;
473 opp-peak-kBps = <8368000 51609600>;
478 compatible = "operating-points-v2";
479 opp-shared;
481 cpu7_opp1: opp-825600000 {
482 opp-hz = /bits/ 64 <825600000>;
483 opp-peak-kBps = <2188000 19660800>;
486 cpu7_opp2: opp-940800000 {
487 opp-hz = /bits/ 64 <940800000>;
488 opp-peak-kBps = <2188000 22732800>;
491 cpu7_opp3: opp-1056000000 {
492 opp-hz = /bits/ 64 <1056000000>;
493 opp-peak-kBps = <3072000 25804800>;
496 cpu7_opp4: opp-1171200000 {
497 opp-hz = /bits/ 64 <1171200000>;
498 opp-peak-kBps = <3072000 31948800>;
501 cpu7_opp5: opp-1286400000 {
502 opp-hz = /bits/ 64 <1286400000>;
503 opp-peak-kBps = <4068000 31948800>;
506 cpu7_opp6: opp-1401600000 {
507 opp-hz = /bits/ 64 <1401600000>;
508 opp-peak-kBps = <4068000 31948800>;
511 cpu7_opp7: opp-1497600000 {
512 opp-hz = /bits/ 64 <1497600000>;
513 opp-peak-kBps = <4068000 40550400>;
516 cpu7_opp8: opp-1612800000 {
517 opp-hz = /bits/ 64 <1612800000>;
518 opp-peak-kBps = <4068000 40550400>;
521 cpu7_opp9: opp-1708800000 {
522 opp-hz = /bits/ 64 <1708800000>;
523 opp-peak-kBps = <4068000 43008000>;
526 cpu7_opp10: opp-1804800000 {
527 opp-hz = /bits/ 64 <1804800000>;
528 opp-peak-kBps = <6220000 43008000>;
531 cpu7_opp11: opp-1920000000 {
532 opp-hz = /bits/ 64 <1920000000>;
533 opp-peak-kBps = <6220000 49152000>;
536 cpu7_opp12: opp-2016000000 {
537 opp-hz = /bits/ 64 <2016000000>;
538 opp-peak-kBps = <7216000 49152000>;
541 cpu7_opp13: opp-2131200000 {
542 opp-hz = /bits/ 64 <2131200000>;
543 opp-peak-kBps = <8368000 49152000>;
546 cpu7_opp14: opp-2227200000 {
547 opp-hz = /bits/ 64 <2227200000>;
548 opp-peak-kBps = <8368000 51609600>;
551 cpu7_opp15: opp-2323200000 {
552 opp-hz = /bits/ 64 <2323200000>;
553 opp-peak-kBps = <8368000 51609600>;
556 cpu7_opp16: opp-2419200000 {
557 opp-hz = /bits/ 64 <2419200000>;
558 opp-peak-kBps = <8368000 51609600>;
561 cpu7_opp17: opp-2534400000 {
562 opp-hz = /bits/ 64 <2534400000>;
563 opp-peak-kBps = <8368000 51609600>;
566 cpu7_opp18: opp-2649600000 {
567 opp-hz = /bits/ 64 <2649600000>;
568 opp-peak-kBps = <8368000 51609600>;
571 cpu7_opp19: opp-2745600000 {
572 opp-hz = /bits/ 64 <2745600000>;
573 opp-peak-kBps = <8368000 51609600>;
576 cpu7_opp20: opp-2841600000 {
577 opp-hz = /bits/ 64 <2841600000>;
578 opp-peak-kBps = <8368000 51609600>;
584 compatible = "qcom,scm-sm8150", "qcom,scm";
585 #reset-cells = <1>;
590 compatible = "qcom,tcsr-mutex";
592 #hwlock-cells = <1>;
602 compatible = "arm,armv8-pmuv3";
607 compatible = "arm,psci-1.0";
611 #power-domain-cells = <0>;
612 power-domains = <&CLUSTER_PD>;
613 domain-idle-states = <&LITTLE_CPU_SLEEP_0>;
617 #power-domain-cells = <0>;
618 power-domains = <&CLUSTER_PD>;
619 domain-idle-states = <&LITTLE_CPU_SLEEP_0>;
623 #power-domain-cells = <0>;
624 power-domains = <&CLUSTER_PD>;
625 domain-idle-states = <&LITTLE_CPU_SLEEP_0>;
629 #power-domain-cells = <0>;
630 power-domains = <&CLUSTER_PD>;
631 domain-idle-states = <&LITTLE_CPU_SLEEP_0>;
635 #power-domain-cells = <0>;
636 power-domains = <&CLUSTER_PD>;
637 domain-idle-states = <&BIG_CPU_SLEEP_0>;
641 #power-domain-cells = <0>;
642 power-domains = <&CLUSTER_PD>;
643 domain-idle-states = <&BIG_CPU_SLEEP_0>;
647 #power-domain-cells = <0>;
648 power-domains = <&CLUSTER_PD>;
649 domain-idle-states = <&BIG_CPU_SLEEP_0>;
653 #power-domain-cells = <0>;
654 power-domains = <&CLUSTER_PD>;
655 domain-idle-states = <&BIG_CPU_SLEEP_0>;
658 CLUSTER_PD: cpu-cluster0 {
659 #power-domain-cells = <0>;
660 domain-idle-states = <&CLUSTER_SLEEP_0>;
664 reserved-memory {
665 #address-cells = <2>;
666 #size-cells = <2>;
671 no-map;
676 no-map;
681 no-map;
685 compatible = "qcom,cmd-db";
687 no-map;
692 no-map;
697 no-map;
701 compatible = "qcom,rmtfs-mem";
703 no-map;
705 qcom,client-id = <1>;
711 no-map;
716 no-map;
721 no-map;
726 no-map;
731 no-map;
736 no-map;
741 no-map;
746 no-map;
751 no-map;
756 no-map;
761 no-map;
766 no-map;
771 no-map;
777 memory-region = <&smem_mem>;
781 smp2p-cdsp {
789 qcom,local-pid = <0>;
790 qcom,remote-pid = <5>;
792 cdsp_smp2p_out: master-kernel {
793 qcom,entry-name = "master-kernel";
794 #qcom,smem-state-cells = <1>;
797 cdsp_smp2p_in: slave-kernel {
798 qcom,entry-name = "slave-kernel";
800 interrupt-controller;
801 #interrupt-cells = <2>;
805 smp2p-lpass {
813 qcom,local-pid = <0>;
814 qcom,remote-pid = <2>;
816 adsp_smp2p_out: master-kernel {
817 qcom,entry-name = "master-kernel";
818 #qcom,smem-state-cells = <1>;
821 adsp_smp2p_in: slave-kernel {
822 qcom,entry-name = "slave-kernel";
824 interrupt-controller;
825 #interrupt-cells = <2>;
829 smp2p-mpss {
837 qcom,local-pid = <0>;
838 qcom,remote-pid = <1>;
840 modem_smp2p_out: master-kernel {
841 qcom,entry-name = "master-kernel";
842 #qcom,smem-state-cells = <1>;
845 modem_smp2p_in: slave-kernel {
846 qcom,entry-name = "slave-kernel";
848 interrupt-controller;
849 #interrupt-cells = <2>;
853 smp2p-slpi {
861 qcom,local-pid = <0>;
862 qcom,remote-pid = <3>;
864 slpi_smp2p_out: master-kernel {
865 qcom,entry-name = "master-kernel";
866 #qcom,smem-state-cells = <1>;
869 slpi_smp2p_in: slave-kernel {
870 qcom,entry-name = "slave-kernel";
872 interrupt-controller;
873 #interrupt-cells = <2>;
878 #address-cells = <2>;
879 #size-cells = <2>;
881 dma-ranges = <0 0 0 0 0x10 0>;
882 compatible = "simple-bus";
884 gcc: clock-controller@100000 {
885 compatible = "qcom,gcc-sm8150";
887 #clock-cells = <1>;
888 #reset-cells = <1>;
889 #power-domain-cells = <1>;
890 clock-names = "bi_tcxo",
896 gpi_dma0: dma-controller@800000 {
897 compatible = "qcom,sm8150-gpi-dma";
912 dma-channels = <13>;
913 dma-channel-mask = <0xfa>;
915 #dma-cells = <3>;
920 compatible = "qcom,geni-se-qup";
922 clock-names = "m-ahb", "s-ahb";
926 #address-cells = <2>;
927 #size-cells = <2>;
932 compatible = "qcom,geni-i2c";
934 clock-names = "se";
936 pinctrl-names = "default";
937 pinctrl-0 = <&qup_i2c0_default>;
939 #address-cells = <1>;
940 #size-cells = <0>;
945 compatible = "qcom,geni-spi";
947 reg-names = "se";
948 clock-names = "se";
950 pinctrl-names = "default";
951 pinctrl-0 = <&qup_spi0_default>;
953 spi-max-frequency = <50000000>;
954 #address-cells = <1>;
955 #size-cells = <0>;
960 compatible = "qcom,geni-i2c";
962 clock-names = "se";
964 pinctrl-names = "default";
965 pinctrl-0 = <&qup_i2c1_default>;
967 #address-cells = <1>;
968 #size-cells = <0>;
973 compatible = "qcom,geni-spi";
975 reg-names = "se";
976 clock-names = "se";
978 pinctrl-names = "default";
979 pinctrl-0 = <&qup_spi1_default>;
981 spi-max-frequency = <50000000>;
982 #address-cells = <1>;
983 #size-cells = <0>;
988 compatible = "qcom,geni-i2c";
990 clock-names = "se";
992 pinctrl-names = "default";
993 pinctrl-0 = <&qup_i2c2_default>;
995 #address-cells = <1>;
996 #size-cells = <0>;
1001 compatible = "qcom,geni-spi";
1003 reg-names = "se";
1004 clock-names = "se";
1006 pinctrl-names = "default";
1007 pinctrl-0 = <&qup_spi2_default>;
1009 spi-max-frequency = <50000000>;
1010 #address-cells = <1>;
1011 #size-cells = <0>;
1016 compatible = "qcom,geni-i2c";
1018 clock-names = "se";
1020 pinctrl-names = "default";
1021 pinctrl-0 = <&qup_i2c3_default>;
1023 #address-cells = <1>;
1024 #size-cells = <0>;
1029 compatible = "qcom,geni-spi";
1031 reg-names = "se";
1032 clock-names = "se";
1034 pinctrl-names = "default";
1035 pinctrl-0 = <&qup_spi3_default>;
1037 spi-max-frequency = <50000000>;
1038 #address-cells = <1>;
1039 #size-cells = <0>;
1044 compatible = "qcom,geni-i2c";
1046 clock-names = "se";
1048 pinctrl-names = "default";
1049 pinctrl-0 = <&qup_i2c4_default>;
1051 #address-cells = <1>;
1052 #size-cells = <0>;
1057 compatible = "qcom,geni-spi";
1059 reg-names = "se";
1060 clock-names = "se";
1062 pinctrl-names = "default";
1063 pinctrl-0 = <&qup_spi4_default>;
1065 spi-max-frequency = <50000000>;
1066 #address-cells = <1>;
1067 #size-cells = <0>;
1072 compatible = "qcom,geni-i2c";
1074 clock-names = "se";
1076 pinctrl-names = "default";
1077 pinctrl-0 = <&qup_i2c5_default>;
1079 #address-cells = <1>;
1080 #size-cells = <0>;
1085 compatible = "qcom,geni-spi";
1087 reg-names = "se";
1088 clock-names = "se";
1090 pinctrl-names = "default";
1091 pinctrl-0 = <&qup_spi5_default>;
1093 spi-max-frequency = <50000000>;
1094 #address-cells = <1>;
1095 #size-cells = <0>;
1100 compatible = "qcom,geni-i2c";
1102 clock-names = "se";
1104 pinctrl-names = "default";
1105 pinctrl-0 = <&qup_i2c6_default>;
1107 #address-cells = <1>;
1108 #size-cells = <0>;
1113 compatible = "qcom,geni-spi";
1115 reg-names = "se";
1116 clock-names = "se";
1118 pinctrl-names = "default";
1119 pinctrl-0 = <&qup_spi6_default>;
1121 spi-max-frequency = <50000000>;
1122 #address-cells = <1>;
1123 #size-cells = <0>;
1128 compatible = "qcom,geni-i2c";
1130 clock-names = "se";
1132 pinctrl-names = "default";
1133 pinctrl-0 = <&qup_i2c7_default>;
1135 #address-cells = <1>;
1136 #size-cells = <0>;
1141 compatible = "qcom,geni-spi";
1143 reg-names = "se";
1144 clock-names = "se";
1146 pinctrl-names = "default";
1147 pinctrl-0 = <&qup_spi7_default>;
1149 spi-max-frequency = <50000000>;
1150 #address-cells = <1>;
1151 #size-cells = <0>;
1156 gpi_dma1: dma-controller@a00000 {
1157 compatible = "qcom,sm8150-gpi-dma";
1172 dma-channels = <13>;
1173 dma-channel-mask = <0xfa>;
1175 #dma-cells = <3>;
1180 compatible = "qcom,geni-se-qup";
1182 clock-names = "m-ahb", "s-ahb";
1186 #address-cells = <2>;
1187 #size-cells = <2>;
1192 compatible = "qcom,geni-i2c";
1194 clock-names = "se";
1196 pinctrl-names = "default";
1197 pinctrl-0 = <&qup_i2c8_default>;
1199 #address-cells = <1>;
1200 #size-cells = <0>;
1205 compatible = "qcom,geni-spi";
1207 reg-names = "se";
1208 clock-names = "se";
1210 pinctrl-names = "default";
1211 pinctrl-0 = <&qup_spi8_default>;
1213 spi-max-frequency = <50000000>;
1214 #address-cells = <1>;
1215 #size-cells = <0>;
1220 compatible = "qcom,geni-i2c";
1222 clock-names = "se";
1224 pinctrl-names = "default";
1225 pinctrl-0 = <&qup_i2c9_default>;
1227 #address-cells = <1>;
1228 #size-cells = <0>;
1233 compatible = "qcom,geni-spi";
1235 reg-names = "se";
1236 clock-names = "se";
1238 pinctrl-names = "default";
1239 pinctrl-0 = <&qup_spi9_default>;
1241 spi-max-frequency = <50000000>;
1242 #address-cells = <1>;
1243 #size-cells = <0>;
1248 compatible = "qcom,geni-i2c";
1250 clock-names = "se";
1252 pinctrl-names = "default";
1253 pinctrl-0 = <&qup_i2c10_default>;
1255 #address-cells = <1>;
1256 #size-cells = <0>;
1261 compatible = "qcom,geni-spi";
1263 reg-names = "se";
1264 clock-names = "se";
1266 pinctrl-names = "default";
1267 pinctrl-0 = <&qup_spi10_default>;
1269 spi-max-frequency = <50000000>;
1270 #address-cells = <1>;
1271 #size-cells = <0>;
1276 compatible = "qcom,geni-i2c";
1278 clock-names = "se";
1280 pinctrl-names = "default";
1281 pinctrl-0 = <&qup_i2c11_default>;
1283 #address-cells = <1>;
1284 #size-cells = <0>;
1289 compatible = "qcom,geni-spi";
1291 reg-names = "se";
1292 clock-names = "se";
1294 pinctrl-names = "default";
1295 pinctrl-0 = <&qup_spi11_default>;
1297 spi-max-frequency = <50000000>;
1298 #address-cells = <1>;
1299 #size-cells = <0>;
1304 compatible = "qcom,geni-debug-uart";
1306 clock-names = "se";
1313 compatible = "qcom,geni-i2c";
1315 clock-names = "se";
1317 pinctrl-names = "default";
1318 pinctrl-0 = <&qup_i2c12_default>;
1320 #address-cells = <1>;
1321 #size-cells = <0>;
1326 compatible = "qcom,geni-spi";
1328 reg-names = "se";
1329 clock-names = "se";
1331 pinctrl-names = "default";
1332 pinctrl-0 = <&qup_spi12_default>;
1334 spi-max-frequency = <50000000>;
1335 #address-cells = <1>;
1336 #size-cells = <0>;
1341 compatible = "qcom,geni-i2c";
1343 clock-names = "se";
1345 pinctrl-names = "default";
1346 pinctrl-0 = <&qup_i2c16_default>;
1348 #address-cells = <1>;
1349 #size-cells = <0>;
1354 compatible = "qcom,geni-spi";
1356 reg-names = "se";
1357 clock-names = "se";
1359 pinctrl-names = "default";
1360 pinctrl-0 = <&qup_spi16_default>;
1362 spi-max-frequency = <50000000>;
1363 #address-cells = <1>;
1364 #size-cells = <0>;
1369 gpi_dma2: dma-controller@c00000 {
1370 compatible = "qcom,sm8150-gpi-dma";
1385 dma-channels = <13>;
1386 dma-channel-mask = <0xfa>;
1388 #dma-cells = <3>;
1393 compatible = "qcom,geni-se-qup";
1396 clock-names = "m-ahb", "s-ahb";
1400 #address-cells = <2>;
1401 #size-cells = <2>;
1406 compatible = "qcom,geni-i2c";
1408 clock-names = "se";
1410 pinctrl-names = "default";
1411 pinctrl-0 = <&qup_i2c17_default>;
1413 #address-cells = <1>;
1414 #size-cells = <0>;
1419 compatible = "qcom,geni-spi";
1421 reg-names = "se";
1422 clock-names = "se";
1424 pinctrl-names = "default";
1425 pinctrl-0 = <&qup_spi17_default>;
1427 spi-max-frequency = <50000000>;
1428 #address-cells = <1>;
1429 #size-cells = <0>;
1434 compatible = "qcom,geni-i2c";
1436 clock-names = "se";
1438 pinctrl-names = "default";
1439 pinctrl-0 = <&qup_i2c18_default>;
1441 #address-cells = <1>;
1442 #size-cells = <0>;
1447 compatible = "qcom,geni-spi";
1449 reg-names = "se";
1450 clock-names = "se";
1452 pinctrl-names = "default";
1453 pinctrl-0 = <&qup_spi18_default>;
1455 spi-max-frequency = <50000000>;
1456 #address-cells = <1>;
1457 #size-cells = <0>;
1462 compatible = "qcom,geni-i2c";
1464 clock-names = "se";
1466 pinctrl-names = "default";
1467 pinctrl-0 = <&qup_i2c19_default>;
1469 #address-cells = <1>;
1470 #size-cells = <0>;
1475 compatible = "qcom,geni-spi";
1477 reg-names = "se";
1478 clock-names = "se";
1480 pinctrl-names = "default";
1481 pinctrl-0 = <&qup_spi19_default>;
1483 spi-max-frequency = <50000000>;
1484 #address-cells = <1>;
1485 #size-cells = <0>;
1490 compatible = "qcom,geni-i2c";
1492 clock-names = "se";
1494 pinctrl-names = "default";
1495 pinctrl-0 = <&qup_i2c13_default>;
1497 #address-cells = <1>;
1498 #size-cells = <0>;
1503 compatible = "qcom,geni-spi";
1505 reg-names = "se";
1506 clock-names = "se";
1508 pinctrl-names = "default";
1509 pinctrl-0 = <&qup_spi13_default>;
1511 spi-max-frequency = <50000000>;
1512 #address-cells = <1>;
1513 #size-cells = <0>;
1518 compatible = "qcom,geni-i2c";
1520 clock-names = "se";
1522 pinctrl-names = "default";
1523 pinctrl-0 = <&qup_i2c14_default>;
1525 #address-cells = <1>;
1526 #size-cells = <0>;
1531 compatible = "qcom,geni-spi";
1533 reg-names = "se";
1534 clock-names = "se";
1536 pinctrl-names = "default";
1537 pinctrl-0 = <&qup_spi14_default>;
1539 spi-max-frequency = <50000000>;
1540 #address-cells = <1>;
1541 #size-cells = <0>;
1546 compatible = "qcom,geni-i2c";
1548 clock-names = "se";
1550 pinctrl-names = "default";
1551 pinctrl-0 = <&qup_i2c15_default>;
1553 #address-cells = <1>;
1554 #size-cells = <0>;
1559 compatible = "qcom,geni-spi";
1561 reg-names = "se";
1562 clock-names = "se";
1564 pinctrl-names = "default";
1565 pinctrl-0 = <&qup_spi15_default>;
1567 spi-max-frequency = <50000000>;
1568 #address-cells = <1>;
1569 #size-cells = <0>;
1575 compatible = "qcom,sm8150-config-noc";
1577 #interconnect-cells = <1>;
1578 qcom,bcm-voters = <&apps_bcm_voter>;
1582 compatible = "qcom,sm8150-system-noc";
1584 #interconnect-cells = <1>;
1585 qcom,bcm-voters = <&apps_bcm_voter>;
1589 compatible = "qcom,sm8150-mc-virt";
1591 #interconnect-cells = <1>;
1592 qcom,bcm-voters = <&apps_bcm_voter>;
1596 compatible = "qcom,sm8150-aggre1-noc";
1598 #interconnect-cells = <1>;
1599 qcom,bcm-voters = <&apps_bcm_voter>;
1603 compatible = "qcom,sm8150-aggre2-noc";
1605 #interconnect-cells = <1>;
1606 qcom,bcm-voters = <&apps_bcm_voter>;
1610 compatible = "qcom,sm8150-compute-noc";
1612 #interconnect-cells = <1>;
1613 qcom,bcm-voters = <&apps_bcm_voter>;
1617 compatible = "qcom,sm8150-mmss-noc";
1619 #interconnect-cells = <1>;
1620 qcom,bcm-voters = <&apps_bcm_voter>;
1623 system-cache-controller@9200000 {
1624 compatible = "qcom,sm8150-llcc";
1626 reg-names = "llcc_base", "llcc_broadcast_base";
1631 compatible = "qcom,sm8150-ufshc", "qcom,ufshc",
1632 "jedec,ufs-2.0";
1635 reg-names = "std", "ice";
1638 phy-names = "ufsphy";
1639 lanes-per-direction = <2>;
1640 #reset-cells = <1>;
1642 reset-names = "rst";
1646 clock-names =
1666 freq-table-hz =
1681 compatible = "qcom,sm8150-qmp-ufs-phy";
1683 #address-cells = <2>;
1684 #size-cells = <2>;
1686 clock-names = "ref",
1692 reset-names = "ufsphy";
1701 #phy-cells = <0>;
1706 compatible = "qcom,sm8150-ipa-virt";
1708 #interconnect-cells = <1>;
1709 qcom,bcm-voters = <&apps_bcm_voter>;
1718 compatible = "qcom,sm8150-slpi-pas";
1721 interrupts-extended = <&intc GIC_SPI 494 IRQ_TYPE_EDGE_RISING>,
1726 interrupt-names = "wdog", "fatal", "ready",
1727 "handover", "stop-ack";
1730 clock-names = "xo";
1732 power-domains = <&aoss_qmp AOSS_QMP_LS_SLPI>,
1735 power-domain-names = "load_state", "lcx", "lmx";
1737 memory-region = <&slpi_mem>;
1739 qcom,smem-states = <&slpi_smp2p_out 0>;
1740 qcom,smem-state-names = "stop";
1744 glink-edge {
1747 qcom,remote-pid = <3>;
1758 compatible = "qcom,adreno-640.1",
1761 #stream-id-cells = <16>;
1764 reg-names = "kgsl_3d0_reg_memory";
1770 operating-points-v2 = <&gpu_opp_table>;
1776 zap-shader {
1777 memory-region = <&gpu_mem>;
1781 gpu_opp_table: opp-table {
1782 compatible = "operating-points-v2";
1784 opp-675000000 {
1785 opp-hz = /bits/ 64 <675000000>;
1786 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>;
1789 opp-585000000 {
1790 opp-hz = /bits/ 64 <585000000>;
1791 opp-level = <RPMH_REGULATOR_LEVEL_NOM>;
1794 opp-499200000 {
1795 opp-hz = /bits/ 64 <499200000>;
1796 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L2>;
1799 opp-427000000 {
1800 opp-hz = /bits/ 64 <427000000>;
1801 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>;
1804 opp-345000000 {
1805 opp-hz = /bits/ 64 <345000000>;
1806 opp-level = <RPMH_REGULATOR_LEVEL_SVS>;
1809 opp-257000000 {
1810 opp-hz = /bits/ 64 <257000000>;
1811 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>;
1817 compatible="qcom,adreno-gmu-640.1", "qcom,adreno-gmu";
1822 reg-names = "gmu", "gmu_pdc", "gmu_pdc_seq";
1826 interrupt-names = "hfi", "gmu";
1833 clock-names = "ahb", "gmu", "cxo", "axi", "memnoc";
1835 power-domains = <&gpucc GPU_CX_GDSC>,
1837 power-domain-names = "cx", "gx";
1841 operating-points-v2 = <&gmu_opp_table>;
1845 gmu_opp_table: opp-table {
1846 compatible = "operating-points-v2";
1848 opp-200000000 {
1849 opp-hz = /bits/ 64 <200000000>;
1850 opp-level = <RPMH_REGULATOR_LEVEL_MIN_SVS>;
1855 gpucc: clock-controller@2c90000 {
1856 compatible = "qcom,sm8150-gpucc";
1861 clock-names = "bi_tcxo",
1864 #clock-cells = <1>;
1865 #reset-cells = <1>;
1866 #power-domain-cells = <1>;
1870 compatible = "qcom,sm8150-smmu-500", "arm,mmu-500";
1872 #iommu-cells = <2>;
1873 #global-interrupts = <1>;
1886 clock-names = "ahb", "bus", "iface";
1888 power-domains = <&gpucc GPU_CX_GDSC>;
1892 compatible = "qcom,sm8150-pinctrl";
1897 reg-names = "west", "east", "north", "south";
1899 gpio-ranges = <&tlmm 0 0 176>;
1900 gpio-controller;
1901 #gpio-cells = <2>;
1902 interrupt-controller;
1903 #interrupt-cells = <2>;
1905 qup_i2c0_default: qup-i2c0-default {
1913 drive-strength = <0x02>;
1914 bias-disable;
1918 qup_spi0_default: qup-spi0-default {
1921 drive-strength = <6>;
1922 bias-disable;
1925 qup_i2c1_default: qup-i2c1-default {
1933 drive-strength = <0x02>;
1934 bias-disable;
1938 qup_spi1_default: qup-spi1-default {
1941 drive-strength = <6>;
1942 bias-disable;
1945 qup_i2c2_default: qup-i2c2-default {
1953 drive-strength = <0x02>;
1954 bias-disable;
1958 qup_spi2_default: qup-spi2-default {
1961 drive-strength = <6>;
1962 bias-disable;
1965 qup_i2c3_default: qup-i2c3-default {
1973 drive-strength = <0x02>;
1974 bias-disable;
1978 qup_spi3_default: qup-spi3-default {
1981 drive-strength = <6>;
1982 bias-disable;
1985 qup_i2c4_default: qup-i2c4-default {
1993 drive-strength = <0x02>;
1994 bias-disable;
1998 qup_spi4_default: qup-spi4-default {
2001 drive-strength = <6>;
2002 bias-disable;
2005 qup_i2c5_default: qup-i2c5-default {
2013 drive-strength = <0x02>;
2014 bias-disable;
2018 qup_spi5_default: qup-spi5-default {
2021 drive-strength = <6>;
2022 bias-disable;
2025 qup_i2c6_default: qup-i2c6-default {
2033 drive-strength = <0x02>;
2034 bias-disable;
2038 qup_spi6_default: qup-spi6_default {
2041 drive-strength = <6>;
2042 bias-disable;
2045 qup_i2c7_default: qup-i2c7-default {
2053 drive-strength = <0x02>;
2054 bias-disable;
2058 qup_spi7_default: qup-spi7_default {
2061 drive-strength = <6>;
2062 bias-disable;
2065 qup_i2c8_default: qup-i2c8-default {
2073 drive-strength = <0x02>;
2074 bias-disable;
2078 qup_spi8_default: qup-spi8-default {
2081 drive-strength = <6>;
2082 bias-disable;
2085 qup_i2c9_default: qup-i2c9-default {
2093 drive-strength = <0x02>;
2094 bias-disable;
2098 qup_spi9_default: qup-spi9-default {
2101 drive-strength = <6>;
2102 bias-disable;
2105 qup_i2c10_default: qup-i2c10-default {
2113 drive-strength = <0x02>;
2114 bias-disable;
2118 qup_spi10_default: qup-spi10-default {
2121 drive-strength = <6>;
2122 bias-disable;
2125 qup_i2c11_default: qup-i2c11-default {
2133 drive-strength = <0x02>;
2134 bias-disable;
2138 qup_spi11_default: qup-spi11-default {
2141 drive-strength = <6>;
2142 bias-disable;
2145 qup_i2c12_default: qup-i2c12-default {
2153 drive-strength = <0x02>;
2154 bias-disable;
2158 qup_spi12_default: qup-spi12-default {
2161 drive-strength = <6>;
2162 bias-disable;
2165 qup_i2c13_default: qup-i2c13-default {
2173 drive-strength = <0x02>;
2174 bias-disable;
2178 qup_spi13_default: qup-spi13-default {
2181 drive-strength = <6>;
2182 bias-disable;
2185 qup_i2c14_default: qup-i2c14-default {
2193 drive-strength = <0x02>;
2194 bias-disable;
2198 qup_spi14_default: qup-spi14-default {
2201 drive-strength = <6>;
2202 bias-disable;
2205 qup_i2c15_default: qup-i2c15-default {
2213 drive-strength = <0x02>;
2214 bias-disable;
2218 qup_spi15_default: qup-spi15-default {
2221 drive-strength = <6>;
2222 bias-disable;
2225 qup_i2c16_default: qup-i2c16-default {
2233 drive-strength = <0x02>;
2234 bias-disable;
2238 qup_spi16_default: qup-spi16-default {
2241 drive-strength = <6>;
2242 bias-disable;
2245 qup_i2c17_default: qup-i2c17-default {
2253 drive-strength = <0x02>;
2254 bias-disable;
2258 qup_spi17_default: qup-spi17-default {
2261 drive-strength = <6>;
2262 bias-disable;
2265 qup_i2c18_default: qup-i2c18-default {
2273 drive-strength = <0x02>;
2274 bias-disable;
2278 qup_spi18_default: qup-spi18-default {
2281 drive-strength = <6>;
2282 bias-disable;
2285 qup_i2c19_default: qup-i2c19-default {
2293 drive-strength = <0x02>;
2294 bias-disable;
2298 qup_spi19_default: qup-spi19-default {
2301 drive-strength = <6>;
2302 bias-disable;
2307 compatible = "qcom,sm8150-mpss-pas";
2310 interrupts-extended = <&intc GIC_SPI 266 IRQ_TYPE_EDGE_RISING>,
2316 interrupt-names = "wdog", "fatal", "ready", "handover",
2317 "stop-ack", "shutdown-ack";
2320 clock-names = "xo";
2322 power-domains = <&aoss_qmp AOSS_QMP_LS_MODEM>,
2325 power-domain-names = "load_state", "cx", "mss";
2327 memory-region = <&mpss_mem>;
2329 qcom,smem-states = <&modem_smp2p_out 0>;
2330 qcom,smem-state-names = "stop";
2334 glink-edge {
2337 qcom,remote-pid = <1>;
2343 compatible = "arm,coresight-stm", "arm,primecell";
2346 reg-names = "stm-base", "stm-stimulus-base";
2349 clock-names = "apb_pclk";
2351 out-ports {
2354 remote-endpoint = <&funnel0_in7>;
2361 compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
2365 clock-names = "apb_pclk";
2367 out-ports {
2370 remote-endpoint = <&merge_funnel_in0>;
2375 in-ports {
2376 #address-cells = <1>;
2377 #size-cells = <0>;
2382 remote-endpoint = <&stm_out>;
2389 compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
2393 clock-names = "apb_pclk";
2395 out-ports {
2398 remote-endpoint = <&merge_funnel_in1>;
2403 in-ports {
2404 #address-cells = <1>;
2405 #size-cells = <0>;
2410 remote-endpoint = <&swao_replicator_out>;
2417 compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
2421 clock-names = "apb_pclk";
2423 out-ports {
2426 remote-endpoint = <&merge_funnel_in2>;
2431 in-ports {
2432 #address-cells = <1>;
2433 #size-cells = <0>;
2438 remote-endpoint = <&apss_merge_funnel_out>;
2445 compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
2449 clock-names = "apb_pclk";
2451 out-ports {
2454 remote-endpoint = <&etf_in>;
2459 in-ports {
2460 #address-cells = <1>;
2461 #size-cells = <0>;
2466 remote-endpoint = <&funnel0_out>;
2473 remote-endpoint = <&funnel1_out>;
2480 remote-endpoint = <&funnel2_out>;
2487 compatible = "arm,coresight-dynamic-replicator", "arm,primecell";
2491 clock-names = "apb_pclk";
2493 out-ports {
2494 #address-cells = <1>;
2495 #size-cells = <0>;
2500 remote-endpoint = <&etr_in>;
2507 remote-endpoint = <&replicator1_in>;
2512 in-ports {
2515 remote-endpoint = <&etf_out>;
2522 compatible = "arm,coresight-tmc", "arm,primecell";
2526 clock-names = "apb_pclk";
2528 out-ports {
2531 remote-endpoint = <&replicator_in0>;
2536 in-ports {
2539 remote-endpoint = <&merge_funnel_out>;
2546 compatible = "arm,coresight-tmc", "arm,primecell";
2551 clock-names = "apb_pclk";
2552 arm,scatter-gather;
2554 in-ports {
2557 remote-endpoint = <&replicator_out0>;
2564 compatible = "arm,coresight-dynamic-replicator", "arm,primecell";
2568 clock-names = "apb_pclk";
2570 out-ports {
2571 #address-cells = <1>;
2572 #size-cells = <0>;
2577 remote-endpoint = <&swao_funnel_in>;
2582 in-ports {
2583 #address-cells = <1>;
2584 #size-cells = <0>;
2589 remote-endpoint = <&replicator_out1>;
2596 compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
2600 clock-names = "apb_pclk";
2602 out-ports {
2605 remote-endpoint = <&swao_etf_in>;
2610 in-ports {
2611 #address-cells = <1>;
2612 #size-cells = <0>;
2617 remote-endpoint = <&replicator1_out>;
2624 compatible = "arm,coresight-tmc", "arm,primecell";
2628 clock-names = "apb_pclk";
2630 out-ports {
2633 remote-endpoint = <&swao_replicator_in>;
2638 in-ports {
2641 remote-endpoint = <&swao_funnel_out>;
2648 compatible = "arm,coresight-dynamic-replicator", "arm,primecell";
2652 clock-names = "apb_pclk";
2653 qcom,replicator-loses-context;
2655 out-ports {
2658 remote-endpoint = <&funnel1_in4>;
2663 in-ports {
2666 remote-endpoint = <&swao_etf_out>;
2673 compatible = "arm,coresight-etm4x", "arm,primecell";
2679 clock-names = "apb_pclk";
2680 arm,coresight-loses-context-with-cpu;
2681 qcom,skip-power-up;
2683 out-ports {
2686 remote-endpoint = <&apss_funnel_in0>;
2693 compatible = "arm,coresight-etm4x", "arm,primecell";
2699 clock-names = "apb_pclk";
2700 arm,coresight-loses-context-with-cpu;
2701 qcom,skip-power-up;
2703 out-ports {
2706 remote-endpoint = <&apss_funnel_in1>;
2713 compatible = "arm,coresight-etm4x", "arm,primecell";
2719 clock-names = "apb_pclk";
2720 arm,coresight-loses-context-with-cpu;
2721 qcom,skip-power-up;
2723 out-ports {
2726 remote-endpoint = <&apss_funnel_in2>;
2733 compatible = "arm,coresight-etm4x", "arm,primecell";
2739 clock-names = "apb_pclk";
2740 arm,coresight-loses-context-with-cpu;
2741 qcom,skip-power-up;
2743 out-ports {
2746 remote-endpoint = <&apss_funnel_in3>;
2753 compatible = "arm,coresight-etm4x", "arm,primecell";
2759 clock-names = "apb_pclk";
2760 arm,coresight-loses-context-with-cpu;
2761 qcom,skip-power-up;
2763 out-ports {
2766 remote-endpoint = <&apss_funnel_in4>;
2773 compatible = "arm,coresight-etm4x", "arm,primecell";
2779 clock-names = "apb_pclk";
2780 arm,coresight-loses-context-with-cpu;
2781 qcom,skip-power-up;
2783 out-ports {
2786 remote-endpoint = <&apss_funnel_in5>;
2793 compatible = "arm,coresight-etm4x", "arm,primecell";
2799 clock-names = "apb_pclk";
2800 arm,coresight-loses-context-with-cpu;
2801 qcom,skip-power-up;
2803 out-ports {
2806 remote-endpoint = <&apss_funnel_in6>;
2813 compatible = "arm,coresight-etm4x", "arm,primecell";
2819 clock-names = "apb_pclk";
2820 arm,coresight-loses-context-with-cpu;
2821 qcom,skip-power-up;
2823 out-ports {
2826 remote-endpoint = <&apss_funnel_in7>;
2833 compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
2837 clock-names = "apb_pclk";
2839 out-ports {
2842 remote-endpoint = <&apss_merge_funnel_in>;
2847 in-ports {
2848 #address-cells = <1>;
2849 #size-cells = <0>;
2854 remote-endpoint = <&etm0_out>;
2861 remote-endpoint = <&etm1_out>;
2868 remote-endpoint = <&etm2_out>;
2875 remote-endpoint = <&etm3_out>;
2882 remote-endpoint = <&etm4_out>;
2889 remote-endpoint = <&etm5_out>;
2896 remote-endpoint = <&etm6_out>;
2903 remote-endpoint = <&etm7_out>;
2910 compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
2914 clock-names = "apb_pclk";
2916 out-ports {
2919 remote-endpoint = <&funnel2_in2>;
2924 in-ports {
2927 remote-endpoint = <&apss_funnel_out>;
2934 compatible = "qcom,sm8150-cdsp-pas";
2937 interrupts-extended = <&intc GIC_SPI 578 IRQ_TYPE_EDGE_RISING>,
2942 interrupt-names = "wdog", "fatal", "ready",
2943 "handover", "stop-ack";
2946 clock-names = "xo";
2948 power-domains = <&aoss_qmp AOSS_QMP_LS_CDSP>,
2950 power-domain-names = "load_state", "cx";
2952 memory-region = <&cdsp_mem>;
2954 qcom,smem-states = <&cdsp_smp2p_out 0>;
2955 qcom,smem-state-names = "stop";
2959 glink-edge {
2962 qcom,remote-pid = <5>;
2968 compatible = "qcom,sm8150-usb-hs-phy",
2969 "qcom,usb-snps-hs-7nm-phy";
2972 #phy-cells = <0>;
2975 clock-names = "ref";
2981 compatible = "qcom,sm8150-usb-hs-phy",
2982 "qcom,usb-snps-hs-7nm-phy";
2985 #phy-cells = <0>;
2988 clock-names = "ref";
2994 compatible = "qcom,sm8150-qmp-usb3-phy";
2997 reg-names = "reg-base", "dp_com";
2999 #address-cells = <2>;
3000 #size-cells = <2>;
3007 clock-names = "aux", "ref_clk_src", "ref", "com_aux";
3011 reset-names = "phy", "common";
3020 #clock-cells = <0>;
3021 #phy-cells = <0>;
3023 clock-names = "pipe0";
3024 clock-output-names = "usb3_phy_pipe_clk_src";
3029 compatible = "qcom,sm8150-qmp-usb3-uni-phy";
3032 #address-cells = <2>;
3033 #size-cells = <2>;
3040 clock-names = "aux", "ref_clk_src", "ref", "com_aux";
3044 reset-names = "phy", "common";
3051 #clock-cells = <0>;
3052 #phy-cells = <0>;
3054 clock-names = "pipe0";
3055 clock-output-names = "usb3_uni_phy_pipe_clk_src";
3060 compatible = "qcom,sm8150-dc-noc";
3062 #interconnect-cells = <1>;
3063 qcom,bcm-voters = <&apps_bcm_voter>;
3067 compatible = "qcom,sm8150-gem-noc";
3069 #interconnect-cells = <1>;
3070 qcom,bcm-voters = <&apps_bcm_voter>;
3074 compatible = "qcom,sm8150-dwc3", "qcom,dwc3";
3077 #address-cells = <2>;
3078 #size-cells = <2>;
3080 dma-ranges;
3088 clock-names = "cfg_noc", "core", "iface", "mock_utmi",
3091 assigned-clocks = <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>,
3093 assigned-clock-rates = <19200000>, <200000000>;
3099 interrupt-names = "hs_phy_irq", "ss_phy_irq",
3102 power-domains = <&gcc USB30_PRIM_GDSC>;
3114 phy-names = "usb2-phy", "usb3-phy";
3119 compatible = "qcom,sm8150-dwc3", "qcom,dwc3";
3122 #address-cells = <2>;
3123 #size-cells = <2>;
3125 dma-ranges;
3133 clock-names = "cfg_noc", "core", "iface", "mock_utmi",
3136 assigned-clocks = <&gcc GCC_USB30_SEC_MOCK_UTMI_CLK>,
3138 assigned-clock-rates = <19200000>, <200000000>;
3144 interrupt-names = "hs_phy_irq", "ss_phy_irq",
3147 power-domains = <&gcc USB30_SEC_GDSC>;
3159 phy-names = "usb2-phy", "usb3-phy";
3164 compatible = "qcom,sm8150-camnoc-virt";
3166 #interconnect-cells = <1>;
3167 qcom,bcm-voters = <&apps_bcm_voter>;
3170 aoss_qmp: power-controller@c300000 {
3171 compatible = "qcom,sm8150-aoss-qmp";
3176 #clock-cells = <0>;
3177 #power-domain-cells = <1>;
3180 tsens0: thermal-sensor@c263000 {
3181 compatible = "qcom,sm8150-tsens", "qcom,tsens-v2";
3187 interrupt-names = "uplow", "critical";
3188 #thermal-sensor-cells = <1>;
3191 tsens1: thermal-sensor@c265000 {
3192 compatible = "qcom,sm8150-tsens", "qcom,tsens-v2";
3198 interrupt-names = "uplow", "critical";
3199 #thermal-sensor-cells = <1>;
3203 compatible = "qcom,spmi-pmic-arb";
3209 reg-names = "core", "chnls", "obsrvr", "intr", "cnfg";
3210 interrupt-names = "periph_irq";
3214 #address-cells = <2>;
3215 #size-cells = <0>;
3216 interrupt-controller;
3217 #interrupt-cells = <4>;
3218 cell-index = <0>;
3222 compatible = "qcom,sm8150-smmu-500", "arm,mmu-500";
3224 #iommu-cells = <2>;
3225 #global-interrupts = <1>;
3310 compatible = "qcom,sm8150-adsp-pas";
3313 interrupts-extended = <&intc GIC_SPI 162 IRQ_TYPE_EDGE_RISING>,
3318 interrupt-names = "wdog", "fatal", "ready",
3319 "handover", "stop-ack";
3322 clock-names = "xo";
3324 power-domains = <&aoss_qmp AOSS_QMP_LS_LPASS>,
3326 power-domain-names = "load_state", "cx";
3328 memory-region = <&adsp_mem>;
3330 qcom,smem-states = <&adsp_smp2p_out 0>;
3331 qcom,smem-state-names = "stop";
3335 glink-edge {
3338 qcom,remote-pid = <2>;
3343 intc: interrupt-controller@17a00000 {
3344 compatible = "arm,gic-v3";
3345 interrupt-controller;
3346 #interrupt-cells = <3>;
3353 compatible = "qcom,sm8150-apss-shared";
3355 #mbox-cells = <1>;
3359 compatible = "qcom,apss-wdt-sm8150", "qcom,kpss-wdt";
3366 #address-cells = <2>;
3367 #size-cells = <2>;
3369 compatible = "arm,armv7-timer-mem";
3371 clock-frequency = <19200000>;
3374 frame-number = <0>;
3382 frame-number = <1>;
3389 frame-number = <2>;
3396 frame-number = <3>;
3403 frame-number = <4>;
3410 frame-number = <5>;
3417 frame-number = <6>;
3426 compatible = "qcom,rpmh-rsc";
3430 reg-names = "drv-0", "drv-1", "drv-2";
3434 qcom,tcs-offset = <0xd00>;
3435 qcom,drv-id = <2>;
3436 qcom,tcs-config = <ACTIVE_TCS 2>,
3441 rpmhcc: clock-controller {
3442 compatible = "qcom,sm8150-rpmh-clk";
3443 #clock-cells = <1>;
3444 clock-names = "xo";
3448 rpmhpd: power-controller {
3449 compatible = "qcom,sm8150-rpmhpd";
3450 #power-domain-cells = <1>;
3451 operating-points-v2 = <&rpmhpd_opp_table>;
3453 rpmhpd_opp_table: opp-table {
3454 compatible = "operating-points-v2";
3457 opp-level = <RPMH_REGULATOR_LEVEL_RETENTION>;
3461 opp-level = <RPMH_REGULATOR_LEVEL_MIN_SVS>;
3465 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>;
3469 opp-level = <RPMH_REGULATOR_LEVEL_SVS>;
3473 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>;
3477 opp-level = <224>;
3481 opp-level = <RPMH_REGULATOR_LEVEL_NOM>;
3485 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>;
3489 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L2>;
3493 opp-level = <RPMH_REGULATOR_LEVEL_TURBO>;
3497 opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L1>;
3503 compatible = "qcom,bcm-voter";
3508 compatible = "qcom,sm8150-osm-l3";
3512 clock-names = "xo", "alternate";
3514 #interconnect-cells = <1>;
3518 compatible = "qcom,cpufreq-hw";
3521 reg-names = "freq-domain0", "freq-domain1",
3522 "freq-domain2";
3525 clock-names = "xo", "alternate";
3527 #freq-domain-cells = <1>;
3531 compatible = "qcom,wcn3990-wifi";
3533 reg-names = "membase";
3534 memory-region = <&wlan_mem>;
3535 clock-names = "cxo_ref_clk_pin", "qdss";
3555 compatible = "arm,armv8-timer";
3562 thermal-zones {
3563 cpu0-thermal {
3564 polling-delay-passive = <250>;
3565 polling-delay = <1000>;
3567 thermal-sensors = <&tsens0 1>;
3570 cpu0_alert0: trip-point0 {
3576 cpu0_alert1: trip-point1 {
3589 cooling-maps {
3592 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3599 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3607 cpu1-thermal {
3608 polling-delay-passive = <250>;
3609 polling-delay = <1000>;
3611 thermal-sensors = <&tsens0 2>;
3614 cpu1_alert0: trip-point0 {
3620 cpu1_alert1: trip-point1 {
3633 cooling-maps {
3636 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3643 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3651 cpu2-thermal {
3652 polling-delay-passive = <250>;
3653 polling-delay = <1000>;
3655 thermal-sensors = <&tsens0 3>;
3658 cpu2_alert0: trip-point0 {
3664 cpu2_alert1: trip-point1 {
3677 cooling-maps {
3680 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3687 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3695 cpu3-thermal {
3696 polling-delay-passive = <250>;
3697 polling-delay = <1000>;
3699 thermal-sensors = <&tsens0 4>;
3702 cpu3_alert0: trip-point0 {
3708 cpu3_alert1: trip-point1 {
3721 cooling-maps {
3724 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3731 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3739 cpu4-top-thermal {
3740 polling-delay-passive = <250>;
3741 polling-delay = <1000>;
3743 thermal-sensors = <&tsens0 7>;
3746 cpu4_top_alert0: trip-point0 {
3752 cpu4_top_alert1: trip-point1 {
3765 cooling-maps {
3768 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3775 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3783 cpu5-top-thermal {
3784 polling-delay-passive = <250>;
3785 polling-delay = <1000>;
3787 thermal-sensors = <&tsens0 8>;
3790 cpu5_top_alert0: trip-point0 {
3796 cpu5_top_alert1: trip-point1 {
3809 cooling-maps {
3812 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3819 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3827 cpu6-top-thermal {
3828 polling-delay-passive = <250>;
3829 polling-delay = <1000>;
3831 thermal-sensors = <&tsens0 9>;
3834 cpu6_top_alert0: trip-point0 {
3840 cpu6_top_alert1: trip-point1 {
3853 cooling-maps {
3856 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3863 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3871 cpu7-top-thermal {
3872 polling-delay-passive = <250>;
3873 polling-delay = <1000>;
3875 thermal-sensors = <&tsens0 10>;
3878 cpu7_top_alert0: trip-point0 {
3884 cpu7_top_alert1: trip-point1 {
3897 cooling-maps {
3900 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3907 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3915 cpu4-bottom-thermal {
3916 polling-delay-passive = <250>;
3917 polling-delay = <1000>;
3919 thermal-sensors = <&tsens0 11>;
3922 cpu4_bottom_alert0: trip-point0 {
3928 cpu4_bottom_alert1: trip-point1 {
3941 cooling-maps {
3944 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3951 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3959 cpu5-bottom-thermal {
3960 polling-delay-passive = <250>;
3961 polling-delay = <1000>;
3963 thermal-sensors = <&tsens0 12>;
3966 cpu5_bottom_alert0: trip-point0 {
3972 cpu5_bottom_alert1: trip-point1 {
3985 cooling-maps {
3988 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3995 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4003 cpu6-bottom-thermal {
4004 polling-delay-passive = <250>;
4005 polling-delay = <1000>;
4007 thermal-sensors = <&tsens0 13>;
4010 cpu6_bottom_alert0: trip-point0 {
4016 cpu6_bottom_alert1: trip-point1 {
4029 cooling-maps {
4032 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4039 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4047 cpu7-bottom-thermal {
4048 polling-delay-passive = <250>;
4049 polling-delay = <1000>;
4051 thermal-sensors = <&tsens0 14>;
4054 cpu7_bottom_alert0: trip-point0 {
4060 cpu7_bottom_alert1: trip-point1 {
4073 cooling-maps {
4076 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4083 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4091 aoss0-thermal {
4092 polling-delay-passive = <250>;
4093 polling-delay = <1000>;
4095 thermal-sensors = <&tsens0 0>;
4098 aoss0_alert0: trip-point0 {
4106 cluster0-thermal {
4107 polling-delay-passive = <250>;
4108 polling-delay = <1000>;
4110 thermal-sensors = <&tsens0 5>;
4113 cluster0_alert0: trip-point0 {
4126 cluster1-thermal {
4127 polling-delay-passive = <250>;
4128 polling-delay = <1000>;
4130 thermal-sensors = <&tsens0 6>;
4133 cluster1_alert0: trip-point0 {
4146 gpu-thermal-top {
4147 polling-delay-passive = <250>;
4148 polling-delay = <1000>;
4150 thermal-sensors = <&tsens0 15>;
4153 gpu1_alert0: trip-point0 {
4161 aoss1-thermal {
4162 polling-delay-passive = <250>;
4163 polling-delay = <1000>;
4165 thermal-sensors = <&tsens1 0>;
4168 aoss1_alert0: trip-point0 {
4176 wlan-thermal {
4177 polling-delay-passive = <250>;
4178 polling-delay = <1000>;
4180 thermal-sensors = <&tsens1 1>;
4183 wlan_alert0: trip-point0 {
4191 video-thermal {
4192 polling-delay-passive = <250>;
4193 polling-delay = <1000>;
4195 thermal-sensors = <&tsens1 2>;
4198 video_alert0: trip-point0 {
4206 mem-thermal {
4207 polling-delay-passive = <250>;
4208 polling-delay = <1000>;
4210 thermal-sensors = <&tsens1 3>;
4213 mem_alert0: trip-point0 {
4221 q6-hvx-thermal {
4222 polling-delay-passive = <250>;
4223 polling-delay = <1000>;
4225 thermal-sensors = <&tsens1 4>;
4228 q6_hvx_alert0: trip-point0 {
4236 camera-thermal {
4237 polling-delay-passive = <250>;
4238 polling-delay = <1000>;
4240 thermal-sensors = <&tsens1 5>;
4243 camera_alert0: trip-point0 {
4251 compute-thermal {
4252 polling-delay-passive = <250>;
4253 polling-delay = <1000>;
4255 thermal-sensors = <&tsens1 6>;
4258 compute_alert0: trip-point0 {
4266 modem-thermal {
4267 polling-delay-passive = <250>;
4268 polling-delay = <1000>;
4270 thermal-sensors = <&tsens1 7>;
4273 modem_alert0: trip-point0 {
4281 npu-thermal {
4282 polling-delay-passive = <250>;
4283 polling-delay = <1000>;
4285 thermal-sensors = <&tsens1 8>;
4288 npu_alert0: trip-point0 {
4296 modem-vec-thermal {
4297 polling-delay-passive = <250>;
4298 polling-delay = <1000>;
4300 thermal-sensors = <&tsens1 9>;
4303 modem_vec_alert0: trip-point0 {
4311 modem-scl-thermal {
4312 polling-delay-passive = <250>;
4313 polling-delay = <1000>;
4315 thermal-sensors = <&tsens1 10>;
4318 modem_scl_alert0: trip-point0 {
4326 gpu-thermal-bottom {
4327 polling-delay-passive = <250>;
4328 polling-delay = <1000>;
4330 thermal-sensors = <&tsens1 11>;
4333 gpu2_alert0: trip-point0 {