Lines Matching +full:interconnect +full:- +full:names
1 // SPDX-License-Identifier: BSD-3-Clause
9 #include <dt-bindings/clock/qcom,gcc-sdx55.h>
10 #include <dt-bindings/clock/qcom,rpmh.h>
11 #include <dt-bindings/interconnect/qcom,sdx55.h>
12 #include <dt-bindings/interrupt-controller/arm-gic.h>
13 #include <dt-bindings/power/qcom-rpmpd.h>
14 #include <dt-bindings/soc/qcom,rpmh-rsc.h>
17 #address-cells = <1>;
18 #size-cells = <1>;
19 qcom,msm-id = <357 0x10000>, <368 0x10000>, <418 0x10000>;
20 interrupt-parent = <&intc>;
28 xo_board: xo-board {
29 compatible = "fixed-clock";
30 #clock-cells = <0>;
31 clock-frequency = <38400000>;
32 clock-output-names = "xo_board";
35 sleep_clk: sleep-clk {
36 compatible = "fixed-clock";
37 #clock-cells = <0>;
38 clock-frequency = <32000>;
41 nand_clk_dummy: nand-clk-dummy {
42 compatible = "fixed-clock";
43 #clock-cells = <0>;
44 clock-frequency = <32000>;
49 #address-cells = <1>;
50 #size-cells = <0>;
54 compatible = "arm,cortex-a7";
56 enable-method = "psci";
58 power-domains = <&rpmhpd SDX55_CX>;
59 power-domain-names = "rpmhpd";
60 operating-points-v2 = <&cpu_opp_table>;
64 cpu_opp_table: cpu-opp-table {
65 compatible = "operating-points-v2";
66 opp-shared;
68 opp-345600000 {
69 opp-hz = /bits/ 64 <345600000>;
70 required-opps = <&rpmhpd_opp_low_svs>;
73 opp-576000000 {
74 opp-hz = /bits/ 64 <576000000>;
75 required-opps = <&rpmhpd_opp_svs>;
78 opp-1094400000 {
79 opp-hz = /bits/ 64 <1094400000>;
80 required-opps = <&rpmhpd_opp_nom>;
83 opp-1555200000 {
84 opp-hz = /bits/ 64 <1555200000>;
85 required-opps = <&rpmhpd_opp_turbo>;
91 compatible = "qcom,scm-sdx55", "qcom,scm";
96 compatible = "arm,psci-1.0";
100 reserved-memory {
101 #address-cells = <1>;
102 #size-cells = <1>;
106 no-map;
111 no-map;
116 no-map;
121 no-map;
126 no-map;
131 compatible = "qcom,cmd-db";
133 no-map;
137 no-map;
142 no-map;
147 no-map;
154 memory-region = <&smem_mem>;
158 smp2p-mpss {
163 qcom,local-pid = <0>;
164 qcom,remote-pid = <1>;
166 modem_smp2p_out: master-kernel {
167 qcom,entry-name = "master-kernel";
168 #qcom,smem-state-cells = <1>;
171 modem_smp2p_in: slave-kernel {
172 qcom,entry-name = "slave-kernel";
173 interrupt-controller;
174 #interrupt-cells = <2>;
177 ipa_smp2p_out: ipa-ap-to-modem {
178 qcom,entry-name = "ipa";
179 #qcom,smem-state-cells = <1>;
182 ipa_smp2p_in: ipa-modem-to-ap {
183 qcom,entry-name = "ipa";
184 interrupt-controller;
185 #interrupt-cells = <2>;
190 #address-cells = <1>;
191 #size-cells = <1>;
193 compatible = "simple-bus";
195 gcc: clock-controller@100000 {
196 compatible = "qcom,gcc-sdx55";
198 #clock-cells = <1>;
199 #reset-cells = <1>;
200 #power-domain-cells = <1>;
201 clock-names = "bi_tcxo", "sleep_clk";
206 compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
211 clock-names = "core", "iface";
216 compatible = "qcom,usb-snps-hs-7nm-phy";
219 #phy-cells = <0>;
222 clock-names = "ref";
228 compatible = "qcom,sdx55-qmp-usb3-uni-phy";
231 #clock-cells = <1>;
232 #address-cells = <1>;
233 #size-cells = <1>;
239 clock-names = "aux", "cfg_ahb", "ref";
243 reset-names = "phy", "common";
249 #phy-cells = <0>;
250 #clock-cells = <0>;
252 clock-names = "pipe0";
253 clock-output-names = "usb3_uni_phy_pipe_clk_src";
257 mc_virt: interconnect@1100000 {
258 compatible = "qcom,sdx55-mc-virt";
260 #interconnect-cells = <1>;
261 qcom,bcm-voters = <&apps_bcm_voter>;
264 mem_noc: interconnect@9680000 {
265 compatible = "qcom,sdx55-mem-noc";
267 #interconnect-cells = <1>;
268 qcom,bcm-voters = <&apps_bcm_voter>;
271 system_noc: interconnect@162c000 {
272 compatible = "qcom,sdx55-system-noc";
274 #interconnect-cells = <1>;
275 qcom,bcm-voters = <&apps_bcm_voter>;
278 ipa_virt: interconnect@1e00000 {
279 compatible = "qcom,sdx55-ipa-virt";
281 #interconnect-cells = <1>;
282 qcom,bcm-voters = <&apps_bcm_voter>;
285 qpic_bam: dma-controller@1b04000 {
286 compatible = "qcom,bam-v1.7.0";
290 clock-names = "bam_clk";
291 #dma-cells = <1>;
293 qcom,controlled-remotely;
297 qpic_nand: nand-controller@1b30000 {
298 compatible = "qcom,sdx55-nand";
300 #address-cells = <1>;
301 #size-cells = <0>;
304 clock-names = "core", "aon";
309 dma-names = "tx", "rx", "cmd";
314 compatible = "qcom,sdx55-ipa";
321 reg-names = "ipa-reg",
322 "ipa-shared",
325 interrupts-extended = <&intc GIC_SPI 241 IRQ_TYPE_EDGE_RISING>,
329 interrupt-names = "ipa",
331 "ipa-clock-query",
332 "ipa-setup-ready";
335 clock-names = "core";
341 interconnect-names = "memory-a",
342 "memory-b",
346 qcom,smem-states = <&ipa_smp2p_out 0>,
348 qcom,smem-state-names = "ipa-clock-enabled-valid",
349 "ipa-clock-enabled";
355 compatible = "qcom,tcsr-mutex";
357 #hwlock-cells = <1>;
361 compatible = "qcom,sdx55-sdhci", "qcom,sdhci-msm-v5";
365 interrupt-names = "hc_irq", "pwr_irq";
368 clock-names = "iface", "core";
373 compatible = "qcom,sdx55-mpss-pas";
376 interrupts-extended = <&intc GIC_SPI 250 IRQ_TYPE_EDGE_RISING>,
382 interrupt-names = "wdog", "fatal", "ready", "handover",
383 "stop-ack", "shutdown-ack";
386 clock-names = "xo";
388 power-domains = <&rpmhpd SDX55_CX>,
390 power-domain-names = "cx", "mss";
392 qcom,smem-states = <&modem_smp2p_out 0>;
393 qcom,smem-state-names = "stop";
397 glink-edge {
400 qcom,remote-pid = <1>;
406 compatible = "qcom,sdx55-dwc3", "qcom,dwc3";
409 #address-cells = <1>;
410 #size-cells = <1>;
418 clock-names = "cfg_noc", "core", "iface", "mock_utmi",
421 assigned-clocks = <&gcc GCC_USB30_MOCK_UTMI_CLK>,
423 assigned-clock-rates = <19200000>, <200000000>;
429 interrupt-names = "hs_phy_irq", "ss_phy_irq",
432 power-domains = <&gcc USB30_GDSC>;
444 phy-names = "usb2-phy", "usb3-phy";
448 pdc: interrupt-controller@b210000 {
449 compatible = "qcom,sdx55-pdc", "qcom,pdc";
451 qcom,pdc-ranges = <0 179 52>;
452 #interrupt-cells = <3>;
453 interrupt-parent = <&intc>;
454 interrupt-controller;
463 compatible = "qcom,spmi-pmic-arb";
469 reg-names = "core", "chnls", "obsrvr", "intr", "cnfg";
470 interrupt-names = "periph_irq";
474 #address-cells = <2>;
475 #size-cells = <0>;
476 interrupt-controller;
477 #interrupt-cells = <4>;
478 cell-index = <0>;
482 compatible = "qcom,sdx55-pinctrl";
485 gpio-controller;
486 #gpio-cells = <2>;
487 interrupt-controller;
488 #interrupt-cells = <2>;
492 compatible = "simple-mfd";
495 #address-cells = <1>;
496 #size-cells = <1>;
500 pil-reloc@94c {
501 compatible = "qcom,pil-reloc-info";
507 compatible = "qcom,sdx55-smmu-500", "arm,mmu-500";
509 #iommu-cells = <2>;
510 #global-interrupts = <1>;
530 intc: interrupt-controller@17800000 {
531 compatible = "qcom,msm-qgic2";
532 interrupt-controller;
533 interrupt-parent = <&intc>;
534 #interrupt-cells = <3>;
540 compatible = "qcom,sdx55-a7pll";
543 clock-names = "bi_tcxo";
544 #clock-cells = <0>;
548 compatible = "qcom,sdx55-apcs-gcc", "syscon";
550 #mbox-cells = <1>;
552 clock-names = "ref", "pll", "aux";
553 #clock-cells = <0>;
557 compatible = "qcom,apss-wdt-sdx55", "qcom,kpss-wdt";
563 #address-cells = <1>;
564 #size-cells = <1>;
566 compatible = "arm,armv7-timer-mem";
568 clock-frequency = <19200000>;
571 frame-number = <0>;
579 frame-number = <1>;
586 frame-number = <2>;
593 frame-number = <3>;
600 frame-number = <4>;
607 frame-number = <5>;
614 frame-number = <6>;
621 frame-number = <7>;
629 compatible = "qcom,rpmh-rsc";
631 reg-names = "drv-0", "drv-1";
634 qcom,tcs-offset = <0xd00>;
635 qcom,drv-id = <1>;
636 qcom,tcs-config = <ACTIVE_TCS 2>, <SLEEP_TCS 2>,
639 rpmhcc: clock-controller {
640 compatible = "qcom,sdx55-rpmh-clk";
641 #clock-cells = <1>;
642 clock-names = "xo";
646 rpmhpd: power-controller {
647 compatible = "qcom,sdx55-rpmhpd";
648 #power-domain-cells = <1>;
649 operating-points-v2 = <&rpmhpd_opp_table>;
651 rpmhpd_opp_table: opp-table {
652 compatible = "operating-points-v2";
655 opp-level = <RPMH_REGULATOR_LEVEL_RETENTION>;
659 opp-level = <RPMH_REGULATOR_LEVEL_MIN_SVS>;
663 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>;
667 opp-level = <RPMH_REGULATOR_LEVEL_SVS>;
671 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>;
675 opp-level = <RPMH_REGULATOR_LEVEL_NOM>;
679 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>;
683 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L2>;
687 opp-level = <RPMH_REGULATOR_LEVEL_TURBO>;
691 opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L1>;
697 compatible = "qcom,bcm-voter";
703 compatible = "arm,armv7-timer";
708 clock-frequency = <19200000>;