Lines Matching +full:0 +full:x0c440000
19 qcom,msm-id = <357 0x10000>, <368 0x10000>, <418 0x10000>;
24 reg = <0 0>;
30 #clock-cells = <0>;
37 #clock-cells = <0>;
43 #clock-cells = <0>;
50 #size-cells = <0>;
52 cpu0: cpu@0 {
55 reg = <0x0>;
107 reg = <0x8fc00000 0x80000>;
112 reg = <0x8fc80000 0x40000>;
117 reg = <0x8fcfd000 0x1000>;
122 reg = <0x8fd00000 0x100000>;
127 reg = <0x8fe00000 0x20000>;
132 reg = <0x8fe20000 0x20000>;
138 reg = <0x8fe40000 0xc0000>;
143 reg = <0x8ff00000 0x100000>;
148 reg = <0x90000000 0x500000>;
163 qcom,local-pid = <0>;
197 reg = <0x100000 0x1f0000>;
207 reg = <0x00831000 0x200>;
217 reg = <0x00ff4000 0x114>;
219 #phy-cells = <0>;
229 reg = <0x00ff6000 0x1c0>;
246 reg = <0x00ff6200 0x170>,
247 <0x00ff6400 0x200>,
248 <0x00ff6800 0x800>;
249 #phy-cells = <0>;
250 #clock-cells = <0>;
259 reg = <0x01100000 0x400000>;
266 reg = <0x09680000 0x40000>;
273 reg = <0x0162c000 0x31200>;
280 reg = <0x01e00000 0x100000>;
287 reg = <0x01b04000 0x1c000>;
292 qcom,ee = <0>;
299 reg = <0x01b30000 0x10000>;
301 #size-cells = <0>;
306 dmas = <&qpic_bam 0>,
316 iommus = <&apps_smmu 0x5e0 0x0>,
317 <&apps_smmu 0x5e2 0x0>;
318 reg = <0x1e40000 0x7000>,
319 <0x1e50000 0x4b20>,
320 <0x1e04000 0x2c000>;
327 <&ipa_smp2p_in 0 IRQ_TYPE_EDGE_RISING>,
346 qcom,smem-states = <&ipa_smp2p_out 0>,
356 reg = <0x01f40000 0x40000>;
362 reg = <0x08804000 0x1000>;
374 reg = <0x04080000 0x4040>;
377 <&modem_smp2p_in 0 IRQ_TYPE_EDGE_RISING>,
392 qcom,smem-states = <&modem_smp2p_out 0>;
407 reg = <0x0a6f8800 0x400>;
438 reg = <0x0a600000 0xcd00>;
440 iommus = <&apps_smmu 0x1a0 0x0>;
450 reg = <0x0b210000 0x30000>;
451 qcom,pdc-ranges = <0 179 52>;
459 reg = <0x0c264000 0x1000>;
464 reg = <0x0c440000 0x0000d00>,
465 <0x0c600000 0x2000000>,
466 <0x0e600000 0x0100000>,
467 <0x0e700000 0x00a0000>,
468 <0x0c40a000 0x0000700>;
472 qcom,ee = <0>;
473 qcom,channel = <0>;
475 #size-cells = <0>;
478 cell-index = <0>;
483 reg = <0xf100000 0x300000>;
493 reg = <0x1468f000 0x1000>;
498 ranges = <0x0 0x1468f000 0x1000>;
502 reg = <0x94c 0x200>;
508 reg = <0x15000000 0x20000>;
535 reg = <0x17800000 0x1000>,
536 <0x17802000 0x1000>;
541 reg = <0x17808000 0x1000>;
544 #clock-cells = <0>;
549 reg = <0x17810000 0x2000>;
553 #clock-cells = <0>;
558 reg = <0x17817000 0x1000>;
567 reg = <0x17820000 0x1000>;
571 frame-number = <0>;
572 interrupts = <GIC_SPI 7 0x4>,
573 <GIC_SPI 6 0x4>;
574 reg = <0x17821000 0x1000>,
575 <0x17822000 0x1000>;
580 interrupts = <GIC_SPI 8 0x4>;
581 reg = <0x17823000 0x1000>;
587 interrupts = <GIC_SPI 9 0x4>;
588 reg = <0x17824000 0x1000>;
594 interrupts = <GIC_SPI 10 0x4>;
595 reg = <0x17825000 0x1000>;
601 interrupts = <GIC_SPI 11 0x4>;
602 reg = <0x17826000 0x1000>;
608 interrupts = <GIC_SPI 12 0x4>;
609 reg = <0x17827000 0x1000>;
615 interrupts = <GIC_SPI 13 0x4>;
616 reg = <0x17828000 0x1000>;
622 interrupts = <GIC_SPI 14 0x4>;
623 reg = <0x17829000 0x1000>;
630 reg = <0x17830000 0x10000>, <0x17840000 0x10000>;
631 reg-names = "drv-0", "drv-1";
634 qcom,tcs-offset = <0xd00>;